Abstract: The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer.

Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises silicon oxide; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and a substance according to formula I wherein R1, R2 and R3 are each independently selected from a C1-4 alky group; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein the substance according to formula I included in the chemical mechanical polishing composition provides an enhanced silicon oxide removal rate and an improved polishing defectivity performance; and, wherein at least some of the silicon oxide is removed from the substrate.

Abstract: The present invention provides a polishing composition for polishing copper or copper alloy, comprising: an oxidizing agent (A); at least one acids (B) selected from amino acids, carboxylic acids of 8 or less carbon atoms, or inorganic acids; a sulfonic acid (C) having an alkyl group of 8 or more carbon atoms; a fatty acid (D) having an alkyl group of 8 or more carbon atoms; and an N-substituted imidazole (E) represented by the following general formula (1). (In the formula (1), Ra, Rb, and Rc represent H or an alkyl group of 1 to 4 carbon atoms, and Rd represents a group selected from the group consisting of a benzyl group, a vinyl group, an alkyl group of 1 to 4 carbon atoms, and a group in which a portion of H of these groups has been substituted with OH or NH2.

Abstract: A method for producing a micromechanical component is proposed, a trench structure being substantially completely filled up by a first filler layer, and a first mask layer being applied on the first filler layer, on which in turn a second filler layer and a second mask layer are applied. A micromechanical component is also proposed, the first filler layer filling up the trench structure of the micromechanical component and at the same time forming a movable sensor structure.

Abstract: Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate (e.g., a copper substrate) are described herein which afford high and tunable rates of metal removal as well as low within a wafer non-uniformity values and low residue levels remaining after polishing.

Abstract: A reverse acting rupture disc is provided having a laser defined electropolished line-of-weakness recess, and an improved method of forming an electropolished line-of-weakness recess in a reverse acting rupture disc that assures full opening of the disc upon reversal. A rupture disc blank is pre-bulged, final bulged, and then provided with a layer of resist material. A laser is used to remove at least a portion of the layer of resist material corresponding to a desired line-of-weakness recess in the concave face of the bulged rupture disc. The disc is then subjected to an electropolishing operation to remove metal from the lased area of the rupture disc, thereby forming a lustrous polished line-of-weakness recess in the disc of desired configuration and of a predetermined depth that is related to material thickness.

Abstract: A method and system for fabricating an optical component are described. The method and system include providing a first planarization stopping and a second planarization stopping structure. The first planarization stopping structure has a first height and a first edge. The second planarization stopping structure has a second height different from the first height and a second edge. The first edge is separated from the second edge by a distance. The method and system also include providing an optical material. The optical material resides at least between the first edge of the first planarization stopping structure and the second edge of the second planarization stopping structure. The method and system also include planarizing the optical components. The planarization removes a portion of the optical material to form a surface between the first planarization stopping structure and the second planarization stopping structure. This surface has a curvature.

Abstract: A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.

Abstract: Semiconductor wafers are polished by a material-removing polishing process A, on both sides of the wafer, using an abrasive-free polishing pad, and a polishing agent which contains abrasive; and a material-removing polishing process B, on at least one side of the wafer, using a polishing pad with a microstructured surface containing no materials which contact the wafer which are harder than the semiconductor material, and a polishing agent is added which has a pH? to 10 and contains no substances with abrasive action. Preferred is a method for producing a semiconductor wafer, comprising the following ordered steps: separating a semiconductor single crystal into wafers; simultaneously processing both sides of the wafer by chip-removing processing; polishing the wafer, comprising a polishing process A and a polishing process B; and CMP of one side of the wafer, removing <1 ?m.

Abstract: A polishing apparatus has a polishing section (302) configured to polish a substrate and a measurement section (307) configured to measure a thickness of a film formed on the substrate. The polishing apparatus also has an interface (310) configured to input a desired thickness of a film formed on a substrate to be polished and a storage device (308a) configured to store polishing rate data on at least one past substrate therein. The polishing apparatus includes an arithmetic unit (308b) operable to calculate a polishing rate and an optimal polishing time based on the polishing rate data and the desired thickness by using a weighted average method which weights the polishing rate data on a lately polished substrate.

Abstract: A substrate polishing apparatus is provided for preventing excessive polishing and insufficient polishing, and enabling a quantitative setting of an additional polishing time. The substrate polishing apparatus comprises a mechanism for polishing a substrate to be polished; a film thickness measuring device for measuring the thickness of a thin film deposited on the substrate; an interface for entering a target thickness for the polished thin film; a storage area for preserving past polishing results; and a processing unit for calculating a polishing time and a polishing rate. The substrate polishing apparatus builds an additional polishing database for storing data acquired from the result of additional polishing in the storage area.

Abstract: Described herein are polishing apparatus, polishing formulations, and polymeric substrates for use in polishing surfaces, and related methods. The apparatus, formulations, substrates, and methods may each be used in applications involving the polishing of metal and/or metal-containing surfaces such as semiconductor wafers. The apparatus, formulations, polymeric substrates, and related methods described herein may be used without abrasives, and in some instances, without mechanical friction of a pad surface against the surface to be polished. Therefore, defects on a polished surface due to such mechanical polishing processes may be reduced.

Abstract: A heterocoagulate comprises first particles, having a particle size of at most 999 nm, on a second particle, having a particle size of at least 3 microns. The first particles comprise cerium oxide, and second particle comprises at least one member selected from the group consisting of silicon oxides, aluminum oxides and zirconium oxides.

Abstract: Methods and apparatus for reducing damage of a semiconductor donor wafer include the steps of: (a) rotating a polishing pad, rotating the semiconductor donor wafer, applying a polishing slurry to the polishing pad, and pressing the semiconductor donor wafer and the polishing pad together; and (b) rotating the polishing pad and the semiconductor donor wafer, discontinuing the application of the polishing slurry, applying a rinsing fluid to the polishing pad, and pressing the semiconductor donor wafer and the polishing pad together, wherein step (a) followed by step (b) is carried out in sequence at least two times, and at least one of the following are reduced in at least two successive intervals of step (a): (i) a pressure at which the semiconductor donor wafer and the polishing pad are pressed together, (ii) a mean particle size of an abrasive within the polishing slurry, and (iii) a concentration of the slurry in water and stabilizers.

Abstract: Disclosed is cerium oxide powder for a CMP abrasive, which can improve polishing selectivity of a silicon oxide layer to a silicon nitride layer and/or within-wafer non-uniformity (WIWNU) during chemical mechanical polishing in a semiconductor fabricating process. More particularly, the cerium oxide powder is obtained by using cerium carbonate having a hexagonal crystal structure as a precursor. Also, CMP slurry comprising the cerium oxide powder as an abrasive, and a shallow trench isolation method for a semiconductor device using the CMP slurry as polishing slurry are disclosed.

Abstract: The present invention provides an etching solution for silver or silver alloy including at one at least ammonium compound represented by the formula (1), (2) or (3) below and an oxidant: wherein each of the variables is as defined herein.

Abstract: The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal.

Abstract: A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

Abstract: A laminate for making signs, the laminate comprising a readily-abraded layer and an abrasion-resistant layer. A method of making signs is also disclosed. The method includes providing a laminate comprising a first layer that is readily etched by abrasives and a second layer disposed beneath the first layer and substantially resistant to abrasive etching. A mask is applied to the top of the laminate; and abrasives are used to selectively remove a portion of the first layer, so as to form a relief image with a controlled and uniform relief depth.

Abstract: A method and system provide a magnetoresistive structure from a magnetoresistive stack that includes a plurality of layers. The method and system include providing a mask that exposes a portion of the magnetoresistive stack. The mask has at least one side, a top, and a base at least as wide as the top. The method and system also include removing the portion of the magnetoresistive stack to define the magnetoresistive structure. The method and system further include providing an insulating layer. A portion of the insulating layer resides on the at least one side of the mask. The method and system further include removing the portion of the insulating layer on the at least one side of the mask and removing the mask.

Abstract: A method for producing a semiconductor wafer includes a number of steps in order including a bilateral material-removing process followed by rounding off an edge of the wafer and grinding front and back sides of the wafer by holding one side and grinding the other. The front and back arc then polished with a polishing cloth including bound abrasives and subsequently treated with an etching medium to carry out a material removal of no more than 1 ?m on each side. The front side is then polished using a polishing cloth including bound abrasives and the back side is simultaneously polished using a polishing cloth free of abrasives while a polish with abrasives is provided. The edge is then polished followed by polishing the back with a polishing cloth including bound abrasives and simultaneously polishing the front with a cloth free of abrasives while a polish including abrasives is provided.

Abstract: Exemplary embodiments provide methods for planarizing a semiconductor surface. In embodiments, the disclosed planarizing methods can include a chemical mechanical planarization (CMP) process using a slurry-free solution that includes hydrogen peroxide (H2O2) but is free of particles such as oxide particles. A semiconductor surface (e.g., germanium) can then be planarized to provide a desirable surface roughness. In embodiments, high-quality Group III-V materials can be formed on the planarized semiconductor surface.

Abstract: A polishing liquid for a chemical mechanical polishing of a semiconductor device includes (a) a carboxylic acid compound having one or more carboxy groups, (b) colloidal silica particles having a ? potential of ?10 mV to ?35 mV when used in the polishing liquid, (c) a benzotriazole derivative, (d) an anionic surfactant, and (e) an oxidizing agent, and the polishing liquid has a pH of from 5.0 to 8.0.

Abstract: A method for fabricating a semiconductor device through a chemical mechanical polishing (CMP) process is provided. The CMP process is performed by using a slurry. The semiconductor device fabrication method can ensure the reliability and economical efficiency of the device by performing a CMP process using a CMP slurry having a high polishing selectivity with respect to a target surface, an anti-scratch characteristic, and a high global planarization characteristic.

Abstract: A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed.

Abstract: Provided is a method for manufacturing, in a simple process, a magnetic recording medium having a distinct magnetic recording pattern formed thereon. A method for manufacturing a magnetic recording medium having a magnetically-separated magnetic recording pattern MP, the method at least including; a first step of forming a first magnetic layer 11 on a non-magnetic substrate 10; a second step of forming a resist layer 12 on the first magnetic layer 11, the resist layer 12 being patterned in correspondence with the magnetic recording pattern MP; a third step of forming a second magnetic layer 13 so as to cover a surface of the first magnetic layer 11 having the resist layer 12 formed thereon; a fourth step of removing the resist layer 12 together with the second magnetic layer 13 formed thereon; and a fifth step of partially removing the first magnetic layer 11 or partially modifying magnetic property of the first magnetic layer 11.

Abstract: A system and method is described for providing a continuous bath wetdeck process for use in the manufacture of semiconductor wafers. The invention provides a method for extending an effective working life of a chemical bath of the type that comprises a chemical bath liquid within a chemical bath container. An amount of fresh chemical is continuously added to the chemical bath liquid and an amount of chemical bath liquid is simultaneously purged from the chemical bath container. A balance is maintained between the amount of fresh chemical that is added to the chemical bath liquid and the amount of chemical bath liquid that is purged in order to maintain the effectiveness of the chemical bath liquid to clean semiconductor wafers within the chemical bath.

Abstract: A polishing mixture and related method of polishing a material wafer surface, such as silicon carbide, are disclosed. The polishing mixture comprises; an abrasive and an oxidizer mixed in an acidic solution. Alumina may be used as the abrasive and the polishing mixture may have a pH less than or equal to seven (7).

Abstract: An apparatus, system and method for removing a damaged material from a low-k dielectric film layer include identifying a control chemistry, the control chemistry configured to selectively remove the damaged material from the low-k dielectric film layer, the damaged material being in a region where a feature was formed through the low-k dielectric film layer; establishing a plurality of process parameters characterizing aspects of the damaged material to be removed and applying the control chemistry to the low-k dielectric film layer, the application of the control chemistry being defined based on the established process parameters of the damaged material, such that the damaged material is substantially removed from the areas around the feature and the areas around the feature are substantially defined by low-k characteristics of the low-k dielectric film layer.

Abstract: Methods of producing magnetic recording heads are disclosed. The methods can include providing a wafer comprising a substrate layer in which are disposed a plurality of damascene trenches. The method can further include depositing a pole material across the whole wafer, wherein the plurality of trenches are filled with the pole material. The methods can further include depositing a mask material over the pole material across the whole wafer. The methods can further include performing a first material removal process across the whole wafer to remove the mask material and a first portion of the pole material at a same material removal rate. The methods can further include performing a second material removal process to remove a second portion of the pole material above the substrate layer.

Abstract: A magnetic recording medium which does not easily cause a material containing Fe or Co to corrode is disclosed. The method for manufacturing a magnetic recording medium 122 includes a process of forming a magnetic layer 30 on a non-magnetic substrate 10, a process of forming a recessed area 65 in the magnetic layer 30, a process of forming a corrosion-resistant film 60 to cover an exposure surface 65c of the recessed area 65, and a process of forming a magnetic recording pattern made of the magnetically separated magnetic layer 30 by forming a non-magnetic layer 40 to fill in the recessed area 65.

Abstract: The invention provides a method of chemically-mechanically polishing a substrate comprising at least one layer of single crystal silicon carbide. The method utilizes a chemical-mechanical polishing composition comprising a liquid carrier, an abrasive, a catalyst comprising a transition metal composition, and an oxidizing agent.

Abstract: The invention provides chemical-mechanical polishing (CMP) compositions and methods for polishing a silicon-containing substrate. A method of the invention comprises the steps of contacting a silicon-containing substrate with a polishing pad and an aqueous CMP composition, and causing relative motion between the polishing pad and the substrate while maintaining a portion of the CMP composition in contact with the surface of the substrate to abrade at least a portion of the substrate. The CMP composition comprises a ceria abrasive, a polishing additive bearing a functional group with a pKa of about 4 to about 9, a nonionic surfactant with an hydrophilic portion and a lipophilic portion wherein the hydrophilic portion has a number average molecular weight of about 500 g/mol or higher, and an aqueous carrier, wherein the pH of the composition is 7 or less. The method reduces defects on the wafers, particularly local areas of high removal.

Abstract: Bonding of substrates including metal-dielectric patterns on a surface with the metal raised above the dielectric is disclosed. One method includes providing a first substrate having a metal-dielectric pattern on a surface thereof; providing a second substrate having a metal-dielectric pattern on a surface thereof; performing a process resulting in the metal being raised above the dielectric; cleaning the metal; and bonding the first substrate to the second substrate. A related structure is also disclosed. The bonding of raised metal provides a strong bonding medium, and good electrical and thermal connections enabling creation of three dimensional integrated structures with enhanced functionality.

Abstract: A method of passivating a CMP composition by dilution and determining the relationship between the extent of dilution and the static etch rate of copper. Such relationship may be used to control the CMP composition during the CMP polish to minimize the occurrence of dishing or other adverse planarization deficiencies in the polished copper, even in the presence of substantial levels of copper ions in the CMP composition and at the copper/CMP composition interface.

Abstract: A method of preparing a thin film on a substrate is described. The method comprises forming an ultra-thin hermetic film over a portion of a substrate using a gas cluster ion beam (GCIB), wherein the ultra-thin hermetic film has a thickness less than approximately 5 nm. The method further comprises providing a substrate in a reduced-pressure environment, and generating a GCIB in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are selected to achieve a thickness of the thin film less than about 5 nanometers (nm). The GCIB is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate according to the beam dose. By doing so, the thin film is formed on the at least a portion of the substrate to achieve the thickness desired.

Abstract: The invention provides a chemical-mechanical polishing composition comprising alpha alumina, fumed alumina, silica, an oxidizing agent that oxidizes nickel-phosphorous, oxalic acid, optionally, tartaric acid, optionally, a nonionic surfactant, optionally, a biocide, and water. The invention also provides a method of chemically-mechanically polishing a substrate comprising contacting a substrate with a polishing pad and the chemical-mechanical polishing composition, moving the polishing pad and the polishing composition relative to the substrate, and abrading at least a portion of the substrate to polish the substrate.

Abstract: A reworking method for integrated circuit devices includes the following: providing a substrate having a first base layer and a first dielectric layer formed thereon, performing a first dry etching process to remove the first dielectric layer, performing a CMP process to remove the first base layer, and sequentially reforming a second base layer and a second dielectric layer on the substrate. When certain layers on the IC device have hailed an inspection or when quality defects are found, the defective layer is removed according to the provided reworking method.

Abstract: A method and apparatus for polishing or planarizing a pre-metal dielectric layer by a chemical mechanical polishing process are provided. The method comprises providing a semiconductor substrate having feature definitions formed thereon, forming a pre-metal dielectric layer over the substrate, wherein the as-deposited pre-metal dielectric layer has an uneven surface topography, and planarizing the uneven surface topography of the pre-metal dielectric layer using chemical mechanical polishing techniques, wherein planarizing the uneven surface topography comprises polishing the pre-metal dielectric layer with a fixed abrasive polishing pad and a first polishing composition to remove a bulk portion of the pre-metal dielectric layer and achieve a first predetermined planarity, and polishing the pre-metal dielectric layer with a non-abrasive polishing pad and high selectivity slurry to remove a residual portion of the pre-metal dielectric and achieve a second predetermined planarity.

Abstract: An etching composition for preventing from leaning a capacitor contains hydrofluoric acid (HF), ammonium fluoride (NH4F), an alkyl ammonium fluoride (ReNH3F; where Re is a C1-C10 linear or branched alkyl radical), a surfactant, an alcohol compound, and water. The composition can effectively suppress the leaning phenomenon of capacitors during the formation of the capacitors, so that height of the storage node of the capacitor can be secured, capacitors with improved capacitance can be manufactured, and the process can be adapted to the production of both present and future devices.

Abstract: A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber layer such that a molar ratio of (Ga+Al)/(Ga+Al+In) is the highest at the bottom of the absorber layer and the lowest at the surface of the absorber. Within the bulk of the absorber, the molar ratio gradually changes between the bottom and the surface of the absorber. In one embodiment, the surface composition of a graded absorber layer may be modified by removing a top portion or slice of the absorber layer, where the molar ratio is low so as to expose the inner portions of the absorber layer having a higher molar ratio of graded materials.

Abstract: By creating a temperature profile across a polishing pad, a respective temperature profile may be obtained in a substrate to be polished, which may result in a respective varying removal rate across the substrate for a chemically reactive slurry material or for an electro-chemically activated polishing process. Hence, highly sensitive materials, such as material comprising low-k dielectrics, may be efficiently polished with a high degree of controllability.

Abstract: A method of machining a workpiece includes applying a fluid between a fixed abrasive component and a workpiece, followed by translation of the fixed abrasive component and the workpiece relative to each other. The fluid contains an anti-clogging agent containing a phosphorus-containing organic chemistry.

Abstract: A method of semiconductor fabrication including an etching process is provided. The method includes providing a substrate and forming a target layer on the substrate. An etchant layer is formed on the target layer. The etchant layer reacts with the target layer and etches a portion of the target layer. In an embodiment, an atomic layer of the target layer is etched. The etchant layer is then removed from the substrate. The process may be iterated any number of times to remove a desired amount of the target layer. In an embodiment, the method provides for decreased lateral etching. The etchant layer may provide for improved control in forming patterns in thin target layers such as, capping layers or high-k dielectric layers of a gate structure.

Abstract: A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile.

Abstract: Nanoimprint molds for molding a surface of a material are provided. A nanoimprint mold includes a body with a molding surface that is formed by shaped nanopillars. The nanopillars may be formed on a substrate and shaped by performing at least a first partial oxidation of the nanopillars and then removing at least a portion of the oxidized material. Once shaped, a hard substance is deposited on the nanopillars to begin forming the molding surface of the nanoimprint mold. The deposition of a hard substance is followed by the deposition of carbon nanotube on the hard substance and then the removal of the substrate and nanopillars from the molding surface.

Abstract: The invention provides a chemical-mechanical polishing composition comprising a cationic abrasive, a cationic polymer, an inorganic halide salt, and an aqueous carrier. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition. The polishing composition exhibits selectivity for removal of silicon nitride over removal of silicon oxide and polysilicon.

Abstract: The present invention is to provide a processing method for manufacturing a highly flat and highly smooth glass substrate with good productivity. A highly flat and highly smooth glass substrate is obtained with good productivity by processing of a glass substrate, which comprises a step of measuring the surface shape of the glass substrate prior to processing, a step of processing the surface of the substrate by changing a processing condition for each site (first processing step), and a step of finish-polishing the surface of the glass substrate that has been subjected to the first processing step (second processing step).

Abstract: A method for forming fine patterns in a semiconductor device includes forming a first hard mask layer over an etch target layer, forming first etch mask patterns having negative slopes over the first hard mask layer, thereby forming a resultant structure, forming a first material layer for a second etch mask over the resultant structure, performing a planarization process until the first etch mask patterns are exposed to form second etch mask patterns filled in spaces between the spacers, removing the spacers, and etching the first hard mask layer and the etch target layer using the first etch mask patterns and the second etch mask patterns.