Combined With Field Effect Transistor Structure Patents (Class 257/124)
  • Patent number: 10720363
    Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: July 21, 2020
    Assignees: IMEC vzw, Vrije Universiteit Brussel
    Inventors: Julien Ryckaert, Naoto Horiguchi, Dan Mocuta, Trong Huynh Bao
  • Patent number: 10659032
    Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: May 19, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Brian Hughes, Rongming Chu
  • Patent number: 10600907
    Abstract: A high voltage semiconductor device includes a semiconductor substrate, a first region, a second region, and an interconnection region. The first region includes an N-type first semiconductor region, an N-type drain region formed in the N-type first semiconductor region, a P-type first body region, an N-type source region formed in the P-type first body region, and a gate electrode formed between the N-type source region and the N-type drain region. The second region includes an N-type second semiconductor region, and a P-type second body region formed in the N-type second semiconductor region. The interconnection region is disposed between the first region and the second region, and includes a first insulation layer formed between the N-type first semiconductor region and the N-type second semiconductor region, a metal interconnection formed on the first insulation layer, and an isolation region formed in the substrate and disposed below the first insulation layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 24, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Young Bae Kim
  • Patent number: 10481651
    Abstract: An electronics control system includes a power control unit disposed above a graphics processing unit and thermally connected to a cooling assembly inside. The system also includes a graphics processing unit disposed below the power control unit and thermally connected to the cooling assembly, an auxiliary DC-DC converter disposed below the power control unit and thermally connected to the cooling assembly, and a cooling assembly disposed at a predetermined location and configured to simultaneously transfer heat away from a power control unit, graphics processing unit, and auxiliary DC-DC converter via fluid circulation are presented.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 19, 2019
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Ercan M. Dede, Jongwon Shin
  • Patent number: 10418471
    Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: September 17, 2019
    Assignee: Ideal Power, Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 10332876
    Abstract: A first semiconductor body including type IV semiconductor material is provided. A second semiconductor body including type III-V semiconductor material is provided. A first adhesion layer is formed on the first semiconductor body. A second adhesion layer is formed on the second semiconductor body. The first and the second semiconductor bodies are bonded together by adhering the first and the second adhesion layers to one another.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Daniel Kueck, Gilberto Curatola, Romain Esteve
  • Patent number: 10290627
    Abstract: The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: May 14, 2019
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Hailian Liang, Huyun Liu, Xiaofeng Gu, Sheng Ding
  • Patent number: 10204991
    Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xusheng Wu, Jin Ping Liu, Min-hwa Chi
  • Patent number: 10164059
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • Patent number: 10091876
    Abstract: A display device including: a display substrate including a display area configured to display an image and a pad area positioned on the periphery of the display area; a first pad part positioned above the pad area and including first pad terminals arranged in a first direction; and a printed circuit board including a base film and a second pad part positioned at one side of the base film and coupled with the first pad part, the second pad part includes first contact terminals coupled with first pad terminals, each of first contact terminals includes first contact pad terminals arranged along a first row forming a first inclination angle with the first direction, and second contact pad terminals spaced from first contact pad terminals and arranged along a second row forming a second inclination angle with the first direction.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung Yong Kim, Jeong Ho Hwang
  • Patent number: 9900002
    Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (B-TRANs) for switching. Four-terminal three-layer B-TRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. B-TRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. B-TRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: February 20, 2018
    Assignee: Ideal Power, Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 9808573
    Abstract: A device for securing and organizing tubing, such as medical venous access lines, includes a tray; a fastener attached to the tray, the fastener designed to attach the tray to another object, such as a post from an IV unit or a patient's bed; at least one tube slot built into the tray, the tube slot sized to accommodate a portion of a tube; a first strap attached to the tray proximate to the fastener; and a second strap attached to the tray proximate to the end of the tray distal from the fastener, wherein the first strap and the second strap are designed to secure the tube within the tube slot without impeding flow through the tube. The device may further include label tabs extending upwardly from the tray proximate to each tube slot.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 7, 2017
    Assignee: Busara Technologies, LLC
    Inventor: Barron Dooley
  • Patent number: 9799766
    Abstract: A high voltage transistor structure comprises a first double diffused region and a second double diffused region formed in a first well of a substrate, wherein the first and second double diffused regions are of the same conductivity as the substrate, a first drain/source region formed in the first double diffused region, a first gate electrode formed over the first well and a second drain/source region formed in the second double diffused region. The high voltage transistor structure further comprises a first spacer formed on a first side of the first gate electrode, wherein the first spacer is between the first drain/source region and the first gate electrode, a second spacer formed on a second side of the first gate electrode and a first oxide protection layer formed between the second drain/source region and the second spacer.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yu Chen, Wan-Hua Huang, Jing-Ying Chen, Kuo-Ming Wu
  • Patent number: 9704851
    Abstract: A silicon controlled rectifier, an electrostatic discharge (ESD) protection circuit including the silicon controlled rectifier and an integrated circuit including the silicon controlled rectifier or ESD protection circuit. The silicon controlled rectifier includes a first region having a first conductivity type and a second region having a second conductivity type located adjacent the first region in a semiconductor substrate. A junction is formed at a boundary between the first region and the second region. Contact regions of the first conductivity type and the second conductivity type located in each of the first region and the second region. A further contact region of the second conductivity type is located in the second region, in between the contact region of the first conductivity type and the junction. The further contact region and the contact region of the second conductivity type in the second region are connected together for biasing the second region.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: July 11, 2017
    Assignee: NXP B.V.
    Inventors: Gijs Jan De Raad, Guido Wouter Willem Quax
  • Patent number: 9660551
    Abstract: The present application teaches, inter alia, methods and circuits for operating B-TRANs (double-base bidirectional bipolar junction transistors). Base drive circuits provide high-impedance drive to the base contact region on whichever side of the device is (instantaneously) operating as the collector. (B-TRANs, unlike other bipolar junction transistors, are controlled by applied voltage, not applied current.) Control signals operate preferred drive circuits, providing diode-mode turn-on and pre-turnoff operation, and a hard ON state with a low voltage drop (the “transistor-ON” state). In some (not necessarily all) preferred embodiments, a self-synchronizing rectifier circuit provides an adjustable low voltage for the gate drive circuit. Also, in some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while monitoring the base current at that terminal, so that no more base current than necessary is applied.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: May 23, 2017
    Assignee: Ideal Power, Inc.
    Inventor: William C. Alexander
  • Patent number: 9647553
    Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 9, 2017
    Assignee: Ideal Power Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 9607978
    Abstract: A double-diffused metal oxide semiconductor (DMOS) structure is configured as an open drain output driver having electrostatic discharge (ESD) protection and a reverse voltage blocking diode inherent in the structure and without requiring metal connections for the ESD and reverse voltage blocking diode protections.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 28, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Philippe Deval, Marija Fernandez, Patrick Besseux, Rohan Braithwaite
  • Patent number: 9595516
    Abstract: A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: March 14, 2017
    Assignee: INTEL IP CORPORATION
    Inventors: Mayank Shrivastava, Christian Russ
  • Patent number: 9559244
    Abstract: A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Chun-Chieh Chuang, Hsiao-Hui Tseng, Tzu-Hsuan Hsu
  • Patent number: 9543293
    Abstract: Switching loss is reduced. A first surface of a semiconductor substrate has a portion included in an IGBT region and a portion included in a diode region. Trenches formed in the first surface include a gate trench and a boundary trench disposed between the gate trench and the diode region. A fourth layer of the semiconductor substrate is provided on the first surface and has a portion included in the diode region. The fourth layer includes a trench-covering well region that covers the deepest part of the boundary trench, a plurality of isolated well regions, and a diffusion region that connects the trench-covering well region and the isolated well regions. The diffusion region has a lower impurity concentration than that of the isolated well regions. A first electrode is in contact with the isolated well regions and away from the diffusion region.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 10, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsuo Takahashi
  • Patent number: 9431577
    Abstract: This invention relates to relates to silicon light emitting devices (SiLEDs), and its application into current Complementary Metal Oxide Semiconductor (CMOS) technology, as well into future Silicon on Insulator (SOI) technology. According to the invention, a silicon based light emitting device is designed to operate by means of avalanche carrier multiplication and emitting at the below threshold wavelength detection range for Silicon of 850 nm and such that it is compatible with CMOS silicon nitride, silicon oxi-nitride and polymer waveguide technology. This favors diverse electro-optical system applications such as electro-optical couplers, fast data transfer on and from chip, various optical interconnect configurations as well as diverse on-chip sensor, fluidic and micro-optical-mechanical sensor applications. Under particular operating conditions emissions at specific wavelengths (for example the longer wavelengths) may be favored, while in other cases tuning of the emitted radiation may be obtained.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 30, 2016
    Assignee: Tshwane University of Technology
    Inventor: Lukas Willem Snyman
  • Patent number: 9355580
    Abstract: A display device includes a display panel; and a backlight panel provided below the display panel and defining a plurality of regions. A first array of light emitting diodes (LEDs) is provided along a first direction, each LED of the first array being coupled to a first line. A driver is coupled to the first line to drive the LEDs coupled to the first line. A second array of LEDs is provided along a second direction, each LEDs of the second array being coupled to a second line. A lighting condition of the regions defined by the backlight panel is controlled by turning on or off the LEDs.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 31, 2016
    Assignee: IXYS Corporation
    Inventors: Nathan Zommer, Sam Seiichiro Ochi
  • Patent number: 9035440
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent to the package paddle; depositing a lead conductive cap on the lead, the lead conductive cap includes a nickel layer having a thickness between 2.55 ?m to 8.00 ?m deposited on the lead, a palladium layer deposited on the nickel layer, and a gold layer deposited on the palladium layer; mounting an integrated circuit over the package paddle; attaching an electrical connector between the lead conductive cap and the integrated circuit; and forming an encapsulation over the integrated circuit, a portion of the lead, and a portion of the package paddle.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: May 19, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Emmanuel Espiritu, Elizar Andres, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Publication number: 20150115313
    Abstract: In an embodiment, a semiconductor device package includes a bidirectional switch circuit. The bidirectional switch circuit includes a first semiconductor transistor mounted on a first die pad, a second semiconductor transistor mounted on a second die pad, the second die pad being separate from the first die pad, and a conductive connector extending between a source electrode of the first transistor and a source electrode of the second transistor.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: Ralf Otremba, Fabio Brucchi, Franz Stückler, Teck Sim Lee
  • Patent number: 9018674
    Abstract: A semiconductor includes a drift zone of a first conductivity type arranged between a first side and a second side of a semiconductor body. The semiconductor device further includes a first region of the first conductivity type and a second region of a second conductivity type subsequently arranged along a first direction parallel to the second side. The semiconductor device further includes an electrode at the second side adjoining the first and second regions. The semiconductor device further includes a third region of the second conductivity type arranged between the drift zone and the first region. The third region is spaced apart from the second region and from the second side.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: April 28, 2015
    Assignee: Infineon Technologies AG
    Inventors: Dorothea Werber, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze, Franz Hirler, Alexander Philippou
  • Patent number: 9012954
    Abstract: An Adjustable Field Effect Rectifier uses aspects of MOSFET structure together with an adjustment pocket or region to result in a device that functions reliably and efficiently at high voltages without significant negative resistance, while also permitting fast recovery and operation at high frequency without large electromagnetic interference.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics International B.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov
  • Patent number: 8994003
    Abstract: To provide a power MISFET using oxide semiconductor. A gate electrode, a source electrode, and a drain electrode are formed so as to interpose a semiconductor layer therebetween, and a region of the semiconductor layer where the gate electrode and the drain electrode do not overlap with each other is provided between the gate electrode and the drain electrode. The length of the region is from 0.5 ?m to 5 ?m. In such a power MISFET, a power source of 100 V or higher and a load are connected in series between the drain electrode and the source electrode, and a control signal is input to the gate electrode.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: March 31, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yasuhiko Takemura
  • Patent number: 8952744
    Abstract: A semiconductor device and an operating method for the same are provided. The semiconductor device includes a first doped region, a second doped region, a first doped contact, a second doped contact, a first doped layer, a third doped contact and a first gate structure. The first doped contact and the second doped contact are on the first doped region. The first doped contact and the second doped contact has a first PN junction therebetween. The first doped layer is under the first or second doped contact. The first doped layer and the first or second doped contact has a second PN junction therebetween. The second PN junction is adjoined with the first PN junction.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: February 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Ying-Chieh Tsai, Wing-Chor Chan, Jeng Gong
  • Patent number: 8946766
    Abstract: Bi-directional silicon controlled rectifier device structures and design structures, as well as fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 8946767
    Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Sonja Krumrey
  • Patent number: 8907373
    Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics SA
    Inventors: Philippe Galy, Jean Jimenez, Johan Bourgeat, Boris Heitz
  • Patent number: 8860079
    Abstract: Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: October 14, 2014
    Assignee: United Test and Assembly Center Ltd.
    Inventors: Catherine Bee Liang Ng, Kriangsak Sae Le, Chuen Khiang Wang, Nathapong Suthiwongsunthorn
  • Patent number: 8822274
    Abstract: A method of assembling a packaged integrated circuit (IC) includes printing a viscous dielectric polymerizable material onto a die pad of a leadframe having metal terminals positioned outside the die pad. An IC die having a top side including a plurality of bond pads is placed with its bottom side onto the viscous dielectric polymerizable material. Bond wires are wire bonded between the plurality of bond pads and the metal terminals of the leadframe.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Wan Mohd Misuari Suleiman, Azdhar Dahalan
  • Patent number: 8796729
    Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: August 5, 2014
    Assignee: Analog Devices, Inc.
    Inventors: David J Clarke, Javier Alejandro Salcedo, Brian B Moane, Juan Luo, Seamus Murnane, Kieran K Heffernan, John Twomey, Stephen Denis Heffernan, Gavin Patrick Cosgrave
  • Patent number: 8786033
    Abstract: A biometric sensor panel includes (a) a first flexible substrate, (b) a plurality of first electrodes formed on the first flexible substrate, the first electrodes being arranged in a first direction, (c) a semiconductor layer formed on the first electrodes, (d) a second flexible substrate, (e) a plurality of second electrodes formed on the second flexible substrate, the second electrodes being arranged in a second direction crossing the first direction, and (f) a pressure sensitive conductive layer formed on the second electrodes, wherein the first and second flexible substrates face each other such that the semiconductor layer is in contact with the pressure sensitive conductive layer.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: July 22, 2014
    Assignee: IVI Holdings, Ltd.
    Inventor: Tamio Saito
  • Publication number: 20140197448
    Abstract: An integrated circuit is produced on a bulk semiconductor substrate in a given CMOS technology and includes a semiconductor device for protection against electrostatic discharges. The semiconductor device has a doublet of floating-gate thyristors coupled in parallel and head-to-tail. Each thyristor has a pair of electrode regions. The two thyristors respectively have two separate gates and a common semiconductor gate region. The product of the current gains of the two transistors of each thyristor is greater than 1. Each electrode region of at least one of the thyristors has a dimension, measured perpendicularly to the spacing direction of the two electrodes of the corresponding pair, which is adjusted so as to impart to the thyristor an intrinsic triggering voltage less than the breakdown voltage of a transistor to be protected, and produced in the CMOS technology.
    Type: Application
    Filed: January 15, 2014
    Publication date: July 17, 2014
    Applicant: STMICROELECTRONICS SA
    Inventors: Philippe Galy, Johan Bourgeat
  • Publication number: 20140138735
    Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: DAVID J. CLARKE, JAVIER ALEJANDRO SALCEDO, BRIAN B. MOANE, JUAN LUO, SEAMUS MURNANE, KIERAN K. HEFFERNAN, JOHN TWOMEY, STEPHEN DENIS HEFFERNAN, GAVIN PATRICK COSGRAVE
  • Patent number: 8704271
    Abstract: A bidirectional electrostatic discharge (ESD) protection device includes a substrate having a topside semiconductor surface that includes a first silicon controlled rectifier (SCR) and a second SCR formed therein including a patterned p-buried layer (PBL) including a plurality of PBL regions. The first SCR includes a first and second n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a first merged drain. The second SCR includes a third and a fourth n-channel remote drain MOS device each having a gate, a source within a p-body, and sharing a second merged drain. The plurality of PBL regions are directly under at least a portion of the sources while being excluded from being directly under either of the merged drains.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: April 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Akram A. Salman
  • Publication number: 20140104733
    Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Micron Technology, Inc.
    Inventors: XIAOFENG FAN, MICHAEL D. CHAINE
  • Patent number: 8686470
    Abstract: An integrated circuit device provides electrostatic discharge (ESD) protection. In connection with various example embodiments, an ESD protection circuit includes a diode-type circuit having a p-n junction that exhibits a low breakdown voltage. Connected in series with the diode between an internal node susceptible to an ESD pulse and ground, are regions of opposite polarity having junctions therebetween for mitigating the passage of leakage current via voltage sharing with the diode's junction. Upon reaching the breakdown voltage, the diode shunts current to ground via another substrate region, bypassing one or more junctions of the regions of opposite polarity and facilitating a low clamping voltage.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: April 1, 2014
    Assignee: NXP, B.V.
    Inventor: Hans-Martin Ritter
  • Publication number: 20140054642
    Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann EDWARDS, Akram A. SALMAN
  • Patent number: 8643055
    Abstract: Semiconductor protection devices, and related methods and systems, especially devices for providing series current limiting. The device typically comprises two regenerative building blocks and/or MOSFETs connected back-to-back in series, where one of the MOSFETs/Regenerative Building Blocks has an extra voltage probe electrode that provides a regenerative signal with self-limited voltage to the other via coupling to its gate electrode.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: February 4, 2014
    Assignee: STMicroelectronics N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov, Richard A. Blanchard
  • Patent number: 8642403
    Abstract: In one aspect, a method of forming contacts to source and drain regions in a FET device includes the following steps. A patternable dielectric is deposited onto the device so as to surround each of the source and drain regions. The patternable dielectric is exposed to cross-link portions of the patternable dielectric that surround the source and drain regions. Uncross-linked portions of the patternable dielectric are selectively removed relative to the cross-linked portions of the patternable dielectric, wherein the cross-linked portions of the patternable dielectric form dummy contacts that surround the source and drain regions. A planarizing dielectric is deposited onto the device around the dummy contacts. The dummy contacts are selectively removed to form vias in the planarizing dielectric which are then filled with a metal(s) so as to form replacement contacts that surround the source and drain regions.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Michael A. Guillorn
  • Patent number: 8598620
    Abstract: A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 ?m technology. Self-aligned processing can be used.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: December 3, 2013
    Assignee: STMicroelectronics N.V.
    Inventors: Alexei Ankoudinov, Vladimir Rodov, Richard Cordell
  • Patent number: 8563986
    Abstract: Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: October 22, 2013
    Assignee: Cree, Inc.
    Inventor: Qingchun Zhang
  • Publication number: 20130264607
    Abstract: A semiconductor includes a drift zone of a first conductivity type arranged between a first side and a second side of a semiconductor body. The semiconductor device further includes a first region of the first conductivity type and a second region of a second conductivity type subsequently arranged along a first direction parallel to the second side. The semiconductor device further includes an electrode at the second side adjoining the first and second regions. The semiconductor device further includes a third region of the second conductivity type arranged between the drift zone and the first region. The third region is spaced apart from the second region and from the second side.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 10, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Dorothea Werber, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze, Franz Hirler, Alexander Philippou
  • Publication number: 20130207157
    Abstract: An exemplary reverse-conducting power semiconductor device with a wafer having a first main side and a second main side parallel to the first main side. The device includes a plurality of diode cells and a plurality of IGCT cells, each IGCT cell including between the first and second main side: a first anode electrode, a first anode layer of a first conductivity type on the first anode electrode, a buffer layer of a second conductivity type on the first anode layer, a drift layer of the second conductivity type on the buffer layer, a base layer of the first conductivity type on the drift layer, a first cathode layer of a second conductivity type on the base layer, and a cathode electrode on the first cathode layer. A mixed part includes the second anode layers of the diode cells alternating with the first cathode layers of the IGCT cells.
    Type: Application
    Filed: March 28, 2013
    Publication date: August 15, 2013
    Applicant: ABB Technology AG
    Inventor: ABB Technology AG
  • Patent number: 8441031
    Abstract: Electrostatic discharge (ESD) protection is provided for discharging current between input and output nodes. In accordance with various embodiments, an ESD protection device includes an open-base transistor having an emitter connected to the input node and a collector connected to pass current to the output node via a resistor in response to a voltage at the input node exceeding a threshold that causes the transistor to break down. The resistor is coupled across emitter and collector regions of a second open-base transistor that is configured to turn on for passing current in response to the current across the resistor exceeding a threshold that applies a threshold breakdown voltage across the second transistor. In some implementations, an emitter and/or base of the second transistor are connected to, or are respectively the same region as, a base and a collector of the first transistor.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: May 14, 2013
    Assignee: NXP B.V.
    Inventors: Steffen Holland, Zhihao Pan
  • Publication number: 20130113017
    Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.
    Type: Application
    Filed: September 27, 2012
    Publication date: May 9, 2013
    Applicant: STMicroelectronics S.A.
    Inventor: STMicroelectronics S.A.
  • Patent number: 8431986
    Abstract: A semiconductor device includes a silicon pillar formed substantially perpendicular to a principal surface of a silicon substrate, a first impurity diffusion layer and a second impurity diffusion layer arranged below and above the silicon pillar, respectively, a gate electrode arranged to penetrate through the silicon pillar in a horizontal direction, a gate dielectric film arranged between the gate electrode and the silicon pillar, a back-gate electrode arranged adjacent to the silicon pillar, and a back-gate dielectric film arranged between the back-gate electrode and the silicon pillar.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: April 30, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Hiroshi Kujirai