Abstract: A vertical voltage-controlled bidirectional monolithic switch formed between the upper and lower surfaces of a semiconductor substrate surrounded with a peripheral wall, including: a first multiple-cell vertical IGBT transistor extending between a cathode formed on the upper surface side and an anode formed on the lower surface side; and a second multiple-cell vertical IGBT transistor extending between a cathode formed on the lower surface side and an anode formed on the upper surface side, in which the cells of each transistor are arranged so that portions of the cells of a transistor are active upon operation of the other transistor.

Abstract: A bidirectional semiconductor device facilitates making a current flow from the first MOSFET to the second MOSFET and vice versa across low on-resistance and exhibits a high breakdown voltage. The bidirectional semiconductor device includes a first n-channel MOSFET including base regions, a second n-channel MOSFET including base regions, and an alternating conductivity type layer formed of drift region and partition regions arranged alternately. Partition regions are isolated from base regions by a high resistivity region and from base regions by a high resistivity region to maintaining a high breakdown voltage between first MOSFET and the second MOSFET. By connecting high resistivity regions and via drift regions to each other, a current is made flow from the first MOSFET to the second MOSFET and vice versa and the on-voltage is reduced.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: An electrostatic discharge protection circuit, comprising a semiconductor-controlled rectifier and a PMOS device. The semiconductor-controlled rectifier, coupled between two nodes, has an N-type semiconductor layer. The PMOS device, integrated with the semiconductor-controlled rectifier to share a first P-type doped region, has a PNP device located in the N-type semiconductor layer. When one of the nodes is coupled to the electrostatic discharge power, the PNP device will conduct to trigger the semiconductor-controlled rectifier.

Abstract: A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual vertical devices. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure.

Abstract: A circuit arrangement, in particular for triggering an ignition output stage, having a power switching transistor and a switchable freewheeling circuit or an auxiliary channel. The freewheeling circuit or the auxiliary channel may be constituted by a triggerable four-layer element.

Abstract: The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, among others.

Abstract: In order that the threshold value of a cell separated from an emitter wire bonding portion (W1, W2) be larger than that of a cell immediately below the emitter wire bonding portion, the area of a diffusion layer (8a) of a cell separated from the wire bonding portion is made larger than that of a diffusion layer (8) for connecting an emitter electrode (2) and a base region (7) in a cell immediately below the wire bonding portion. This allows a hole current to be discharged outside via an emitter wire within a short time period, without adversely affecting the operating characteristics and the steady loss, in a position where this hole current readily remains upon turn-off in a conventional IGBT. This shortens the fall time and reduces the switching loss.

Abstract: The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

Abstract: In a semiconductor device of self-extinguish type, in which a channel constituting a current path is controlled by a control voltage applied to a gate electrode, the channel is constructed between an n type cathode region 12 formed in one major surface of n silicon substrate 11 and p type anode region 15 formed in the other major surface of the silicon substrate is opened and closed by the control voltage applied to a gate region 14 as well as a guard region. The guard region is formed by p+ type guard regions 18 and 19 provided adjacent to the channels, and a p type auxiliary guard region 20 formed between the p+ type guard regions 18 and 19 and having a lower impurity concentration than that of the guard regions 18 and 19. During the conduction state, electrons are hardly diffuse laterally underneath the guard region, and therefore upon the turn-off operation, electrons can be taken out at a high speed.

Abstract: With a self-protect thyristor, having a MOSFET (M1) that is connected in series with the thyristor and a second, self-controlled MOSFET (M2) between the p-base of the thyristor and the external cathode (KA), several unit cells for the thyristor are arranged parallel connected in a semiconductor wafer. The voltage at the series MOSFET (M1) functions as an indicator for the overcurrent and excess temperature, and an additional MOSFET (M4) is provided where source (region) is connected conducting to the source of the series MOSFET (M1), where drain is conductivity connected with the gate of the series MOSFET (M1) and where gate conductivity connected with the drain of the series MOSFET (M1). A resistance (Rg) is provided between the gate electrode (G1) of the series MOSFET (M1) and the gate (G) of the thyristor.

Abstract: A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modem RF technologies such as silicon-germanium BiCMOS processes.

Abstract: The IGBT (insulated gate bipolar transistor) has a weakly doped drift zone of a first conductivity formed in a weakly doped semiconductor substrate of the same conductivity. A highly doped first well zone of the first conductivity and a highly doped second well zone of a second conductivity are arranged between the drift zone and the semiconductor substrate.

Abstract: The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.

Abstract: A chip carrier film comprising a metal wiring formed on a surface of a base film, a first insulating film covering the metal wiring excluding a semiconductor chip connecting pad portion and a terminal connecting pad portion, a semiconductor chip connected to the semiconductor chip connecting pad portion of the metal wiring and mounted on the base film, and a second insulating film formed on a back face of the base film and having a different coefficient of curing shrinkage from that of the first insulating film. It is possible to obtain a chip carrier film capable of preventing the suspension of the base film from being generated by the self weight of the semiconductor chip when holding the base film by the delivery device and of carrying out mounting without a hindrance.

Abstract: An insulated gate semiconductor device in which the ON voltage is decreased by providing strip like trenches (207) having gate electrodes (210) buried therein are formed in an upper main surface of a semiconductor base body (200), and an N+ emitter layer (206) is exposed in a ladder-like form in the upper main surface of the semiconductor base body interposed between adjacent trenches (207). Accordingly, even if the position of a zonal region (Ra) which is a contact surface with an emitter electrode (212) is shifted, the emitter electrode (212) is surely in contact with the N+ emitter layer (206). Furthermore, the ladder-like N+ emitter layer (206) is formed adjacent to the trench (7), so that a channel region (208) is formed without discontinuation along the trench (207). Accordingly, it has the effect of facilitating miniaturization of elements and of effectively making use of the miniaturization to decrease the ON voltage.

Abstract: A p-n junction is connected between two terminals. The p-n junction is formed between two semiconductor regions of a semiconductor with a breakdown field strength of at least 10.sup.6 V/cm. A channel region, which adjoins the p-n junction is connected in series with a silicon component between the two terminals. The channel region is provided in a first of the two semiconductor regions. A depletion zone of the p-n junction carries the reverse voltage in the off state of the silicon component.

Abstract: An electrostatic discharge protective circuit of the invention includes a silicon controller rectifier (SCR) and a current diverter. The current diverter is used to bypass an initial low current thereby to prevent the SCR from being triggered by the low current. Thus, a trigger current required to activate the SCR can be greatly increased thereby to maintain an internal circuit at a normal operating state.

Abstract: Silicon carbide power devices include a semiconductor substrate of first conductivity type (e.g., N-type) having a face thereon and a blocking voltage supporting region of first conductivity type therein extending to the face. The voltage supporting region is designed to have a much lower majority carrier conductivity than an underlying and highly conductive "bypass" portion of the semiconductor substrate. This bypass portion of the substrate supports large lateral currents with low on-state voltage drop. First and second semiconductor devices are also provided having respective first and second active regions of first conductivity type therein. These first and second active regions extend on opposing sides of the voltage supporting region and are electrically coupled to the bypass portion of the semiconductor substrate which underlies and extends opposite the voltage supporting region relative to the face of the substrate.

Abstract: A monolithic component including, in an N-type lightly-doped substrate of a semiconductor wafer, two portions separated by a P-type insulating wall. A first portion of the two portions includes a high voltage lateral component, a layer of which substantially corresponds to the thickness of the wafer. The second portion includes logic circuit components. A rear surface of the substrate includes a P-type layer coated with a metallization. The insulating wall is in electrical contact with a low voltage terminal of the high voltage lateral component, such as the gate region of a thyristor. The logic portion includes at least one vertical component.

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is symmetrical, having an N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type drift region, having a portion more heavily doped with P-type dopants. The double RESURF structure can be provided by a buried oxide layer, a floating doped region, or a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

Abstract: A field relaxation region of the second conductivity type is formed between the base region and a drain electrode contact portion at which the drain region contacts with a drain electrode but distanced from both the base region and the drain electrode contact portion and the field relaxation region is also separated via the drain region from the laterally extending portion of the semiconductor isolation region to form a drain current channel region between the field relaxation region and the laterally extending portion of the semiconductor isolation region and further the field relaxation region is electrically connected via an interconnection to the source region and the vertically extending portion of the semiconductor isolation region so that the field relaxation region and the semiconductor isolation region have the same potential as the source region whereby if the lateral MOS field effect transistor is reverse-biased by a voltage, then a first space charge region is formed which extend from a first p-n

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a RESURF operation to provide high voltage blocking in both directions. The IGBT is symmetrical, having N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type-drift region, having a portion more heavily doped with P-type dopants. The RESURF operation can be provided by a buried oxide layer or by a P substrate or by a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: In accordance with the invention, integrated circuit dies may be packaged in a plastic package employing an area area array technology such as a conductive ball grid array, column grid array or pin grid array. One aspect of the invention is an integrated circuit package(10) which includes an electronic circuit enclosed by a plastic body (12, 14). The molded plastic body has a first major surface opposing a second major surface. The first major surface of integrated circuit (10) has a plurality of openings therein. One of a plurality of conductive pads (18) is adjacent to each one of the openings and is electrically connected to the electronic circuit. Each of a plurality of conductors (20) is electrically connected to one of the pads (18) and protrudes from one of the openings (22).

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: A low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of an IC from electrostatic discharge damage using at least one NMOS transistor and at least two SCR connected in parallel between the bonding pad and a circuit ground point. When the electrostatic discharge stress is applied to the bonding pad, the NMOS will breakdown before breakdown of the gate oxide layer of the internal circuit to trigger the SCRs into snapback mode operation. Then the electrostatic discharge stress on the bonding pad is released by two SCRs (or more). Because the electrostatic discharge stress can be released by two SCRs at the same time, the invention can protect the SCRs from damage as well rather than the prior art using just one SCR and lead to better ESD performance. Furthermore, the chip area of the invention is about 150 .mu.m.sup.

Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.

Abstract: A voltage-controlled power monolithic bidirectional switch has two main terminals and includes a control electrode whose voltage is referenced to one of the main terminals. The switch includes a lateral P-channel MOS transistor; a vertical N-channel MOS transistor, the source well of the vertical N-channel MOS transistor also constituting the source of the lateral transistor; a lateral thyristor whose first three regions correspond to the source, drain and channel of the lateral MOS transistor; a first vertical thyristor disposed in parallel with the lateral thyristor; and a second vertical thyristor having a polarity opposite to the first polarity and disposed in parallel with the vertical MOS transistor.

Abstract: High withstand voltage, low on-voltage, low turn-off loss, and high switching speed are realized in semiconductor bidirectional switches in which the potential of the substrate is floating. A switch has a p-type substrate without an electrode, and an n-layer on the substrate. At least one pair of p-well regions and at least one p-region are formed in a surface layer of the n-layer. An n.sup.+ region is formed in the p-well region, and a gate electrode is fixed via an insulation film to the p-well region. A main electrode is fixed to a part of the surface of the n.sup.+ region and the surface of a p.sup.+ contact region in the p-well region.

Abstract: A new static memory cell based on the bistable operation of a three-terminal four layer semiconductor device working in the forward blocking state is disclosed. The power consumption of the memory cell is low. The switching speed of the memory cell is in the nanosecond range. The memory cell may be integrated into VLSI processes and is of a size suitable for VLSI applications. The memory cell comprises a semiconductor device which comprises: an n-type semiconductor cathode region; a p-type semiconductor gate region; a third semiconductor region adjacent the gate region; a fourth region adjacent the third semiconductor region; and a hole-injecting boundary between the third semiconductor region and the fourth region. The semiconductor device is preferably a p-n-p-n device. The gate current-voltage characteristics of the device comprise a negative resistance region. The device is designed to operate in a forward blocking low current state.

Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.

Abstract: An insulated-gate bipolar transistor (IGBT) is connected in reverse-parallel with a current-regenerative diode which, for economy of manufacture, is integrated with the IGBT. Such a diode may extend laterally on an IGBT chip, with two conductivity regions forming the diode respectively connected to emitter and collector electrodes of the IGBT. Alternatively, the diode may be formed by short-circuiting a buffer layer and a collector layer. By such integration, greater device packing density can be realized.

Abstract: The performance of COMFET-based electrical switches may be improved by connecting a MOSFET substantially in parallel with the COMFET. In a monolithic embodiment, a MOSFET drain region may be added to a surface of a COMFET and shorted to the emitter region of the COMFET. The invention decreases the turn-off time of the COMFET, reduces the discontinuity at current direction reversal and increases the latch-up current of a semiconductor switch.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: An optically triggered silicon controlled rectifier (SCR) circuit (20) has a number of semiconductor layers diffused into an N- substrate (21). The layers form an SCR (50) having a P+ anode region (25), a P+ gate region (24), and an N+ cathode region (27). An adjustable base-shunt resistance, in the form of a P- channel depletion mode MOSFET (Q3), connects between the SCR gate region and the cathode region. The MOSFET includes a MOSFET gate region (35), a P+ drain region (24), a P-- channel (26), and a P+ source region (23). The substrate also accommodates a PN photodiode (22, D1) which connects to the MOSFET gate region for switching the MOSFET on and off in response to incident optical radiation (L) thereon. The SCR gate region also comprises photosensitive material. When sufficient optical radiation illuminates the photodiode and the SCR gate region, the MOSFET is turned off and the SCR is triggered, permitting anode-to-cathode current to flow.

Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: A GTO thyristor includes a p-type emitter layer, an n-type base layer, a p-type base layer and an n-type emitter layer. An additional n-type layer is formed on the p-type base layer next to the n-type emitter layer An additional p.sup.+ -type layer is formed on the additional n-type layer and stretches to the n-type emitter layer. An anode electrode and a cathode electrode are disposed respectively on the n-type emitter layer and the p-type base layer. The n-type emitter layer and the additional p.sup.+ -type layer are connected with each other by a floating electrode. A first gate electrode is disposed on the additional p.sup.+ -type layer, additional n-type layer and p-type base layer with an insulating film interposed therebetween so as to form a first FET. A second gate electrode is disposed on the n-type base layer, p-type base layer and n-type emitter layer with an insulating film interposed therebetween so as to form a second FET.

Abstract: A switching device includes a thyristor and a MOSFET, and a voltage clamp circuit. The voltage clamp circuit includes an N.sup.+ type contact region formed in a surface layer of a N type substrate and electrically connected to a gate electrode of a MOSFET, and a P type guard ring surrounding the contact region.

Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.