J-fet (junction Field Effect Transistor) Patents (Class 257/134)
  • Patent number: 10672746
    Abstract: An integrated circuit includes a first chip including a high-voltage depletion-mode transistor and a second chip including an enhancement-mode device. The chips have first and second gate contact pads, first and second source contact pads and first and second drain contact pads, respectively, on their front sides. Chips are joined together via their front sides, and the area of the first chip is larger than that of the second chip. The first chip includes an additional contact pad on its front side that is electrically insulated from the high-voltage depletion-mode transistor and that contacts the second gate contact pad. The first gate contact pad contacts the second source contact pad and/or the first source contact pad contacts the second drain contact pad. The first gate contact pad and the additional contact pad extend at least partially into a peripheral portion of the first chip.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 2, 2020
    Assignee: Exagan
    Inventors: Domenico Lo Verde, Laurent Guillot, Fabrice Letertre
  • Patent number: 10622381
    Abstract: As a display device has higher definition, the number of pixels is increased and thus, the number of gate lines and signal lines is increased. When the number of gate lines and signal lines is increased, it is difficult to mount IC chips including driver circuits for driving the gate lines and the signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided on the same substrate, and at least part of the driver circuit comprises a thin film transistor including an oxide semiconductor sandwiched between gate electrodes. A channel protective layer is provided between the oxide semiconductor and a gate electrode provided over the oxide semiconductor. The pixel portion and the driver circuit are provided on the same substrate, which leads to reduction of manufacturing cost.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Shunpei Yamazaki
  • Patent number: 10411124
    Abstract: A semiconductor structure includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a transition body over the III-Nitride intermediate stack, a III-Nitride buffer layer situated over the transition body, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 10, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Chan Kyung Choi, Mihir Tungare, Peter Wook Kim
  • Patent number: 10121886
    Abstract: This application provides a high power semiconductor device, which is characterized by forming two diodes connected in parallel and a schottky contact on a channel layer to lower the turn-on voltage and turn-on resistance of the high power semiconductor device at the same time and to enhance the breakdown voltage.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 6, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Ming-Chin Chen, Yi-Chih Lin, Shang-Ju Tu
  • Patent number: 9929090
    Abstract: Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile memories. The memory circuitry employs an antifuse scheme that includes an array of 1 T bitcells, wherein each bitcell effectively contains one gate or transistor-like device that provides both an antifuse element and a selector device for that bitcell. In particular, the bitcell device has asymmetric trench-based source/drain contacts such that one contact forms a capacitor in conjunction with the spacer and gate metal, and the other contact forms a diode in conjunction with a doped diffusion area and the gate metal. The capacitor serves as the antifuse element of the bitcell, and can be programmed by breaking down the spacer. The diode effectively provides a Schottky junction that serves as a selector device which can eliminate program and read disturbs from bitcells sharing the same bitline/wordline.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ting Chang, Chia-Hong Jan, Walid M. Hafez
  • Patent number: 9735769
    Abstract: Systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using multiple different semi-conductive channel regions generating structures formed by multiple different semi-conductive electrical current or voltage control structures. One embodiment includes providing a first and second metal oxide semiconductor field effect transistor (MOSFET) sections formed on opposite sides of a metal-semiconductor field effect transistor (MESFET) such that operation of the MESFET modulates or controls current otherwise controlled by an electrical path of the MOSFET sections. A control system for determining when an embodiment of the invention is to be operated is also provided to include automated systems including sensors as well as manually operated systems. Automated systems can include radiation sensors as well as other control systems such as high voltage radio frequency transmitter or receiver systems. Methods of operation for a variety of modes are also provided.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: August 15, 2017
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Jeffrey L. Titus
  • Patent number: 9716170
    Abstract: Embodiments of the invention are directed to a vertical FET device having gate and source or drain features. The device includes a fin formed in a substrate and a source or a drain region formed in the substrate. The device further includes a trench formed in the source or the drain region and a dielectric region formed in the trench. The device further includes a gate formed along vertical sidewalls of the fin and positioned such that a space between the gate and the source or the drain region includes at least a portion of the dielectric region. In some embodiments, the device further includes a bottom spacer formed over an upper surface of the dielectric region and positioned such that the space between the gate and the source or the drain region further includes at least a portion of the bottom spacer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 25, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 9698594
    Abstract: Components can be damaged if they are exposed to excess voltages. A device is disclosed herein which can be placed in series with a component and a node that may be exposed to high voltages. If the voltage becomes too high, the device can autonomously switch into a relatively high impedance state, thereby protecting the other components.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: July 4, 2017
    Assignee: ANALOG DEVICES GLOBAL
    Inventor: Edward John Coyne
  • Patent number: 9608092
    Abstract: A method for forming a field-effect semiconductor device includes: providing a wafer having a main surface and a first semiconductor layer of a first conductivity type; forming at least two trenches from the main surface partly into the first semiconductor layer so that each of the at least two trenches includes, in a vertical cross-section substantially orthogonal to the main surface, a side wall and a bottom wall, and that a semiconductor mesa is formed between the side walls of the at least two trenches; forming at least two second semiconductor regions of a second conductivity type in the first semiconductor layer so that the bottom wall of each of the at least two trenches adjoins one of the at least two second semiconductor regions; and forming a rectifying junction at the side wall of at least one of the at least two trenches.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: March 28, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jens Konrath, Hans-Joachim Schulze, Roland Rupp, Wolfgang Werner, Frank Pfirsch
  • Patent number: 9461115
    Abstract: A switching power supply has a start-up circuit that includes a field effect transistor (JFET), which has a gate region (a p-type well region) formed in a surface layer of a p-type substrate and a drift region (a first n-type well region). A plurality of source regions (second n-type well regions) are formed circumferentially around the drift region. A drain region (a third n-type well region) is formed centrally of the source region. The drain region and the source regions can be formed at the same time. A metal wiring of the source electrode wiring connected to source regions is divided into at least two groups to form at least two junction field effect transistors.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: October 4, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaru Saito, Koji Sonobe
  • Patent number: 9455701
    Abstract: Apparatuses and methods for modulating current/voltage response using multiple semi-conductive channel regions (SCR) produced from different integrated semiconductor structures are provided. In particular, embodiments include systems and methods for controlling current or mitigating electromagnetic or radiation interference effects using combined integrated functions of a lateral double-diffused metal-oxide semiconductor field effect transistor (LDMOSFET) and metal-semiconductor field effect transistor (MESFET) disposed in proximity of a LDMOSFET's SCR within a certain orientation forming a second SCR.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 27, 2016
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Jeffrey L. Titus
  • Patent number: 9406762
    Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: August 2, 2016
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Patent number: 9331068
    Abstract: A hybrid semiconductor bipolar switch in which a normally-on high-voltage wide-bandgap semiconductor bipolar switch and a normally-off field effect transistor are connected in a cascode (Baliga-pair) configuration. The switch may be constructed as a stacked hybrid device where a discrete transistor is bonded on top of a bipolar switch. Power systems may use plural switches paired with anti-parallel diodes.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 3, 2016
    Assignee: United Silicon Carbide, Inc.
    Inventors: Leonid Fursin, Anup Bhalla
  • Patent number: 9293548
    Abstract: According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: March 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuneo Ogura
  • Patent number: 9291874
    Abstract: An optical deflection element is provided with a substrate; an optical waveguide film made of an electro-optic medium, and constituting an optical waveguide formed on the substrate; a first electrode pair disposed on an incident side of the optical waveguide film at a position facing a film thickness direction of the optical waveguide film, and configured to deflect a light beam transmitting through the optical waveguide film in an in-plane direction of the optical waveguide film in accordance with a first applied voltage; and a second electrode pair disposed on an output side of the optical waveguide film at a position facing the film thickness direction of the optical waveguide film, and configured to deflect the light beam deflected in the in-plane direction of the optical waveguide film by the first electrode pair in the film thickness direction of the optical waveguide film in accordance with a second applied voltage. The second electrode pair includes a first electrode and a second electrode.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: March 22, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Norihito Fujinoki
  • Patent number: 9136397
    Abstract: A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: September 15, 2015
    Assignee: Infineon Technologies AG
    Inventors: Jens Konrath, Hans-Joachim Schulze, Roland Rupp, Wolfgang Werner, Frank Pfirsch
  • Patent number: 9041120
    Abstract: A transistor device comprises: at least one individual transistor cell arranged in a transistor cell field on a semiconductor body, each individual transistor cell comprising a gate electrode; a gate contact, electrically coupled to the gate electrodes of the transistor cells and configured to switch on the at least one transistor cell by providing a gate current in a first direction and configured to switch off the at least one transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction; at least one gate-resistor structure monolithically integrated in the transistor device, the gate-resistor structure providing a first resistance for the gate current when the gate current flows in the first direction, and providing a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: May 26, 2015
    Assignee: Infineon Technologies AG
    Inventors: Stephan Voss, Peter Tuerkes, Holger Huesken
  • Patent number: 9041049
    Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
  • Patent number: 8901603
    Abstract: A protection circuit for metal-oxide-semiconductor field-effect transistors (MOSFETs) that are used as active bypass diodes in photovoltaic solar power systems is disclosed. The protection circuit comprises, a detection circuit for detecting the start of a surge event, a switch disposed to connect the MOSFET's drain to it's gate in response to the start of the surge, a diode in series with the switch, a bistable circuit for keeping the switch closed during the surge, and a means of resetting the bistable circuit after the surge.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: December 2, 2014
    Inventor: Steven Andrew Robbins
  • Patent number: 8890109
    Abstract: Provided are resistive random access memory (ReRAM) cells including resistive switching layers and thermally isolating structures for limiting heat dissipation from the switching layers during operation. Thermally isolating structures may be positioned within a stack or adjacent to the stack. For example, a stack may include one or two thermally isolating structures. A thermally isolating structure may directly interface with a switching layer or may be separated by, for example, an electrode. Thermally isolating structures may be formed from materials having a thermal conductivity of less than 1 W/m*K, such as porous silica and mesoporous titanium oxide. A thermally isolating structure positioned in series with a switching layer generally has a resistance less than the low resistance state of the switching layer. A thermally isolating structure positioned adjacent to a switching layer may have a resistance greater than the high resistance state of the switching layer.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 18, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140291721
    Abstract: A protection circuit for metal-oxide-semiconductor field-effect transistors (MOSFETs) that are used as active bypass diodes in photovoltaic solar power systems is disclosed. The protection circuit comprises, a detection circuit for detecting the start of a surge event, a switch disposed to connect the MOSFET's drain to it's gate in response to the start of the surge, a diode in series with the switch, a bistable circuit for keeping the switch closed during the surge, and a means of resetting the bistable circuit after the surge.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: SUNFIELD SEMICONDUCTOR INC.
    Inventor: Steven Andrew Robbins
  • Patent number: 8841698
    Abstract: A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500° C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: September 23, 2014
    Assignee: The United States of America as Represented by the Administrator of National Aeronautics and Space Administration
    Inventor: Philip G. Neudeck
  • Patent number: 8829573
    Abstract: A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 9, 2014
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 8829482
    Abstract: A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 9, 2014
    Assignee: Adesto Technologies Corporation
    Inventors: Antonio R. Gallo, Chakravarthy Gopalan, Yi Ma
  • Patent number: 8796738
    Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 5, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8791510
    Abstract: A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Kyu Lee
  • Patent number: 8778758
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of electrode structures above a substrate. The method includes forming an insulating film on the plurality of electrode structures to make a gap between mutually-adjacent electrode structures. The method includes forming a silicon nitride film having compressive stress above the insulating film. The method includes forming a planarization film above the silicon nitride film. The method includes planarizing a surface of the planarization film by polishing by CMP (chemical mechanical polishing) method.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Kubota
  • Patent number: 8723235
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Grant
    Filed: February 20, 2012
    Date of Patent: May 13, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8710543
    Abstract: A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: April 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Yuhji Ichikawa
  • Patent number: 8581298
    Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8575648
    Abstract: A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 5, 2013
    Assignee: DENSO CORPORATION
    Inventors: Yuuichi Takeuchi, Rajesh Kumar Malhan, Naohiro Sugiyama
  • Patent number: 8569795
    Abstract: A semiconductor device of an embodiment includes: a silicon carbide substrate including first and second principal surfaces; a first conductive-type first silicon carbide layer provided on the first principal surface of the silicon carbide substrate; a second conductive-type first silicon carbide region formed on a surface of the first silicon carbide layer; a first conductive-type second silicon carbide region formed on a surface of the first silicon carbide region; a second conductive-type third silicon carbide region formed on the surface of the first silicon carbide region; a gate insulating film continuously formed on the surfaces of the first silicon carbide layer, the first silicon carbide region, and the second silicon carbide region; a first electrode formed of silicon carbide formed on the gate insulating film; a second electrode formed on the first electrode; an interlayer insulating film for covering the first and second electrodes; a third electrode electrically connected to the second silicon ca
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Yukio Nakabayashi, Takashi Shinohe, Makoto Mizukami
  • Patent number: 8564017
    Abstract: A drift layer has a thickness direction throughout which a current flows and has an impurity concentration N1d for a first conductivity type. A body region is provided on a portion of the drift layer, has a channel to be switched by a gate electrode, has an impurity concentration N1b for the first conductivity type, and has an impurity concentration N2b for the second conductivity type greater than the impurity concentration N1b. A JFET region is disposed adjacent to the body region on the drift layer, has an impurity concentration N1j for the first conductivity type, and has an impurity concentration N2j for the second conductivity type smaller than the impurity concentration N1j. N1j?N2j>N1d and N2j<N2b are satisfied.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: October 22, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Misako Honaga, Takeyoshi Masuda, Keiji Wada, Toru Hiyoshi
  • Patent number: 8513675
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 20, 2013
    Assignee: Power Integrations, Inc.
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8460976
    Abstract: The present invention relates to a manufacturing method of SOI devices, and in particular, to a manufacturing method of SOI high-voltage power devices.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: June 11, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8436397
    Abstract: In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Haruka Shimizu, Natsuki Yokoyama
  • Patent number: 8421119
    Abstract: A GaN related compound semiconductor element includes: a channel layer made of a GaN related compound semiconductor; and a source layer and a drain layer, which are disposed in a manner of sandwiching the channel layer. The source layer includes two adjacent ridge portions which are formed by selective growth. A source electrode is formed over the surface, sandwiched by the ridge portions, of the channel layer, and the surfaces of the respective two adjacent ridge portions. The selective-growth mask formed between the two ridge portions is removed by wet etching. In addition, as another embodiment, a gate electrode is formed in a manner that the direction of the longer dimension of the gate electrode is aligned with the m plane of the channel layer. Moreover, as still another embodiment, the channel layer has a multilayer structure in which a GaN layer doped with no impurity is used as an intermediate layer.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: April 16, 2013
    Assignee: Rohm Co., Ltd.
    Inventor: Yukio Shakuda
  • Patent number: 8415720
    Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 9, 2013
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Badih El-Kareh, Kyu Ok Lee, Joo Hyung Kim, Jung Joo Kim
  • Patent number: 8399888
    Abstract: A p-type SiC semiconductor includes a SiC crystal that contains Al and Ti as impurities, wherein the atom number concentration of Ti is equal to or less than the atom number concentration of Al. It is preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 0.01%?(Concentration of Ti)/(Concentration of Al)?20%. It is more preferable that the concentration of Al and the concentration of Ti satisfy the following relations: (Concentration of Al)?5×1018/cm3; and 1×1017/cm3?(Concentration of Ti)?1×1018/cm3.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: March 19, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hiroaki Saitoh, Akinori Seki, Tsunenobu Kimoto
  • Patent number: 8377755
    Abstract: A method of manufacturing a SOI high voltage power chip with trenches is disclosed. The method comprises: forming a cave and trenches at a SOI substrate; filling oxide in the cave; oxidizing the trenches, forming oxide isolation regions for separating low voltage devices at the same time; filling oxide in the oxidized trenches; and then forming drain regions, source regions and gate regions for a high voltage power device and low voltage devices. The process involves depositing an oxide layer overlapping the cave of the SOI substrate. A SOI high voltage power chip thus made will withstand at least above 700V voltage.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: February 19, 2013
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
    Inventors: Xinhong Cheng, Zhongjian Wang, Yuehui Yu, Dawei He, Dawei Xu, Chao Xia
  • Patent number: 8334579
    Abstract: An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The integrated circuit device includes a substrate, a diffusion source, and a lightly doped diffusion region in contact with a conductive layer. A junction of the lightly doped diffusion region with the conductive layer forms a Schottky region. An annealing process is performed to form the lightly doped diffusion region. The annealing process causes dopants from the diffusion source (for example, an n-well disposed in the substrate) of the integrated circuit device to diffuse into a region of the substrate, thereby forming the lightly doped diffusion region.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: December 18, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping Chun Yeh, Der-Chyang Yeh, Chih-Ping Chao
  • Publication number: 20120199875
    Abstract: A switching device includes a low voltage normally-off transistor and a control circuit built into a common die. The device includes source, gate and drain electrodes for the transistor and one or more auxiliary electrodes. The drain electrode is on one surface of a die on which the transistor is formed, while each of the remaining electrodes is located on an opposite surface. The one or more auxiliary electrodes provide electrical contact to the control circuit, which is electrically connected to one or more of the other electrodes.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 9, 2012
    Inventors: Anup Bhalla, Sik Lui, Jun Hu, Fei Wang
  • Patent number: 8227831
    Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hidekatsu Onose
  • Patent number: 8222649
    Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: July 17, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naruhisa Miura, Keiko Fujihira, Kenichi Otsuka, Masayuki Imaizumi
  • Patent number: 8202772
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: June 19, 2012
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8188540
    Abstract: A double-gate semiconductor device includes a MOS gate and a junction gate, in which the bias of the junction gate is a function of the gate voltage of the MOS gate. The breakdown voltage of the double-gate semiconductor device is the sum of the breakdown voltages of the MOS gate and the junction gate. The double-gate semiconductor device provides improved RF capability in addition to operability at higher power levels as compared to conventional transistor devices. The double-gate semiconductor device may also be fabricated in a higher spatial density configuration such that a common implantation between the MOS gate and the junction gate is eliminated.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: May 29, 2012
    Assignee: ACCO Semiconductor, Inc.
    Inventors: Denis A. Masliah, Alexandre G. Bracale, Francis C. Huin, Patrice J. Barroul
  • Patent number: 8159001
    Abstract: A graded junction space decreasing an implant concentration gradient between n-well and p-well regions of a semiconductor device is provided for enhancing breakdown voltage in high voltage applications. Split or unified FOX regions may be provided overlapping with the graded junction space. By using a p-well blocking layer to separate the p-well(s) and the n-well, breakdown voltage characteristic is improved without the cost of an additional mask or process change.
    Type: Grant
    Filed: July 19, 2006
    Date of Patent: April 17, 2012
    Assignee: Synopsys, Inc.
    Inventor: Bin Wang
  • Patent number: 8120072
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Grant
    Filed: July 24, 2008
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20120007138
    Abstract: The present invention provides a smoke-free ESD protection structure used in integrated circuit devices. A JFET or n-channel MOS transistor is coupled between an I/O pad, and a transistor and diode, wherein the JFET or n-channel MOS transistor limits the current flowing through the diode and transistor to prevent the integrated circuit device from heating up and catching on fire or smoke during the smoke test. Moreover, the integrated circuit device will not be damaged by the smoke test.
    Type: Application
    Filed: July 12, 2010
    Publication date: January 12, 2012
    Inventor: James Nguyen
  • Publication number: 20110316494
    Abstract: According to an embodiment of the invention, there is provided a switching power supply device including an integrated body and a plurality of external terminals. In the integrated body, a first switching element, a constant current element, and a diode are connected in series. The plurality of external terminals include a first external terminal connected to a main terminal of an element disposed on one end side of the integrated body and a second external terminal connected to a main terminal of an element disposed on another end side of the integrated body.
    Type: Application
    Filed: June 27, 2011
    Publication date: December 29, 2011
    Applicant: TOSHIBA LIGHTING & TECHNOLOGY CORPORATION
    Inventors: Noriyuki Kitamura, Yuji Takahashi, Koji Suzuki, Koji Takahashi, Toru Ishikita