Abstract: According to an embodiment of the invention, there is provided a switching power supply device including an integrated body and a plurality of external terminals. In the integrated body, a first switching element, a constant current element, and a diode are connected in series. The plurality of external terminals include a first external terminal connected to a main terminal of an element disposed on one end side of the integrated body and a second external terminal connected to a main terminal of an element disposed on another end side of the integrated body.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: To improve the surge resistance of J-FET, a P-type epitaxial layer 2 and an N-type epitaxial layer 3 are formed on a P++-conductive substrate 1; N+-conductive source diffusion layer 4 and drain diffusion layer 5, and a p+-conductive gate diffusion layer 6 are formed in the N-type epitaxial layer 3; and a short-circuit preventing layer 8 of a reversed conduction-type diffusion layer is formed adjacent to the side walls of the source diffusion layer 4 and the drain diffusion layer 5. Having the constitution, the punch-through to be caused by surge voltage is prevented in the surface region of the device, and the surge resistance thereof is improved. Via the holes formed in a protective insulation film 9 on the surface of the device, a source electrode 10 connected to the source diffusion layer 4, and a drain electrode 11 connected to the drain diffusion layer 5 are formed on the surface side of the device.

Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.

Abstract: Semiconductor switching devices include a wide band-gap drift layer having a first conductivity type (e.g., n-type), and first and second wide band-gap well regions having a second conductivity type (e.g., p-type) on the wide band-gap drift layer. First and second wide band-gap source/drain regions of the first conductivity type are on the first and second wide band-gap well regions, respectively. A wide band-gap JFET region having the first conductivity type is provided between the first and second well regions. This JFET region includes a first local JFET region that is adjacent a side surface of the first well region and a second local JFET region that is adjacent a side surface of the second well region. The local JFET regions have doping concentrations that exceed a doping concentration of a central portion of the JFET region that is between the first and second local JFET regions of the JFET region.

Abstract: The present invention provides a MOSFET and so forth that offer high breakdown voltage and low on-state loss (high channel mobility and low gate threshold voltage) and that can easily achieve normally OFF. A drift layer 2 of a MOSFET made of silicon carbide according to the present invention has a first region 2a and a second region 2b. The first region 2a is a region from the surface to a first given depth. The second region 2b is formed in a region deeper than the first given depth. The impurity concentration of the first region 2a is lower than the impurity concentration of the second region 2b.

Abstract: A semiconductor device includes at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type, a first well region of a second conductivity type, a second well region of a first conductivity type, a drift region of a second conductivity type, a collector region of a first conductivity type, and a collector contact. Each cell is disposed within the first well region, and the first well region is disposed within the second well region. The device further includes a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region, and at least one embedded region embedded in the first well region. The device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first well region and the second well region.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a Drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof.

Abstract: In a high voltage junction field effect transistor, a first well (11) of a first conductivity type is formed in a substrate (10) of a second conductivity type. A source (14) and a drain (15) which are each of the first conductivity type are formed in the first well. A gate (16) of the second conductivity type is arranged in a second well (12) of the second conductivity type, wherein the second well is of the retrograde type. The source, gate and drain are spaced apart from one another by field oxide regions (13a to 13d). Field plates (17a, 17b) extend over the field oxide (13a, 13b) from the gate (16) in the direction of source and drain.

Abstract: A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: Insulated gate bipolar conduction transistors (IBCTs) are provided. The IBCT includes a drift layer having a first conductivity type. An emitter well region is provided in the drift layer and has a second conductivity type opposite the first conductivity type. A well region is provided in the drift layer and has the second conductivity type. The well region is spaced apart from the emitter well region. A space between the emitter well region and the well region defines a JFET region of the IBCT. An emitter region is provided in the well region and has the first conductivity type and a buried channel layer is provided on the emitter well region, the well region and the JFET region and has the first conductivity type. Related methods of fabrication are also provided.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

Abstract: An energy transmission device includes: a semiconductor device formed on a first semiconductor substrate; a semiconductor integrated circuit including a reverse current preventing diode and a control circuit; a DC voltage source; and a transformer. The reverse current preventing diode includes a reverse current preventing layer of a second conductivity type formed at a surface of a second semiconductor substrate, and a well layer of a first conductivity type formed in the second semiconductor substrate and covering the reverse current preventing layer. The transformer includes a primary winding connected in series with the semiconductor device and the DC voltage source, and a first secondary winding connected to a load. The energy transmission device is configured so that electric power is supplied from the first secondary winding of the transformer to the load. A second drain electrode of the semiconductor device is electrically connected to the reverse current preventing layer.

Abstract: We disclose the structure of a JFET device, the method of making the device and the operation of the device. The device is built near the top of a substrate. It has a buried layer that is electrically communicable to a drain terminal. It has a channel region over the buried layer contacting gate regions that connect to a gate terminal. The channel region, of which the length spans the distance between the buried layer and a source region, is connected to a source terminal. The device current flows in the channel substantially perpendicularly to the top surface of the substrate.

Abstract: A semiconductor device is disclosed. One embodiment provides a top surface. A first lateral semiconductor region is arranged adjacent to the top surface and includes a transistor structure. The transistor structure includes a drain zone of a first conductivity type. A second lateral semiconductor region is arranged below the first semiconductor region and includes a junction field-effect transistor structure. The junction field-effect transistor structure includes a source zone of the first conductivity type which is electrically connected to the drain zone of the transistor structure.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: In one embodiment, a semiconductor device comprises a semiconductor material having a first conductivity type with a body region of a second conductivity type disposed in the semiconductor material. The body region is adjacent a JFET region. A source region of the first conductivity type is disposed in the body region. A gate layer is disposed over the semiconductor material and has a first opening over the JFET region and a second opening over the body region.

Abstract: A single-chip common-drain JFET device comprises a drain, two gates and two source arranged such that two common-drain JFETs are formed therewith. Due to the two JFETs merged within a single chip, no wire bonding connection is needed therebetween, thereby without parasitic inductance and resistance caused by bonding wire, and therefore improving the performance and reducing the package cost. The single-chip common-drain JFET device may be applied in buck converter, boost converter, inverting converter, switch, and two-step DC-to-DC converter to improve their performance and efficiency. Alternative single-chip common-drain JFET devices are also provided for current sense or proportional current generation.

Abstract: An epitaxially layered structure with gate voltage bias supply circuit element for improvement in performance for semiconductor field effect transistor (FET) devices utilizes a structure comprised of a substrate, a first layer semiconductor film of either an n-type or a p-type grown epitaxially on the substrate, with the possibility of a buffer layer between the substrate and first layer film, an active semiconductor layer grown epitaxially on the first semiconductor layer with the conductivity type of the active layer being opposite that of the first semiconductor layer, with the active layer having a gate region and a drain region and a source region with electrical contacts to gate, drain and source regions sufficient to form a FET, an electrical contact on either the substrate or the first semiconductor layer, and a gate voltage bias supply circuit element electrically connected to gate contact and to substrate or first semiconductor layer with voltage polarity and magnitude sufficient to increase device

Abstract: This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.

Abstract: The present, invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

Abstract: In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult. In the invention, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance.

Abstract: Example embodiments are directed to a junction field effect thin film transistor (JFETFT) including a first electrode formed on a substrate, a first conductive first gate semiconductor pattern formed on the first gate electrode, a second conductive semiconductor channel layer formed on the substrate and the first conductive first gate semiconductor pattern, and source and drain electrodes formed on the second conductive semiconductor pattern and located at both sides of the first conductive gate semiconductor pattern. The JFETFT may further include a first conductive second gate semiconductor pattern formed on a portion of the second conductive semiconductor channel layer between the source electrode and the drain electrode, and a second gate electrode formed on the first conductive second gate semiconductor pattern.

Abstract: A semiconductor device includes a first field effect transistor including a source and a gate and disposed in a silicon carbide substrate; and a second field effect transistor including a drain and a gate and disposed in the substrate. The drain of the second field effect transistor connects to the source of the first field effect transistor. The gate of the second field effect transistor connects to the gate of the first field effect transistor.

Abstract: A semiconductor vertical junction field effect power transistor formed by a semiconductor structure having top and bottom surfaces and including a plurality of semiconductor layers with predetermined doping concentrations and thicknesses and comprising at least a bottom layer as drain layer, a middle layer as blocking and channel layer, a top layer as source layer. A plurality of laterally spaced U-shaped trenches with highly vertical side walls defines a plurality of laterally spaced mesas. The mesas are surrounded on the four sides by U-shaped semiconductor regions having conductivity type opposite to that of the mesas forming U-shaped pn junctions and defining a plurality of laterally spaced long and vertical channels with a highly uniform channel opening dimension. A source contact is formed on the top source layer and a drain contact is formed on the bottom drain layer.

Abstract: A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.

Abstract: A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a second direction surrounding a portion of the channel to allow for application and removal of a gate voltage. Application of the gate voltage repels majority carriers in the channel to reduce the current that conducts between the source and drain.

Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.

Abstract: A junction field effect transistor (JFET) is fashioned where a channel of transistor is buried deeply within the workpiece within which the JFET is formed. Burying the channel below the surface of the workpiece and/or away from overlying conductive materials distances a current that flows in the channel from outside influences, such as the effects of the overlying conductive materials. The deep channel also provides a more regular path for the current flowing therein by moving the channel away from non-uniformities on or near the surface of the workpiece, where said non-uniformities or irregularities would interrupt or otherwise disturb current flowing in a channel that is not as deep. These aspects of the deep channel serve to reduce noise and allow the transistor to operate in a more repeatable and predictable manner, among other things.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

Abstract: To provide a semiconductor device that permits free setting of characteristics of individual semiconductor elements which are mixedly mounted and have different characteristics, and is free of steps between formed semiconductor elements, in a manufacturing method for the semiconductor device, an n-type silicon layer is deposited on a p-type silicon substrate by epitaxial growth, and then an SOI layer is deposited thereon through the intermediary of a BOX layer. A junction transistor using a part of the n-type silicon layer as a channel region and a MOS transistor using the SOI layer are produced.

Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.

Abstract: A semiconductor device including a metal oxide layer, a channel area of the metal oxide layer, a preservation layer formed on the channel area of the metal oxide layer, and at least two channel contacts coupled to the channel area of the metal oxide layer, and a method of forming the same.

Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).

Abstract: The present invention discloses a laser dicing apparatus for a gallium arsenide wafer and a method thereof, wherein firstly, a gallium arsenide wafer is stuck onto a holding film; next, the gallium arsenide wafer together with the holding film is disposed on a working table; the gallium arsenide wafer has multiple chips or dice with a scribed line drawn between every two chips; a control device and an object lens are used to position the working table and a laser, and two video devices are used to observe whether the laser has been precisely aimed at one of the scribed lines; after parameters have been input into the control device, the laser is used to cut the gallium arsenide wafer, and the gallium arsenide wafer is then separated into multiple discrete chips or dice. The present invention can precisely cut gallium arsenide wafers, reduce the cost and accelerate the fabrication process.

Abstract: The present invention provides a system for providing a cross-lateral junction field effect transistor (114) having desired high-performance desired voltage, frequency or current characteristics. The cross-lateral transistor is formed on a commercial semiconductor substrate (102). A channel structure (124) is formed along the substrate, having source (120) and drain (122) structures laterally formed on opposites sides thereof. A first gate structure (116) is formed along the substrate, laterally adjoining the channel structure orthogonal to the source and drain structures. A second gate structure (118) is formed along the substrate, laterally adjoining the channel structure, orthogonal to the source and drain structures and opposite the first gate structure.

Abstract: A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to controlling the final junction geometry and thereby reducing the junction capacitance by establishing the lateral extent of the implanted gate region, the gate definition spacer also limits the available diffusion paths for the implanted dopant species during anneal. Also, the gate definition spacer defines the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: The present invention provides a JFET which receives an additional implant during fabrication, which extends its drain region towards its source region, and/or its source region towards its drain region. The implant reduces the magnitude of the e-field that would otherwise arise at the drain/channel (and/or source/channel) junction for a given drain and/or source voltage, thereby reducing the severity of the gate current and breakdown problems associated with the e-field. The JFET's gate layer is preferably sized to have a width which provides respective gaps between the gate layer's lateral boundaries and the drain and/or source regions for each implant, with each implant implanted in a respective gap.

Abstract: A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.