Abstract: An SCR with a first semiconductor region and plural concentric semiconductor regions, each surrounding the first semiconductor region. The SCR also includes, surrounded by at least one concentric semiconductor region in the plurality of concentric semiconductor regions, an electrically non-contacted region of a semiconductor type and positioned to modulate a snapback voltage of the silicon controlled rectifier and an electrically-contacted region of the semiconductor type and positioned to provide a diodic response between the at least one concentric semiconductor region in the plurality of concentric semiconductor regions and the electrically-contacted region.

Abstract: A vertical power semiconductor device is proposed. The vertical power semiconductor device includes a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction. The vertical power semiconductor device further includes a drift region in the semiconductor body. The drift region includes platinum atoms. The vertical power semiconductor device further includes a field stop region in the semiconductor body between the drift region and the second main surface. The field stop region includes a plurality of impurity peaks. A first impurity peak of the plurality of impurity peaks has a larger concentration than a second impurity peak of the plurality of impurity peaks. The first impurity peak includes hydrogen and the second impurity peak includes helium.

Abstract: One or more systems, devices and/or methods of use provided herein relate to a device that can facilitate a signal generation. A current-mode end-to-end signal path can include a digital to analog converter (DAC) operating in current-mode and an upconverting mixer, operating in current-mode and operatively coupled to the DAC. Analog inputs and analog outputs of the DAC and the upconverting mixer can be represented as currents, and the DAC can generate a baseband signal. In one or more embodiments, a current source and a diode-connected transistor can be arranged in parallel in the current-mode signal path between a baseband filter and an output stage comprising the upconverting mixer. The device and/or system can be a radio frequency DAC. The diode-connected transistor can be programmable to vary gain and/or can be directly connected to the output stage absent a turnaround current mirror connected therebetween.

Abstract: A semiconductor device of an embodiment includes first and second electrodes; first and second gate electrodes; and semiconductor layer including first and second planes, the semiconductor layer including a first semiconductor region of first conductivity type including first portion, second portion having a carrier concentration higher than the first portion, and third portion having a carrier concentration lower than the second portion; a second semiconductor region of second conductivity type between the first semiconductor region and the first plane and facing the first gate electrode; a third semiconductor region of first conductivity type between the second semiconductor region and the first plane and contacting the first electrode; a fourth semiconductor region of second conductivity type between the first semiconductor region and the second plane and facing the second gate electrode; and a fifth semiconductor region of first conductivity type between the fourth semiconductor region and the second plan

Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.

Abstract: The reverse recovery withstand capability of a semiconductor device is improved. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the substrate and through which current flows between upper and lower surfaces of the substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion and arrayed next to the transistor portion along a predetermined array direction in a top view of the substrate; and an edge termination structure portion provided between a peripheral end of the substrate and the active portion in the top view. The lifetime control region including a lifetime killer is provided on an upper-surface side of the substrate and in a range from the diode portion to at least part of the edge termination structure portion, facing the diode portion in a direction of extension orthogonal to the array direction.

Abstract: To improve the turn-off withstand capability of a semiconductor device. A semiconductor device is provided, including: a semiconductor substrate; an active portion that is provided in the semiconductor substrate and through which current flows between upper and lower surfaces of the semiconductor substrate; a transistor portion provided in the active portion; a diode portion provided in the active portion, and arrayed next to the transistor portion along a predetermined array direction in a top view of the semiconductor substrate; and an edge termination structure portion provided between a peripheral end of the semiconductor substrate and the active portion in the top view. In the top view, at at least part of the edge termination structure portion, which part facing the transistor portion in the direction of extension orthogonal to the array direction, a first-conductivity type first cathode region is provided in contact with the lower surface.

Abstract: A semiconductor device include a semiconductor body with a drain region of a first conductivity type, a drift region of the first conductivity type and having a doping concentration lower than a doping concentration of the drain region, a buffer region of the first conductivity type arranged between the drift region and the drain region, a source region of the first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region and forming a first pn-junction with the source region and a second pn-junction with the drift region, and a charge compensation region of the second conductivity type extending from the body region towards the buffer region. A source metallization is in ohmic contact with the source region. A drain metallization is ohmic contact with the drain region.

Abstract: A semiconductor device includes: a semiconductor substrate having a cell region, a termination region located around the cell region, and a wiring region; an IGBT provided in the cell region; an insulating film provided on the semiconductor substrate in the wiring region; a gate electrode provided on the insulating film and connected to a gate of the IGBT; a p-type well layer provided on a surface side of the semiconductor substrate in the termination region; and a diode provided in the wiring region, wherein the diode includes a the p-type base layer provided on the surface side of the semiconductor substrate and an n-type cathode layer provided on a reverse side of the semiconductor substrate, the p-type base layer is provided in common to the wiring region and the cell region and has a lower impurity concentration and a smaller depth than the p-type well layer.

Abstract: A semiconductor device may include a semiconductor substrate. A semiconductor substrate may include a diode region and an IGBT region provided adjacent to the diode region. The IGBT region may include a plurality of first conductive-type low concentration regions provided between a buffer region and a collector region, arranged with intervals therebetween in a direction parallel to the semiconductor substrate, and having a lower impurity concentration than the collector region. The collector region may include a first contact portion that is in contact with the buffer region between the low concentration regions adjacent to each other.

Abstract: In a semiconductor device including a low lifetime region of a depth within a range on both sides sandwiching a p-n junction of a p-type semiconductor region bottom portion, the low lifetime region includes a central region that has a portion coinciding with the semiconductor region as seen from one main surface side and is selectively formed as far as the position of a contact end portion of a region of the coinciding portion with which the semiconductor region and a metal electrode are in contact, a peripheral region wherein the central region extends as far as the position of an outer peripheral end of the semiconductor region, and an expanded end portion region wherein the peripheral region extends as far as an outer peripheral end of the innermost of guard rings. Because of this, it is possible to reduce leakage current while maintaining high reverse recovery current resistance.

Abstract: A non-volatile memory device comprises a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.

Abstract: According to one embodiment, a semiconductor device includes a first region having an insulated gate bipolar transistor and a second region having a diode. The first region and the second region are formed in a same chip. A breakdown voltage of the second region is lower than a breakdown voltage of the first region.

Abstract: A semiconductor package in an embodiment includes a semiconductor device which has a first semiconductor element, a second semiconductor element, and a common first electrode between the first and second semiconductor elements. A second electrode is electrically connected to the first semiconductor element. A third electrode extends through the second semiconductor element and electrically connects to the first electrode. A fourth electrode is electrically connected to the second semiconductor element. A first terminal of the package is electrically connected to the third electrode. A second terminal of the package is electrically connected to the second electrode and the fourth electrode. An insulating material surrounds the semiconductor device.

Abstract: A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.

Abstract: In a semiconductor device including an IGBT and a diode, an upper-side lifetime control region, which is provided in the drift region within a range located above an intermediate depth of the drift region, is provided in a diode area and is not provided in an IGBT area. A first inter-trench semiconductor region, which is adjacent to a second inter-trench semiconductor region in a diode area, includes a barrier region of an n-type located between the body region and the drift region and a pillar region of the n-type extending from a position being in contact with the upper electrode to a position being in contact with the barrier region. Each of the second inter-trench semiconductor regions in the diode area does not include the pillar region.

Abstract: A semiconductor device includes a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, a first electrode, a third semiconductor region of the second conductive type, a fourth semiconductor region of the first conductive type, and a conductive portion. The second semiconductor region is provided on the first semiconductor region. The first electrode is provided on the second semiconductor region. The third semiconductor region is provided on the first electrode. The fourth semiconductor region is provided on the third semiconductor region. The conductive portion is surrounded by the third semiconductor region and an intervening insulation portion and is electrically connected to the first electrode.

Abstract: A semiconductor device includes an insulated gate bipolar transistor (IGBT) arrangement. The IGBT arrangement includes a first configuration region of emitter-side insulated gate bipolar transistor structures and a second configuration region of emitter-side insulated gate bipolar transistor structures. The first configuration region and the second configuration region are arranged at a main surface of a semiconductor substrate of the semiconductor device. Further, the IGBT arrangement includes a collector layer and a drift layer. The collector layer is arranged at a backside surface of the semiconductor substrate and the drift layer is arranged between the collector layer and the emitter-side IGBT structures of the first configuration region and the second configuration region. Additionally, the collector layer includes at least a first doping region laterally adjacent to a second doping region.

Abstract: The semiconductor device includes a first semiconductor layer of the first conductive type, a second semiconductor layer having the cubic crystalline structure formed on the first semiconductor layer, an electrode formed on the second semiconductor layer, and a reactive region formed between the second semiconductor layer and the electrode. The second semiconductor layer includes an upper surface that is tilted from the (100) plane. The reactive region includes at least one element constituting the second semiconductor layer, at least one element constituting the electrode, and forming a protuberance extending toward the second semiconductor layer.

Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization and a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A first gate electrode of the first field-effect structure is electrically coupled to a first gate driver circuit and a second gate electrode of the second field-effect structure is electrically coupled to a second gate driver circuit different from the first gate driver circuit. The first field-effect structure and the second field-effect structure share a common drain.

Abstract: The present invention achieves a formation of a metal oxide film of a thin film transistor with a simplified process. The present invention is concerned with a method for manufacturing a field-effect transistor comprising a gate electrode, a source electrode, a drain electrode, a channel layer and a gate insulating layer wherein the channel layer is formed by using a metal salt-containing composition comprising a metal salt, a polyvalent carboxylic acid having a cis-form structure of —C(COOH)?C(COOH)—, an organic solvent and a water wherein a molar ratio of the polyvalent carboxylic acid to the metal salt is in the range of 0.5 to 4.0.

Abstract: An electrostatic discharge (ESD) protection circuit structure includes several diffusion regions and a MOS transistor. The circuit structure includes a first diffusion region of a first type (e.g., P-type or N-type) formed in a first well of the first type, a second diffusion region of the first type formed in the first well of the first type, and a first diffusion region of a second type (e.g., N-type or P-type) formed in a first well of the second type. The first well of the second type is formed in the first well of the first type. The MOS transistor is of the second type and includes a drain formed by a second diffusion region of the second type formed in a second well of the second type bordering the first well of the first type.

Abstract: A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region.

Abstract: A semiconductor device includes a semiconductor substrate having a diode active region and an edge termination region adjacent to each other, a first region of a first conductivity type in the diode active region, a second region of a second conductivity type, a third region of the first conductivity type in the edge termination region, and a fourth region of the second conductivity type. The first region and the third region share a drift region of the first conductivity type. The first region and the third region share a fifth region of the first conductivity type. The drift region in the third region is greater in number of crystal defects per unit volume than the drift region in the first region in order that the drift region in the third region is shorter in carrier lifetime than the drift region in the first region.

Abstract: A method of making a memristor having an embedded switching layer include exposing a surface portion of a first electrode material within a via to a reactive species to form the switching layer embedded within and at surface of the via. The via is in contact with a first conductor trace. The method further includes depositing a layer of a second electrode material adjacent to the via surface and patterning the layer into a column aligned with the via. The method further includes depositing an interlayer dielectric material to surround the column and providing a second conductor trace in electrical contact with the second electrode material of the column.

Abstract: Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw1|>|Vw2|. Vw1 represents writing voltage for first to N-th steps. Vw2 represents writing voltage for (N+1)-th and subsequent steps, where N?1, |Ve1|>|Ve2|. Ve1 represents erasing voltage for first to M-th steps. Ve2 represents erasing voltage for M+1-th and subsequent steps. tw1<te1. tw1 represents writing pulse width for first to N-th steps. te1 represents erasing pulse width for first to M-th steps. M?1. The (N+1)-th writing step follows the M-th erasing step.

Abstract: An ESD protection circuit includes a MOS transistor of a first type, a MOS transistor of a second type, an I/O pad, and first, second, and third guard rings of the first, second, and first types, respectively. The MOS transistor of the first type has a source coupled to a first node having a first voltage, and a drain coupled to a second node. The MOS transistor of the second type has a drain coupled to the second node, and a source coupled to a third node having a second voltage lower than the first voltage. The I/O pad is coupled to the second node. The first, second, and third guard rings are positioned around the MOS transistor of the second type.

Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode.

Abstract: A semiconductor device includes a source metallization and a semiconductor body. The semiconductor body includes a first field-effect structure including a source region of a first conductivity type electrically coupled to the source metallization. The semiconductor body also includes a second field-effect structure including a source region of the first conductivity type electrically coupled to the source metallization. A voltage tap including a semiconductor region within the semiconductor body is electrically coupled to a first gate electrode of the first field-effect structure by an intermediate inverter structure.

Abstract: A reverse-conducting semiconductor device includes a freewheeling diode and an insulated gate bipolar transistor (IGBT) on a common wafer. Part of the wafer forms a base layer with a base layer thickness. The IGBT includes a collector side and an emitter side arranged on opposite sides of the wafer. A first layer of a first conductivity type and a second layer of a second conductivity type are alternately arranged on the collector side. The first layer includes at least one first region with a first region width and at least one first pilot region with a first pilot region width. The second layer includes at least one second region with a second region width and at least one second pilot region with a second pilot region width. Each second region width is equal to or larger than the base layer thickness, whereas each first region width is smaller than the base layer thickness. Each second pilot region width is larger than each first pilot region width.

Abstract: Programming a variable resistance element includes: a writing step of applying a writing voltage pulse to transition metal oxide comprising two stacked metal oxide layers to decrease resistance of the metal oxide, each metal oxide layer having different oxygen deficiency; and an erasing step of applying an erasing voltage pulse, of different polarity than the writing pulse, to the metal oxide to increase resistance of the metal oxide. |Vw1|>|Vw2|, Vw1 representing voltage of the writing pulse for first to N-th writing steps, and Vw2 representing voltage of the writing pulse for (N+1)-th and subsequent writing steps, N being at least equal to 1, te1>te2, te1 representing pulse width of the erasing pulse for first to M-th erasing steps, and te2 representing pulse width of the erasing pulse for (M+1)-th and subsequent erasing steps. M>1. The (N+1)-th writing step follows the M-th erasing step.

Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

Abstract: A semiconductor device has a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type complementary to the first conductivity type arranged in or on the first semiconductor layer. Further, the semiconductor device has a region of the first conductivity type arranged in the second semiconductor layer. A first electrode contacts the region of the first conductivity type and the second semiconductor layer. A first trench extends into the first semiconductor layer, and a voltage dependent short circuit diverter structure includes electrically conductive material arranged in the first trench and coupled to the first electrode and a highly-doped diverter region of the second conductivity type.

Abstract: A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the IGBT cell region; a third semiconductor region on the second side in the diode cell region; a fourth semiconductor region on the first side surrounding the active element cell area; a fifth semiconductor region on the first side surrounding the fourth semiconductor region; and a sixth semiconductor region on the second side below the fourth semiconductor region. The second semiconductor region, the third semiconductor region and the sixth semiconductor region are electrically coupled with each other.

Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a source region and a drain region. The source region is to be coupled to a low-level voltage. The drain region is disposed apart from the source region and includes a first P-type heavily doped region and at least one first N-type heavily doped region. The first P-type heavily doped region is configured to couple to a pad, and the first N-type heavily doped region is adjacent to the first P-type heavily doped region and floated. An electrostatic discharge protection apparatus is also disclosed herein.

Abstract: The present disclosure relates to methods of treating a silicon substrate with an ultra-fast laser to create a getter material for example in a substantially enclosed MEMS package. In an embodiment, the laser treating comprises irradiating the silicon surface with a plurality of laser pulses adding gettering microstructure to the treated surface. Semiconductor based packaged devices, e.g. MEMS, are given as examples hereof.

Abstract: An electrostatic discharge (ESD) protection element using an NPN bipolar transistor, includes: a trigger element connected at one end with a pad. The NPN bipolar transistor includes: a first base diffusion layer; a collector diffusion layer connected with the pad; a trigger tap formed on the first base diffusion layer and connected with the other end of the trigger element through a first wiring; and an emitter diffusion layer and a second base diffusion layer formed on the first base diffusion layer and connected in common to a power supply through a second wiring which is different from the first wiring.

Abstract: A low voltage transient voltage suppressing (TVS) device supported on a semiconductor substrate supporting an epitaxial layer thereon. The TVS device further includes a bottom-source metal oxide semiconductor field effect transistor (BS-MOSFET) comprises a trench gate surrounded by a drain region encompassed in a body region disposed near a top surface of the semiconductor substrate wherein the drain region interfaces with the body region constituting a junction diode and the drain region encompassed in the body region on top of the epitaxial layer constituting a bipolar transistor with a top electrode disposed on the top surface of the semiconductor functioning as a drain/collector terminal and a bottom electrode disposed on a bottom surface of the semiconductor substrate functioning as a source/emitter electrode.

Abstract: An integrated circuit package that comprises a lead frame, an integrated circuit located on the lead frame and a shunt resistor coupled to the lead frame and to the integrated circuit. The shunt resistor has a lower temperature coefficient of resistance than the lead frame, and the lead frame has a lower resistivity than the shunt resistor. The shunt resistor has a low-resistance coupling to external leads of the lead frame, or, the shunt resistor has its own integrated external leads.

Abstract: A semiconductor device has a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type complementary to the first conductivity type arranged in or on the first semiconductor layer. Further, the semiconductor device has a region of the first conductivity type arranged in the second semiconductor layer. A first electrode contacts the region of the first conductivity type and the second semiconductor layer. A first trench extends into the first semiconductor layer, and a voltage dependent short circuit diverter structure includes electrically conductive material arranged in the first trench and coupled to the first electrode and a highly-doped diverter region of the second conductivity type.

Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.

Abstract: According to one embodiment, a semiconductor device comprises a body of a first conductivity type having a source region and a channel, the body being in contact with a top contact layer. The device also comprises a gate arranged adjacent the channel and a drift zone of a second conductivity type arranged between the body and a bottom contact layer. An integrated diode is formed partially by a first zone of the first conductivity type within the body and being in contact with the top contact layer and a second zone of the second conductivity type being in contact with the bottom contact layer. A reduced charge carrier concentration region is formed in the drift zone having a continuously increasing charge carrier lifetime in the vertical direction so that the charge carrier lifetime is lowest near the body and highest near the bottom contact layer.

Abstract: A semiconductor device includes: a substrate; an active element cell area including IGBT cell region and a diode cell region; a first semiconductor region on a first side of the substrate in the active element cell area; a second semiconductor region on a second side of the substrate in the IGBT cell region; a third semiconductor region on the second side in the diode cell region; a fourth semiconductor region on the first side surrounding the active element cell area; a fifth semiconductor region on the first side surrounding the fourth semiconductor region; and a sixth semiconductor region on the second side below the fourth semiconductor region. The second semiconductor region, the third semiconductor region and the sixth semiconductor region are electrically coupled with each other.

Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Abstract: A semiconductor body includes a drift zone of a first conduction type. A body zone of a second conduction type complementary to the first conduction type is located near the surface in the semiconductor body. The semiconductor body includes a near-surface field stop zone of the second complementary conduction type and doped more lightly than the body zone.

Abstract: A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region.