Abstract: A method for transferring a thin semiconductor layer from one substrate to another substrate involves depositing a thin epitaxial monocrystalline semiconductor layer on a substrate having surface contaminants. An interface that includes the contaminants is formed in between the deposited layer and the substrate. Hydrogen atoms are introduced into the structure and allowed to diffuse to the interface. Afterward, the thin semiconductor layer is bonded to a second substrate and the thin layer is separated away at the interface, which results in transferring the thin epitaxial semiconductor layer from one substrate to the other substrate.

Abstract: According to an embodiment of the invention, there is provided a semiconductor device comprising: a semiconductor element having a first main electrode, a second main electrode and a control electrode, a current flowing between the first and second main electrodes being controlled by a control signal which is input between the control electrode and the second main electrode; and a capacitor formed by providing an insulating layer between the second main electrode and the control electrode of the semiconductor element.

Abstract: An IGBT with monolithic integrated antiparallel diode has one or more emitter short regions forming the diode cathode in the region of the high-voltage edge. The p-type emitter regions of the IGBT have no emitter shorts. The counterelectrode of the diode exclusively comprises p-type semiconductor wells on the front side of the device. Particularly in applications, such as lamp ballast, in which the diode of the IGBT is firstly forward-biased, hard commutation is not effected and the current reversal takes place relatively slowly. The emitter short regions may be strips or points below the high-voltage edge. The horizontal bulk resistance is increased and the snapback effect is reduced without reducing the robustness in the edge region. In a second embodiment, the IGBT is produced using thin wafer technology and the thickness of the substrate defining the inner zone is less than 200 ?m. The thickness of the emitter region or of the emitter regions and short region(s) is less than 1 ?m.

Abstract: A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0?x?1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0?y?1 and 0<z?1; and a gate electrode formed on the second compound layer. The gate electrode is electrically connected to a resistance element formed on a first interlayer insulating film that covers the gate electrode, through a metal wiring formed on a second interlayer insulating film that covers the first interlayer insulating film.

Abstract: A method of manufacturing a liquid crystal display device is intended to decrease the number of manufacturing steps. The liquid crystal display device is arranged so that in each pixel area provided on a liquid-crystal-side surface of one of a pair of substrates disposed to oppose each other with a liquid crystal interposed therebetween, a signal from a drain line is applied to a pixel electrode via a drain electrode and a source electrode which are formed in a layer overlying a semiconductor layer of a thin film transistor, by the supply of a scanning signal from a gate electrode which is positioned as an underlying layer with respect to the semiconductor layer.

Abstract: A preferably asymetrical thyristor (1) with at least one driver stage (20) for amplifying a control current (I) fed into the cathodal base (16) of the thyristor, in which, in the driver stage, the transistor gain factors &agr;npn and &agr;pnp are in each case greater than, preferably, in the thyristor and anode short circuits of the thyristor (174) have a smaller electrical conductivity in the driver stage than in the thyristor.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: An improved relaxation oscillator circuit is provided using conventional CMOS device shunted with a current source (101 and 103) at each load of two cross-coupled gain stages. The improved oscillator uses a clamp voltage reference (134), to control the voltage swing across the charging/discharging capacitor (118). The improvements provide improved speed to power ratio, increased frequency tuning range, and less process and temperature variation effects. A transistor (130) and current source (138) replicate output transistors (110, 114) and current sources (101, 103).

Abstract: There is provided a semiconductor integrated circuit device having a macro cell structure including: a rectangular macro cell region formed on a semiconductor substrate; a first diffusion region having the minimum permissible width, formed apart at least by a minimum inter-diffusion distance from both left and right side ends in upper and lower sides of the macro cell region, and formed in the vicinity of both upper and lower ends of the macro cell region; and a second diffusion region in which a well contact is formed. The first diffusion region is electrically connected with the second diffusion region.

Abstract: Both the blocking voltage as well as the sweep voltage of conventional thyristors exhibit a pronounced temperature behavior, whereby the corresponding voltage values can change by up to 15% within the relevant temperature range (5° C.-120° C.). In the proposed thyristor, the overhead triggering is compelled by the “punch through” effect that is independent of the temperature (expanse of the space charge zone allocated to the p-base/n-base junction 10) up to the neighboring n-base/p-emitter junction 11). Due to the laterally non-uniform distribution of the dopant in the n+ stop zone (7′) of the anode-side base (7), further, it is assured that the central thyristor region always ignites first. Sweep or punch through voltage is not dependent on the temperature in the asymmetrical thyristors.

Abstract: In a gate turn-off thyristor (GTO) with homogeneous anode, emitter and stop layer, a device which short-circuit the stop layer with the anode is provided in an edge termination region. As a result, in a reverse-biased state, the GTO has a structure of a diode in the edge region and amplification of a reverse current is obviated. With this structure, thermal loading in the edge region is reduced, as the GTO tolerates a higher operating temperature at a predetermined voltage.

Abstract: A semiconductor rectifier in which the sum of loss during reverse recovery and loss in a conducting state can be suppressed even if the ratio between the periods of the conducting and blocking states varies and a method of driving the same are disclosed. A voltage is applied to a gate electrode formed in a face-to-face relationship with a base layer of a first conductivity type and an emitter layer of a second conductivity type with a gate insulation film interposed therebetween to form an inversion layer on the surface of the base layer of the first conductivity type. As a result, the base layer of the first conductivity type and the short layer of the first conductivity type are short-circuited to decrease the density of carriers in the base layer of the first conductivity type, loss during a reverse recovery operation can be suppressed.

Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.

Abstract: A novel semiconductor switching device is disclosed. The switching device is designed and constructed to include, for example, a highly interdigitated cathode/gate structure on both anode and cathode sides. The semiconductor switching device can be multi-loaded on both anode and cathode sides which provides a great deal of flexibility in operation.

Abstract: A bidirectional lateral insulated gate bipolar transistor (IGBT) includes two gate electrodes. The IGBT can conduct current in two directions. The IGBT relies on a double RESURF structure to provide high voltage blocking in both directions. The IGBT is symmetrical, having an N-type drift region in contact with an oxide layer. A P-type region is provided above the N-type drift region, having a portion more heavily doped with P-type dopants. The double RESURF structure can be provided by a buried oxide layer, a floating doped region, or a horizontal PN junction. The IGBT can be utilized in various power operations, including a matrix switch or a voltage source converter.

Abstract: A lateral semiconductor device, such as an LIGBT, LMOSFET, lateral bipolar transistor, lateral thyristor, or lateral MOS control thyristor, includes a device area surrounded by an n-type region in an n-channel lateral semiconductor device or by a p-type region in a p-channel lateral semiconductor device. Connecting the n-type region in the n-channel lateral semiconductor device or the p-type region in the p-channel lateral semiconductor device at a same potential as a first main electrode suppresses operation of parasitic transistors, as well as prevents carrier accumulation in isolated regions or a substrate. As a result, a switching loss of the lateral semiconductor device is greatly reduced, a switching speed of the lateral semiconductor device is improved, and a current capacity of the lateral semiconductor device is increased.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: An integrated circuit arrangement includes an IGBT, provided with a secondary contact connected with the drift area, and a diode connected between the secondary contact and the anode of the IGBT. The cathode of the diode is connected with the anode of the IGBT and the anode of the diode is connected with the secondary contact of the IGBT. In this way the pn-junction of the IGBT, formed through the drift area and the channel area, can be used as an internal free-running diode of the IGBT.

Abstract: It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N.sup.- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N.sup.- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.

Abstract: A thyristor according to the invention comprises a layer sequence containing an n-type emitter layer (4), a p-type base layer (5), an n-type base layer (6) and a p-type emitter layer (7) in a semiconductor substrate (3) between an anode (1) and a cathode (2). The p-type emitter layer (7) is perforated by anode short-circuit zones (8) and is thereby subdivided into sections. In this arrangement, the anode short circuits (8) short-circuit the n-type base layer (6) to the anode (1). Disposed between the anode short circuits (8) and the p-type emitter layer (7) is a p-type barrier layer (9), also referred to as p-type soft layer. According to the invention, said p-type barrier layer (9) has gaps (12) in which the n-type base (6) is contacted by the anode (1) either directly or via an anode short circuit (8).

Abstract: MOSFET and IGBT components protected against overvoltage by a limiting diode inserted between drain or, respectively, collector terminal and gate terminal are provided. A freewheeling diode connected to the component having a limiting diode with a breakdown voltage that is lower than the breakdown voltage of the freewheeling diode by a defined amount is provided. This over-voltage protection can be achieved in a simple way by integrating the limiting diode into the semiconductor body of the freewheeling diode and by a corresponding arrangement of the anode zone of the limiting diode.

Abstract: On one major surface of an n.sup.- -type semiconductor substrate, a p-type base region is formed in a semiconductor substrate, and an n-type emitter region is formed in the p-type base region. A p-type source region is formed near the p-type base region. A cathode electrode has a so-called shorted emitter structure in which the cathode electrode is connected to the p-type source region, the p-type base region, and the n-type emitter region. The p-type source region preferably has a pattern adjacent the p-type base region. The p-type base region is preferably constituted by a plurality of diffusion layers which are electrically connected to each other. Therefore, turn-off characteristics of a device can be improved, and turn-on characteristics are improved without degrading the turn-off characteristics, thereby improving trade-off between the turn-on characteristics and the turn-off characteristics.

Abstract: A static induction thyristor has a first semiconductor area having a high impurity concentration of a first conductivity type. A second semiconductor area having low impurity concentration is formed adjacent to the first semiconductor area. A third semiconductor area having a high impurity concentration of a second conductivity type which is the conductivity type opposite to the first conductivity type is formed on a part of a surface of the second semiconductor area so located as to form a fourth semiconductor area located within the third semiconductor area. A fifth semiconductor area having a high impurity concentration of the first conductivity type is formed on the part of the surface of the second semiconductor area in spaced relation to the forth semiconductor area.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductive type with a low impurity density; a first region of a second conductive type; a second region of the first conductive type with a high impurity density formed in a surface of the first region; a third region of the second conductive type with a high impurity density; a gate insulating film formed on the surface of the first region intervening between an exposed surface of the semiconductor substrate and the second region; a gate electrode formed on the gate insulating film; a fourth region of the second conductive type opposite to the first region on the other surface of the semiconductor substrate; a fifth region of the first conductive type with a high impurity density which is opposite to the third region and adjacent to the fourth region; a first electrode commonly brought into contact with the first and second regions; a second electrode brought into contact with the second region and connected to the first electrode; and a

Abstract: A compound semiconductor device is provided which includes a thyristor region constructed by four continuous layers of p-n-p-n and an MOSFET region which is formed in the intermediate n layer of the thyristor region so as to be away from the intermediate p layer. The MOSFET is constructed by a p well layer, a source layer, and a drain layer. One main electrode of the device is in ohmic contact with the outside p layer of the thyristor region. While the other main electrode is in ohmic contact with the source layer and well layer of the MOSFET region. An arrangement is provided for electrically connecting the outside n layer of the thyristor region and the drain layer of the MOSFET region. Also, a first insulating gate is formed on the well layer between the source layer and the drain layer of the MOSFET region and a second insulating gate is formed on the intermediate p layer of the thyristor region; with the first and second insulating gates being electrically connected.

Abstract: A lateral insulated-gate bipolar transistor has a drift region having therein a base layer and a collector layer. An emitter layer is formed in the base layer. A gate electrode structure, comprising a control electrode and gate insulating layer, contacts the base layer, and also contacts the drift layer and the emitter layer. An emitter electrode contacts the emitter layer, and also the base layer, and a collector electrode contacts the collector layer. The emitter and collector electrodes are elongate and the ratio of their resistances per unit length is in the range of 0.5 to 2.0. This reduces the possibility of a localized high current density along the electrodes, thereby reducing the risk of latch-up due to parasitic thyristors. The collector and emitter electrodes may be of the same width and thickness, or of different widths and thicknesses, or may each have an auxiliary part (for example, in a multi-layer wiring arrangement), so that their resistances per unit length are in the desired range.

Abstract: An MCT (MOS controlled thyristor) including a first outer layer of a first conductivity type whose surface contacts a first major electrode, and a second outer layer at which an MOS structure is disposed, and whose surface contacts a second major electrode. The MCT is provided with a second conductivity type region formed in the first outer layer in such a manner that it contacts the first major electrode, but does not contact an inner layer adjacent to the first layer. The MCT has a low on-resistance, a small turn-off loss, and can prevent a negative resistance phenomenon from occurring.

Abstract: A p-type emitter layer 2 is formed in one surface portion of an n.sup.- -type base layer 1 of high resistance. p.sup.+ -type contact layers 2b and n.sup.+ -type current blocking layers 6 are formed in a preset area ratio in the surface area of the p-type emitter layer. A cathode electrode 4 is formed in contact with the contact layer 2b as well as the current blocking layer 6 of the pn junction diode section. With this cathode structure, the electron injection in the ON state can be suppressed so as to reduce the carrier concentration of a portion of the n.sup.- -type base layer 1 lying on the cathode side, and the parasitic transistor effect caused at the time of reverse recovery can be suppressed by provision of the current blocking layer 6.