Combined With Other Solid-state Active Device In Integrated Structure Patents (Class 257/146)
  • Patent number: 11217510
    Abstract: A semiconductor device forming a bidirectional switch includes a carrier, first and second semiconductor elements arranged on the carrier, a first row of terminals arranged along a first side face of the carrier, a second row of terminals arranged along a second side face of the carrier opposite the first side face, and an encapsulation body encapsulating the first and second semiconductor elements. Each row of terminals includes a gate terminal, a sensing terminal and at least one power terminal of the bidirectional switch.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Michael Treu
  • Patent number: 11145641
    Abstract: An electrostatic discharge protection device including the following components is provided. A first PNP BJT includes a P-type region, first and second N-type well regions, first P-type, first N-type, and second P-type doped regions, and an N-type region. An NPN BJT includes first P-type and third N-type well regions, a second N-type doped region, a third P-type doped region, and a third N-type doped region. A second PNP BJT includes the first P-type and third N-type well regions, the third P-type doped region, the third N-type doped region, and a fourth P-type doped region. The second P-type doped region, the first N-type doped region, the third N-type doped region, and the fourth P-type doped region are coupled to a high voltage side terminal. The first P-type doped region, the second N-type doped region, and the third P-type doped region are coupled to a low voltage side terminal.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 12, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Wing-Chor Chan, Che-Hong Chen
  • Patent number: 10964699
    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: March 30, 2021
    Assignee: TCLab, Inc.
    Inventor: Harry Luan
  • Patent number: 10861833
    Abstract: A semiconductor device includes a first and a second metal layer, the second provided on a same plane as the first layer, and first second and third terminals. A first metal wiring layer is electrically connected to the first terminal. A second metal wiring layer is electrically connected to the second terminal and the second metal layer and disposed over the first metal wiring layer. A third metal wiring layer is electrically connected to the third terminal and the first metal layer. A first semiconductor chip is provided between the first metal wiring layer and the first metal layer. A second semiconductor chip is provided between the third metal wiring layer and the second metal layer. The first chip has electrodes connected to the first metal wiring layer and the first metal layer. The second chip has electrodes connected to the third metal wiring layer and the second metal layer.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 8, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuo Tonedachi
  • Patent number: 10700069
    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: June 30, 2020
    Assignee: TC Lab, Inc.
    Inventor: Harry Luan
  • Patent number: 10573568
    Abstract: A method of producing a semiconductor component is provided. The method includes providing a silicon substrate having a <111>-surface defining a vertical direction, forming in the silicon substrate at least one electronic component, forming at least two epitaxial semiconductor layers on the silicon substrate to form a heterojunction above the <111>-surface, and forming a HEMT-structure above the <111>-surface.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Gebhart Dippold
  • Patent number: 10573650
    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 25, 2020
    Assignee: TC Lab, Inc.
    Inventor: Harry Luan
  • Patent number: 10461659
    Abstract: A semiconductor device includes a module substrate, a first input wiring line disposed on a top surface of the module substrate and including a first portion extending along a first side of the module substrate and a second portion extending along a second side that is adjacent to the first side, the second portion having one end that is connected to one end of the first portion, a first input terminal disposed on another end of the second portion and electrically connected to the first input wiring line, first to fourth transistors, first and second output terminals, a second input wiring line disposed on the top surface of the module substrate so as to be close to a fourth side that is opposite to the first side and adjacent to the second side, a second input terminal, and a module sealing member sealing the top surface.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: October 29, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Teiichi Okubo
  • Patent number: 10249609
    Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a first bipolar junction transistor (BJT) and a second BJT cross-coupled with the first BJT to operate as a first semiconductor-controlled rectifier (SCR), where a base of the first BJT is connected to a collector of the second BJT, and a base of the second BJT is connected to an emitter or a collector of the first BJT. The integrated circuit device additionally includes a triggering device comprising a first diode having a cathode electrically connected to the base of the first BJT. The integrated circuit device further includes a third BJT cross-coupled with the second BJT to operate as a second SCR, where the third BJT has a collector connected to the base of the second BJT and a base connected to the collector of the second BJT.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: April 2, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Javier Alejandro Salcedo, Linfeng He
  • Patent number: 10170607
    Abstract: A semiconductor device has a semiconductor substrate including a first conductivity-type drift layer, a second conductivity-type base layer disposed in a surface layer portion of the drift layer, and a second conductivity-type collector layer and a first conductivity-type cathode layer disposed opposite to the base layer with respect to the drift layer. In the semiconductor substrate, an IGBT region and a diode region are alternately and repetitively arranged. The IGBT region and the diode region are divided by a boundary between the collector layer and the cathode layer. The collector layer is defined as a first collector layer. The semiconductor device includes a second collector layer having a second conductivity-type impurity concentration higher than that of the first collector layer, at a surface of the semiconductor substrate adjacent to the first collector layer and the cathode layer.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 1, 2019
    Assignee: DENSO CORPORATION
    Inventor: Kenji Kouno
  • Patent number: 10164447
    Abstract: To provide a semiconductor product high in versatility. A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: December 25, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Mochizuki, Kensuke Nakashima, Takahiro Korenari, Kouji Nakajima
  • Patent number: 9705399
    Abstract: A buck converter device with a zero-cross comparator with an adaptive threshold. The buck converter comprises of a control block that controls a first p-channel MOSFET switch, and a second n-channel MOSFET switch. The p-channel MOSFET switch and the n-channel MOSFET switch provide a sense signal utilizing parasitic bipolar junction transistors. The p-channel MOSFET provides a sense current for the pnp parasitic bipolar junction transistor, The n-channel MOSFET provides a sense current for the npn parasitic bipolar junction transistor. The sense current is stored on a capacitor, and establishes an adaptive offset adjustment to a zero-cross comparator.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: July 11, 2017
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Jindrich Svorc
  • Patent number: 9685778
    Abstract: An integrated circuit includes a vertical Shockley diode and a first vertical transistor. The diode is formed by, from top to bottom of a semiconductor substrate, a first region of a first conductivity type, a substrate of a second conductivity type, and a second region of the first conductivity type having a third region of the second conductivity type formed therein. The vertical transistor is formed by, also from top to bottom, a portion of the second region and a fourth region of the second conductivity type. The third and fourth regions are electrically connected to each other.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: June 20, 2017
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Mathieu Rouviere, Laurent Moindron, Christian Ballon
  • Patent number: 9620637
    Abstract: A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Franz Hirler
  • Patent number: 9606081
    Abstract: A bio-sensing semiconductor structure is provided. A transistor includes a channel region and a gate underlying the channel region. A first dielectric layer overlies the transistor. A first opening extends through the first dielectric layer to expose the channel region. A bio-sensing layer lines the first opening and covers an upper surface of the channel region. A second dielectric layer lines the first opening over the bio-sensing layer. A second opening within the first opening extends to the bio-sensing layer, through a region of the second dielectric layer overlying the channel region. A method for manufacturing the bio-sensing semiconductor structure is also provided.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Ming Chang, Chih-Jen Chan, Chung-Yen Chou, Lee-Chuan Tseng, Shih-Wei Lin, Yuan-Chih Hsieh
  • Patent number: 9559092
    Abstract: An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: January 31, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: T. Jordan Davis
  • Patent number: 9543294
    Abstract: A semiconductor device includes a semiconductor substrate; and a temperature sense diode fixed on the semiconductor substrate. The temperature sense diode includes: an anode electrode; a p-type semiconductor layer being in contact with the anode electrode; an n-type semiconductor layer being in contact with the p-type semiconductor layer; and a cathode electrode being in contact with the n-type semiconductor layer; and the anode electrode. The p-type semiconductor layer, the n-type semiconductor layer, and the cathode electrode are stacked along a thickness direction of the semiconductor substrate. An electric resistivity of the anode electrode or the cathode electrode whichever is located closer to the semiconductor substrate is lower than an electric resistivity of the n-type semiconductor layer and an electric resistivity of the p-type semiconductor layer.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: January 10, 2017
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Takaya Shimono
  • Patent number: 9531187
    Abstract: An overvoltage protection device capable of protecting a power supply line and including in parallel a break-over diode, a controlled switch, and a circuit for controlling the switch.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: December 27, 2016
    Assignee: STMICROELECTRONICS (TOURS) SAS
    Inventors: Jérôme Heurtier, Guillaume Bougrine, Arnaud Florence
  • Patent number: 9484221
    Abstract: A power semiconductor device has a semiconductor body having a first surface and a second surface that runs substantially parallel to the first surface. A first metallization is arranged on the first surface. A second metallization is arranged on the second surface. The semiconductor body includes an n-doped first semiconductor region spaced apart from the first metallization and having a first maximum doping concentration, an n-doped second semiconductor region having a second maximum doping concentration higher than the first maximum doping concentration and adjoining the first semiconductor region, and a third semiconductor region in ohmic contact with the second metallization, arranged between the second metallization and the second semiconductor region, and adjoining the second semiconductor region. The second semiconductor region is made of a semiconductor material which includes electrically active chalcogen impurities as donors.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: November 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gerhard Schmidt, Josef Georg Bauer
  • Patent number: 9461466
    Abstract: An overvoltage protection device capable of protecting a power supply line and including in parallel a break-over diode, a controlled switch, and a circuit for controlling the switch.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 4, 2016
    Assignee: STMicroelectronics (Tours) SAS
    Inventors: Jérôme Heurtier, Guillaume Bougrine, Arnaud Florence
  • Patent number: 9461030
    Abstract: A capacitive component region is formed below a temperature detecting diode or below a protective diode. In addition, the capacitive component region is formed below an anode metal wiring line connecting the temperature detecting diode and an anode electrode pad and below a cathode metal wiring line connecting the temperature detecting diode and a cathode electrode pad. The capacitive component region is an insulating film interposed between polysilicon layers. Specifically, a first insulating film, a polysilicon conductive layer, and a second insulating film are sequentially formed on a first main surface of a semiconductor substrate, and the temperature detecting diode, the protective diode, the anode metal wiring line, or the cathode metal wiring line is formed on the upper surface of the second insulating film. Therefore, it is possible to improve the static electricity resistance of the temperature detecting diode or the protective diode.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: October 4, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 9006782
    Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: April 14, 2015
    Assignee: Analog Devices, Inc.
    Inventor: Javier Alejandro Salcedo
  • Publication number: 20150076556
    Abstract: An integrated circuit (IC) device including an electrostatic discharge (ESD) protection network for a high voltage application. The ESD protection network includes a common diode structure coupled between an external contact of the IC device and a substrate of the IC device, such that the common diode structure is forward biased towards the external contact, a Darlington transistor structure coupled between the external contact and the substrate of the IC device, and the Darlington transistor structure includes: an emitter node coupled to the external contact; a collector node coupled to the substrate; and a base node coupled between the emitter node of the Darlington transistor structure and the common diode structure. The at least one ESD protection network further comprises an isolation diode structure coupled between the emitter node and the base node of the Darlington transistor structure such that the isolation diode structure is forward biased towards the base node.
    Type: Application
    Filed: January 20, 2012
    Publication date: March 19, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Patrice Besse, Philippe Givelin, Eric Rolland
  • Patent number: 8956924
    Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Krzysztof Domanski, Cornelius C. Russ, Kai Esmark
  • Patent number: 8946766
    Abstract: Bi-directional silicon controlled rectifier device structures and design structures, as well as fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
  • Publication number: 20150021659
    Abstract: A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal (310) and a second terminal (308). A first lightly doped region (304) having a first conductivity type (N?) is formed on a second lightly doped region (314) having a second conductivity type (P?). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region (400) having the second conductivity type (P+) is formed at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Inventor: Robert N. Rountree
  • Publication number: 20140367739
    Abstract: A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view.
    Type: Application
    Filed: May 26, 2014
    Publication date: December 18, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Akira Muto, Nobuya Koike, Masaki Kotsuji, Yukihiro Narita
  • Patent number: 8907375
    Abstract: A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Sony Corporation
    Inventor: Masashi Yanagita
  • Patent number: 8890205
    Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Kuenemund, Dennis Tischendorf, Uwe Weder
  • Publication number: 20140291721
    Abstract: A protection circuit for metal-oxide-semiconductor field-effect transistors (MOSFETs) that are used as active bypass diodes in photovoltaic solar power systems is disclosed. The protection circuit comprises, a detection circuit for detecting the start of a surge event, a switch disposed to connect the MOSFET's drain to it's gate in response to the start of the surge, a diode in series with the switch, a bistable circuit for keeping the switch closed during the surge, and a means of resetting the bistable circuit after the surge.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: SUNFIELD SEMICONDUCTOR INC.
    Inventor: Steven Andrew Robbins
  • Publication number: 20140264435
    Abstract: According to one embodiment, a semiconductor module includes: a first circuit component: a second circuit component; and a third circuit component. The first circuit component includes: an insulating first substrate; a first conductive layer; a first switching element; and a first diode. The second circuit component includes: an insulating second substrate; a second conductive layer; a second switching element; and a second diode. The second circuit component is disposed between the first circuit component and the third circuit component. The third circuit component includes: an insulating third substrate; a third conductive layer provided on the third substrate and including a third element mounting unit; a third switching element provided on the third element mounting unit; and a third diode provided on the third element mounting unit. A direction from the third switching element toward the third diode is an opposite direction to the first direction.
    Type: Application
    Filed: September 16, 2013
    Publication date: September 18, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomohiro IGUCHI, Masayuki Uchida, Daisuke Hiratsuka, Masako Fukumitsu
  • Patent number: 8829564
    Abstract: A semiconductor device includes a semiconductor substrate and a MOS transistor. The semiconductor substrate has the first main surface and the second main surface facing each other. The MOS transistor includes a gate electrode (5a) formed on the first main surface side, an emitter electrode (11) formed on the first main surface side, and a collector electrode (12) formed in contact with the second main surface. An element generates an electric field in a channel by a voltage applied to the gate electrode (5a), and controls the current between the emitter electrode (11) and the collector electrode (12) by the electric field in the channel. The spike density in the interface between the semiconductor substrate and the collector electrode (12) is not less than 0 and not more than 3×108 unit/cm2. Consequently, a semiconductor device suitable for parallel operation is provided.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 9, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 8772836
    Abstract: To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. A semiconductor device has a transistor element and a rectifying element on a single substrate. The transistor element has an active layer formed on the substrate and three electrodes (source electrode, drain electrode, and gate electrode) disposed on the active layer. The rectifying element has an anode electrode disposed on the active layer, a cathode electrode which is the drain electrode, and a first auxiliary electrode between the anode electrode and cathode electrode.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: July 8, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Osamu Machida
  • Publication number: 20140167106
    Abstract: Protection circuit architectures with integrated supply clamps and methods of forming the same are provided herein. In certain implementation, an integrated circuit interface protection device includes a first diode protection structure and a first thyristor protection structure electrically connected in parallel between a signal pin a power high supply. Additionally, the protection device includes a second diode protection structure and a second thyristor protection structure electrically connected in parallel between the signal pin and a power low supply. Furthermore, the protection device includes a third diode protection structure and a third thyristor protection structure electrically connected in parallel between the power high supply and the power low supply.
    Type: Application
    Filed: February 1, 2013
    Publication date: June 19, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: Javier Alejandro Salcedo
  • Publication number: 20140167101
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate of a first conductivity type. The TVS includes a buried dopant region of a second conductivity type disposed and encompassed in an epitaxial layer of the first conductivity type wherein the buried dopant region extends laterally and has an extended bottom junction area interfacing with the underlying portion of the epitaxial layer thus constituting a Zener diode for the TVS device. The TVS device further includes a region above the buried dopant region further comprising a top dopant layer of a second conductivity type and a top contact region of a second conductivity type which act in combination with the epitaxial layer and the buried dopant region to form a plurality of interfacing PN junctions constituting a SCR acting as a steering diode to function with the Zener diode for suppressing a transient voltage.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Limin Weng
  • Patent number: 8748938
    Abstract: There is provided a solid-state imaging device in which a plurality of pixels is two-dimensionally arranged in a pixel region. Each of the pixels is formed in an island-shaped semiconductor. In this island-shaped semiconductor, a signal line N+ region and a P region are formed from the bottom. On an upper side surface of this P region, an N region and a P+ region are formed from an inner side of the island-shaped semiconductor. Above the P region, a P+ region is formed. By setting the P+ region and the P+ region to have a low-level voltage and setting the signal line N+ region to have a high-level voltage that is higher than the low-level voltage, signal charges accumulated in the N region are discharged to the signal line N+ region via the P region.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: June 10, 2014
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada
  • Patent number: 8742455
    Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 3, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Edward Coyne
  • Patent number: 8716747
    Abstract: A diode region and an IGBT region are formed in a semiconductor layer of a semiconductor device. A lifetime controlled region is formed in the semiconductor layer. In a plan view, the lifetime controlled region has a first lifetime controlled region located in the diode region and a second lifetime controlled region located in a part of the IGBT region. The second lifetime controlled region extends from a boundary of the diode region and the IGBT region toward the IGBT region. In the plan view, a tip of the second lifetime controlled region is located in a forming area of the body region in the IGBT region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: May 6, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Jun Saito, Sachiko Aoi, Takahide Sugiyama
  • Patent number: 8692289
    Abstract: Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ti Su, Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
  • Patent number: 8680573
    Abstract: Device structures, design structures, and fabrication methods for a silicon controlled rectifier. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. A doped region of a second conductivity type is formed in the well. A cathode of a silicon controlled rectifier and a cathode of a diode are formed in the device region. The silicon controlled rectifier comprises a first portion of the well and an anode comprised of a first portion of the doped region. The diode comprises a second portion of the well and an anode comprised of a second portion of the doped region.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: James P. Di Sarro, Robert J. Gauthier, Jr., Junjun Li
  • Patent number: 8659079
    Abstract: Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 25, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Wei-Ming Liao, Tieh-Chiang Wu
  • Publication number: 20140027815
    Abstract: Fast turn on silicon controlled rectifiers for ESD protection. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of a second conductivity type; a second well of the second conductivity type; a first diffused region of the first conductivity type and coupled to a first terminal; a first diffused region of the second conductivity type; a second diffused region of the first conductivity type; a second diffused region of the second conductivity type in the second well; wherein the first diffused region of the first conductivity type and the first diffused region of the second conductivity type form a first diode, and the second diffused region of the first conductivity type and the second diffused region of the second conductivity type form a second diode, and the first and second diodes are series coupled between the first terminal and the second terminal.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ti Su, Tzu-Heng Chang, Jen-Chou Tseng, Ming-Hsiang Song
  • Patent number: 8604515
    Abstract: A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: December 10, 2013
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Benjamin Morillon
  • Patent number: 8507945
    Abstract: A semiconductor device includes a semiconductor substrate and a MOS transistor. The semiconductor substrate has the first main surface and the second main surface facing each other. The MOS transistor includes a gate electrode (5a) formed on the first main surface side, an emitter electrode (11) formed on the first main surface side, and a collector electrode (12) formed in contact with the second main surface. An element generates an electric field in a channel by a voltage applied to the gate electrode (5a), and controls the current between the emitter electrode (11) and the collector electrode (12) by the electric field in the channel. The spike density in the interface between the semiconductor substrate and the collector electrode (12) is not less than 0 and not more than 3×108 unit/cm2. Consequently, a semiconductor device suitable for parallel operation is provided.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: August 13, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Publication number: 20130200428
    Abstract: A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal (310) and a second terminal (308). A first lightly doped region (304) having a first conductivity type (N?) is formed on a second lightly doped region (314) having a second conductivity type (P?). A first heavily doped region having the second conductivity type (P+ ) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+ ) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region (400) having the second conductivity type (P+ ) is formed at least partially within the first lightly doped region at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 8, 2013
    Inventor: Robert Newton Rountree
  • Patent number: 8471291
    Abstract: In a semiconductor device in which a diode and an IGBT are formed in a main region of a same semiconductor substrate, in order to obtain a sufficiently large sense IGBT current in a stable manner, a sense region is provided with a first region in which a distance from an end of a main cathode region on a side of the sense region in a plan view of the semiconductor substrate is equal to or longer than 615 ?m. Alternatively, in order to obtain a sufficiently large sense diode current in a stable manner, the sense region is provided with a second region in which a distance from the main cathode region in a plan view of the semiconductor substrate is equal to or shorter than 298 ?m. The sense region may be provided with both the first region and the second region.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: June 25, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Akitaka Soeno
  • Patent number: 8461623
    Abstract: A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: June 11, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shuhei Nakata
  • Publication number: 20130119433
    Abstract: Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 16, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Taiwan Semiconductor Manufacturing Company L
  • Patent number: RE44547
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 22, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Gary H. Loechelt, John M. Parsey, Peter J. Zdebel, Gordon M. Grivna
  • Patent number: RE45365
    Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: February 10, 2015
    Assignee: Semiconductor Components Industries
    Inventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna