Combined With Other Solid-state Active Device In Integrated Structure Patents (Class 257/146)
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Patent number: 8461623Abstract: A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.Type: GrantFiled: April 23, 2009Date of Patent: June 11, 2013Assignee: Mitsubishi Electric CorporationInventor: Shuhei Nakata
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Publication number: 20130119433Abstract: Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.Type: ApplicationFiled: October 26, 2012Publication date: May 16, 2013Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventor: Taiwan Semiconductor Manufacturing Company L
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Publication number: 20130100559Abstract: A semiconductor component includes a semiconductor substrate, and a doped well having a well terminal and a transistor structure having at least one potential terminal formed in the semiconductor substrate. The transistor structure has a parasitic thyristor, and is at least partly arranged in the doped well. The potential terminal and the well terminal are connected via a resistor.Type: ApplicationFiled: April 19, 2012Publication date: April 25, 2013Applicant: Infineon Technologies AGInventors: Thomas Kuenemund, Dennis Tischendorf, Uwe Weder
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Patent number: 8421095Abstract: A method of fabricating a light emitting diode array, comprising: providing a temporary substrate; forming a first light emitting stack and a second light emitting stack on the temporary substrate; forming a first insulating layer covering partial of the first light emitting stack; forming a wire on the first insulating layer and electrically connecting to the first light emitting stack and the second light emitting stack; forming a second insulating layer fully covering the first light emitting stack, the wire and partial of the second light emitting stack; forming a metal connecting layer on the second insulating layer and electrically connecting to the second light emitting stack; forming a conductive substrate on the metal connecting layer; removing the temporary substrate; and forming a first electrode connecting to the first light emitting stack.Type: GrantFiled: December 30, 2011Date of Patent: April 16, 2013Assignee: Epistar CorporationInventor: Chao-Hsing Chen
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Publication number: 20130056792Abstract: An integrated circuit comprising electro-static discharge (ESD) protection circuitry arranged to provide ESD protection to an external terminal of the integrated circuit. The ESD protection circuitry comprises: a thyristor circuit comprising a first bipolar switching device operably coupled to the external terminal and a second bipolar switching device operably coupled to another external terminal, a collector of the first bipolar switching device being coupled to a base of the second bipolar switching device and a base of the first bipolar switching device being coupled to a collector of the second bipolar switching device. A third bipolar switching device is also provided and operably coupled to the thyristor circuit and has a threshold voltage for triggering the thyristor circuit, the threshold voltage being independently configurable of the thyristor circuit.Type: ApplicationFiled: May 18, 2010Publication date: March 7, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Patrice Besse, Jean Philippe Laine
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Patent number: 8378455Abstract: An electric component arrangement is described, comprising a semiconductor component (1) and a varistor body (2), which is contact-connected to the semiconductor component in order to protect the latter against electrostatic discharges. The semiconductor component and the varistor body are arranged on a common carrier (3) containing a highly thermally conductive ceramic.Type: GrantFiled: May 14, 2009Date of Patent: February 19, 2013Assignee: Epcos AGInventors: Thomas Feichtinger, Guenter Engel, Axel Pecina
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Patent number: 8362519Abstract: The present teachings provide a semiconductor device comprising: an IGBT element region, a diode element region and a boundary region provided between the IGBT element region and the diode element region are formed in one semiconductor substrate. The boundary region comprises a second conductivity type first diffusion region, a first conductivity type second diffusion region, and a second conductivity type third diffusion region. A first drift region of the IGBT element region contiguously contacts the first diffusion region of the boundary region, and a second drift region of the diode element region contiguously contacts the first diffusion region of the boundary region. A first body region of the IGBT element region contiguously contacts the second diffusion region of the boundary region, and a second body region of the diode element region contiguously contacts the second diffusion region of the boundary region.Type: GrantFiled: December 9, 2011Date of Patent: January 29, 2013Assignee: Toyota Jidosha Kabushiki KaishaInventor: Akitaka Soeno
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Patent number: 8330185Abstract: A semiconductor device, including a semiconductor substrate in which a diode region and an IGBT region are formed, is provided. A lifetime control region is formed within a diode drift region. The diode drift region and the IGBT drift region are a continuous region across a boundary region between the diode region and the IGBT region. A first separation region and a second separation region are formed within the boundary region. The first separation region is formed of a p-type semiconductor, formed in a range extending from an upper surface of the semiconductor substrate to a position deeper than both of a lower end of an anode region and a lower end of a body region, and bordering with the anode region. The second separation region is formed of a p-type semiconductor, formed in a range extending from the upper surface of the semiconductor substrate to a position deeper than both of the lower end of the anode region and the lower end of the body region, and bordering with the body region.Type: GrantFiled: September 23, 2011Date of Patent: December 11, 2012Assignee: Toyota Jidosha Kabushiki KaishaInventor: Akitaka Soeno
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Publication number: 20120286321Abstract: The semiconductor device for protection from electrostatic discharges comprises several modules (MDi) for protection from electrostatic discharges comprising triggerable elements (TRi) coupled with triggering means, the said modules being connected between two terminals by the intermediary of a resistive network (R). A common semiconductor layer contacts all of the modules, each triggerable element (TRi) having at least one gate (GHi), and the triggering means comprise a single triggering circuit (TC) common to all of the triggerable elements and whose output is connected to the gates of all of the triggerable elements.Type: ApplicationFiled: April 26, 2012Publication date: November 15, 2012Applicant: STMicroelectronics SAInventors: Philippe Galy, Jean Jimenez
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Publication number: 20120281329Abstract: This invention discloses an electronic device formed as an integrated circuit (IC) wherein the electronic device further includes a transient voltage suppressing (TVS) circuit for suppressing a transient voltage. The transient voltage suppressing (TVS) circuit includes a Zener diode connected between a ground terminal and a node for triggering a snapback circuit. In one embodiment, this node may be a Vcc terminal. The TVS device further includes a snapback circuit connected in parallel to the Zener diode for conducting a transient voltage current with a snapback current-voltage (I-V) characteristic upon turning on of the snapback circuit. And, the TVS device further includes a snapback suppressing circuit connected in series with the snapback circuit for conducting a current with an I-V characteristic complementary to the snapback-IV characteristic for clamping a snapback voltage.Type: ApplicationFiled: July 10, 2012Publication date: November 8, 2012Inventor: Shekar Mallikarjunaswamy
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Patent number: 8299496Abstract: Provided is a semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed. A separation region formed of a p-type semiconductor is formed in a range between the diode region and the IGBT region and extending from an upper surface of the semiconductor substrate to a position deeper than both a lower end of an anode region and a lower end of a body region. A diode lifetime control region is formed within a diode drift region. A carrier lifetime in the diode lifetime control region is shorter than that in the diode drift region outside the diode lifetime control region. An end of the diode lifetime control region on an IGBT region side is located right below the separation region.Type: GrantFiled: September 23, 2011Date of Patent: October 30, 2012Assignee: Toyota Jidosha Kabushiki KaishaInventors: Tatsuji Nagaoka, Akitaka Soeno
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Patent number: 8294174Abstract: This disclosure discloses a light-emitting device comprising a substrate; and a plurality of rectifying units, comprising a first rectifying unit and a second rectifying unit, formed on the substrate for receiving and regulating an alternating current signal into a direct current signal. Each of the rectifying units comprises a contact layer and a schottky metal layer. The light-emitting device further comprises a plurality of light-emitting diodes receiving the direct current signal; and a first terminal provided on the substrate and covering the contact layer of the first rectifying unit and the schottky metal layer of the second rectifying unit.Type: GrantFiled: August 27, 2010Date of Patent: October 23, 2012Assignee: Epistar CorporationInventors: Chao-Hsing Chen, Yu-Pin Hsu
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Patent number: 8164110Abstract: The present invention relates to integration of lateral high-voltage devices, such as a lateral high-voltage diode (LHVD) or a lateral high-voltage thyristor, with other circuitry on a semiconductor wafer, which may be fabricated using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, or the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The reverse breakdown voltage capability of the LHVD may be increased by using an intrinsic material between the anode and the cathode. Similarly, in a lateral high-voltage thyristor, such as a lateral high-voltage Silicon-controlled rectifier (LHV-SCR), the withstand voltage capability of the LHV-SCR may be increased by using an intrinsic material between the anode and the cathode.Type: GrantFiled: November 18, 2010Date of Patent: April 24, 2012Assignee: RF Micro Devices, Inc.Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
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Publication number: 20120091504Abstract: In one embodiment, a bi-directional ESD device is formed to have a third harmonic at frequencies no less than about one gigahertz wherein the third harmonic has a magnitude that is no greater than about minus thirty five dBm.Type: ApplicationFiled: October 19, 2010Publication date: April 19, 2012Inventors: T. Jordan Davis, Ali Salih
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Publication number: 20120091503Abstract: The present invention discloses a high-voltage ESD protection device including a silicon controlled rectifier and a first PNP transistor. The silicon controlled rectifier includes a high-voltage P-well and N-well; a first N+ and P+ diffusion region are formed in the high-voltage P-well; a second N+ and P+ diffusion region are formed in the high-voltage N-well. The first PNP transistor comprises an N-type buried layer; a low-voltage N-well formed in the N-type buried layer; and a base, emitter and collector formed in the low-voltage N-well. The base and emitter are shorted together; the collector is shorted to the second N+ diffusion region and the second P+ diffusion region; the first N+ diffusion region is shorted to the first P+ diffusion region to act as a ground terminal. The high-voltage ESD protection device can effectively adjust the ESD trigger voltage and improve the snapback sustaining voltage after the device is switched on.Type: ApplicationFiled: October 18, 2011Publication date: April 19, 2012Inventor: Qing Su
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Publication number: 20120049241Abstract: In a high voltage ESD protection structure with a gate voltage reference and low impedance load, the CDM robustness of the structure is improved by including a gate resistor and a reverse path diode.Type: ApplicationFiled: August 27, 2010Publication date: March 1, 2012Inventor: Vladislav Vashchenko
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Patent number: 8125002Abstract: A semiconductor device includes a semiconductor substrate, an insulated gate transistor formed to the semiconductor substrate, a diode formed to the semiconductor substrate, and a control transistor formed to the semiconductor substrate. A first current terminal of the insulated gate transistor is coupled to a cathode of the diode at a high potential side. A second current terminal of the insulated gate transistor is coupled to an anode of the diode at a low potential side. The control transistor is configured to turn off the insulated gate transistor by reducing a potential of a gate terminal of the insulated gate transistor when the diode conducts an electric current.Type: GrantFiled: November 6, 2008Date of Patent: February 28, 2012Assignee: DENSO CorporationInventors: Yutaka Fukuda, Yukio Tsuzuki
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Publication number: 20110309409Abstract: A semiconductor device includes: a semiconductor substrate having an electronic circuit including a power supply line and a ground line formed thereon; and an electrostatic discharge protection element provided between the power supply line and the ground line on the semiconductor substrate, the electrostatic discharge protection element including a thyristor and a trigger diode driving the thyristor, wherein the trigger diode includes an anode diffusion layer formed on the semiconductor substrate, a cathode diffusion layer formed on the semiconductor substrate apart from the anode diffusion layer, and a gate electrode formed between the anode diffusion layer and the cathode diffusion layer on the semiconductor substrate, a gate insulation film being interposed between the semiconductor substrate and the trigger diode, and an external terminal to be connected to an external power supply is electrically connected to the gate electrode.Type: ApplicationFiled: June 10, 2011Publication date: December 22, 2011Applicant: SONY CORPORATIONInventor: Takashi Yamazaki
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Patent number: 7968940Abstract: Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n? drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.Type: GrantFiled: September 27, 2007Date of Patent: June 28, 2011Assignee: Anpec Electronics CorporationInventor: Florin Udrea
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Patent number: 7952143Abstract: A semiconductor device in which both an IGBT element region and a diode element region exist in the same semiconductor substrate includes a low lifetime region, which is formed in at least a part of a drift layer within the diode element region and shortens the lifetime of holes. A mean value of the lifetime of holes in the drift layer that includes the low lifetime region is shorter within the IGBT element region than within the diode element region.Type: GrantFiled: May 7, 2009Date of Patent: May 31, 2011Assignee: Toyota Jidosha Kabushiki KaishaInventors: Akitaka Soeno, Yukihiro Hisanaga
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Publication number: 20110062491Abstract: A power semiconductor module (1) includes a first MOS transistor (16) connected to a positive side power supply terminal via a first conductor pattern (11), a first free wheeling diode (17) connected to the positive side power supply terminal via a second conductor pattern (12), a second MOS transistor (18) connected to a negative side power supply terminal via a third conductor pattern (13), and a second free wheeling diode (19) connected to the negative side power supply terminal via a fourth conductor pattern (14). These semiconductor elements (16-19) are connected to a load side output terminal via a common fifth conductor pattern (15). The semiconductor element (16, 17) connected to the positive side power supply terminal and the semiconductor element (18, 19) connected to the negative side power supply terminal are arranged alternately, substantially linearly.Type: ApplicationFiled: April 23, 2009Publication date: March 17, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shuhei Nakata
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Patent number: 7902570Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.Type: GrantFiled: October 9, 2009Date of Patent: March 8, 2011Assignee: Princeton Lightwave, Inc.Inventors: Mark Allen Itzler, Rafael Ben-Michael, Sabbir Sajjad Rangwala
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Patent number: 7902601Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.Type: GrantFiled: December 16, 2008Date of Patent: March 8, 2011Assignee: Semiconductor Components Industries, LLCInventors: Gary H. Loechelt, John M. Parsey, Jr., Peter J. Zdebel, Gordon M. Grivna
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Publication number: 20110006341Abstract: An electrostatic discharge (ESD) protection element using an NPN bipolar transistor, includes: a trigger element connected at one end with a pad. The NPN bipolar transistor includes: a first base diffusion layer; a collector diffusion layer connected with the pad; a trigger tap formed on the first base diffusion layer and connected with the other end of the trigger element through a first wiring; and an emitter diffusion layer and a second base diffusion layer formed on the first base diffusion layer and connected in common to a power supply through a second wiring which is different from the first wiring.Type: ApplicationFiled: June 29, 2010Publication date: January 13, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Kouichi SAWAHATA
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Patent number: 7859012Abstract: In accordance with an embodiment of the present invention, a semiconductor memory device includes an array of thyristor-based memory formed in a silicon-on-insulator (SOI) supporting substrate. A portion of the supporting structure of the SOI substrate has a density of dopants sufficient to assist delivery of a bias to the backside of an insulating layer beneath a thyristor of the thyristor-based semiconductor memory. By enabling biasing of the substrate at the backside of the insulating layer beneath the thyristor, a back-gate control is available for controlling or compensating the gain of a component bipolar device of the thyristor with respect to temperature.Type: GrantFiled: August 10, 2009Date of Patent: December 28, 2010Assignee: T-RAM SemiconductorInventor: Maxim Ershov
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Publication number: 20100314681Abstract: A structure of power semiconductor device integrated with clamp diodes sharing same gate metal pad is disclosed. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon.Type: ApplicationFiled: June 11, 2009Publication date: December 16, 2010Applicant: FORCE MOS TECHNOLOGY CO. LTD.Inventor: Fu-Yuan Hsieh
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Patent number: 7816706Abstract: The power semiconductor device with a four-layer npnp structure can be turned-off via a gate electrode. The first base layer comprises a cathode base region adjacent to the cathode region and a gate base region adjacent to the gate electrode, but disposed at a distance from the cathode region. The gate base region has the same nominal doping density as the cathode base region in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region, which is opposite the cathode metallization. The gate base region has a higher doping density than the cathode base region and/or the gate base region has a greater depth than the cathode base region in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.Type: GrantFiled: January 16, 2008Date of Patent: October 19, 2010Assignee: ABB Technology AGInventors: Munaf Rahimo, Peter Streit
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Publication number: 20100213510Abstract: A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.Type: ApplicationFiled: May 4, 2010Publication date: August 26, 2010Inventors: Michitaka OSAWA, Takamitsu KANAZAWA
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Patent number: 7723727Abstract: Disclosed are a liquid crystal display and a substrate for the same. The substrate comprises first wires formed in one direction on the substrate; second wires intersecting and insulated from the first wires; pixel electrodes formed in pixel regions defined by the first wires and the second wires; and switching elements connected to the first wires, the second wires and the pixel electrodes, wherein an interval between two adjacent second wires has a predetermined dimension that repeatedly varies from one set of adjacent second wires to the next, and a side of the pixel electrodes adjacent to the second wires is shaped in a pattern identical to the second wires such that the pixel electrodes have a wide portion and a narrow portion.Type: GrantFiled: February 28, 2005Date of Patent: May 25, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jang-Kun Song
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Patent number: 7633095Abstract: Integrating high-voltage devices with other circuitry, which may be fabricated on a semiconductor wafer using low-voltage foundry technology, such as a low-voltage complementary metal oxide semiconductor (LV-CMOS) process. The other circuitry may include low-voltage devices, such as switching transistors used in logic circuits, computer circuitry, and the like, or other high-voltage devices, such as a microelectromechanical system (MEMS) switch. The high-voltage devices may be used to create useful high-voltage circuits, such as level-shifting circuits, input protection circuits, charge pump circuits, switching circuits, latch circuits, latching switch circuits, interface circuits, any combination thereof, or the like. The high-voltage circuits may be controlled by the other circuitry.Type: GrantFiled: June 17, 2008Date of Patent: December 15, 2009Assignee: RF Micro Devices, Inc.Inventors: Daniel Charles Kerr, David C. Dening, Julio Costa
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Publication number: 20090302347Abstract: A semiconductor integrated circuit includes a plurality of circuit cells each including a pad on a semiconductor chip. Each of the circuit cells includes a high-side transistor, a level shift circuit, a low-side transistor, a pre-driver, and a pad. The high-side transistor and the low-side transistor are arranged to face each other with the pad interposed therebetween.Type: ApplicationFiled: September 29, 2006Publication date: December 10, 2009Inventors: Hiroki Matsunaga, Masahiko Sasada, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando
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Patent number: 7626193Abstract: A single-photon detector is disclosed that provides reduced afterpulsing without some of the disadvantages for doing so in the prior art. An embodiment of the present invention provides a stimulus pulse to the active area of an avalanche photodetector to stimulate charges that are trapped in energy trap states to detrap. In some embodiments of the present invention, the stimulus pulse is a thermal pulse.Type: GrantFiled: March 27, 2006Date of Patent: December 1, 2009Assignee: Princeton Lightwave, Inc.Inventors: Mark Allen Itzler, Rafael Ben-Michael, Sabbir Sajjad Rangwala
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Patent number: 7622753Abstract: A component formed in a substrate of a first conductivity type, having two inputs and two outputs and: a first diode having its anode connected to a first input and having its cathode connected to a first output; a second diode having its anode connected to a second output and having its cathode connected to the first input; a one-way switch having its anode connected to the first output, its cathode being connected to the second output; and a third diode having its anode connected to the second output, its cathode being connected to the first output; the first, second, and third diodes being formed in a first portion of the substrate separated by a wall of the second conductivity type from a second substrate portion comprising the switch.Type: GrantFiled: August 30, 2006Date of Patent: November 24, 2009Assignee: STMicroelectronics S.A.Inventors: Samuel Menard, Benjamin Cheron, Arnaud Edet
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Publication number: 20090283863Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region of the first conductive type formed in the base region. Also, the semiconductor device includes a buffer layer of the first conductive type formed on the second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity therein of approximately 5×1015 cm?3 or less, and the collector layer has a maximal concentration of the second conductive type impurity therein of approximately 1×1017 cm?3 or more. Further, the ratio of the maximal concentration of the collector layer to the maximal concentration of the buffer layer being greater than 100.Type: ApplicationFiled: July 28, 2009Publication date: November 19, 2009Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Eisuke SUEKAWA
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Publication number: 20090283862Abstract: One of the aspects of the present invention is to provide a semiconductor device, which includes a semiconductor layer of a first conductive type having first and second surfaces. The semiconductor layer includes a base region of a second conductive type formed in the first surface and an emitter region of the first conductive type formed in the base region. Also, the semiconductor device includes a buffer layer of the first conductive type formed on the second surface of the semiconductor layer, and a collector layer of the second conductive type formed on the buffer layer. The buffer layer has a maximal concentration of the first conductive type impurity therein of approximately 5×1015 cm?3 or less, and the collector layer has a maximal concentration of the second conductive type impurity therein of approximately 1×1017 cm?3 or more. Further, the ratio of the maximal concentration of the collector layer to the maximal concentration of the buffer layer being greater than 100.Type: ApplicationFiled: July 28, 2009Publication date: November 19, 2009Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Eisuke SUEKAWA
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Patent number: 7573077Abstract: In accordance with an embodiment of the present invention, a thyristor-based semiconductor memory device may comprise an array of thyristor-based memory formed in an SOI wafer. A supporting substrate may be formed with a density of dopants sufficient to assist delivery of a bias level to the backside of an insulating layer beneath a thyristor. Such conductivity within the substrate may allow reliable back-gate control for the gain of a component bipolar device of the thyristor.Type: GrantFiled: May 4, 2005Date of Patent: August 11, 2009Assignee: T-RAM Semiconductor, Inc.Inventor: Maxim Ershov
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Patent number: 7557386Abstract: A reverse conducting insulated gate bipolar transistor (IGBT) includes a semiconductor substrate having a front side and a back side and a first conductivity region between the front and back sides. The first conductivity region includes a reduced lifetime zone, a first lifetime zone between the reduced lifetime zone and the front side, and an intermediate lifetime zone between the reduced lifetime zone and the back side. Charge carriers in the first lifetime zone have a first carrier lifetime, charge carriers in the reduced lifetime zone have a reduced carrier lifetime shorter than the first carrier lifetime, and charge carriers in the intermediate lifetime zone have an intermediate carrier lifetime shorter than the first carrier lifetime and longer than the reduced carrier lifetime.Type: GrantFiled: March 30, 2006Date of Patent: July 7, 2009Assignee: Infineon Technologies Austria AGInventors: Holger Ruething, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Frank Hille
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Patent number: 7550393Abstract: A solid-state imaging device includes a light sensor formed in a semiconductor substrate. In addition, the solid-state imaging device includes a light block layer with an opening formed through the light block layer over at least a portion of the light sensor. Furthermore, at least one sidewall of the light block layer facing the opening is concave shaped for reducing smear phenomenon.Type: GrantFiled: January 31, 2005Date of Patent: June 23, 2009Assignee: Samsung Electronics Co., Ltd.Inventor: Hee-Geun Jeong
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Patent number: 7508016Abstract: A CMOS image sensor formed on a chip has a ROM disposed on the chip for recording pixel defect locations, chip-by-chip variations such as bias, and other manufacturing production data. Testing results and repair solutions are written to the ROM after production testing. A simple circuit for writing information to the ROM also is provided on the CMOS chip. During operational use of the image sensor, data is read from the on-chip ROM to assist in compensating for manufacturing process variations.Type: GrantFiled: January 17, 2006Date of Patent: March 24, 2009Assignee: Micron Technology, Inc.Inventor: Richard H. Tsai
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Patent number: 7498614Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n (or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.Type: GrantFiled: August 14, 2007Date of Patent: March 3, 2009Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Xing-bi Chen
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Patent number: 7498634Abstract: A semiconductor device includes: a substrate having a first side and a second side; an IGBT; and a diode. The substrate includes a first layer, a second layer on the first layer, a first side N region on the second layer, second side N and P regions on the second side of the first layer, a first electrode in a first trench for a gate electrode, a second electrode on the first side N region and in a second trench for an emitter electrode and an anode electrode, and a third electrode on the second side N and P regions for a collector electrode and a cathode. The first trench penetrates the first side N region and the second layer, and reaches the first layer. The second trench penetrates the first side N region, and reaches the second layer.Type: GrantFiled: January 4, 2007Date of Patent: March 3, 2009Assignee: DENSO CORPORATIONInventors: Yukio Tsuzuki, Norihito Tokura
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Patent number: 7465965Abstract: A semiconductor device including: a bulk semiconductor substrate; an access transistor; a thruster formed on the bulk semiconductor substrate connecting to the access transistor; an element separating region to separate the region for the access transistor and the region for the thruster from each other; and a wiring layer connecting one of the diffused layers of the access transistor and the cathode of the thruster together through a connecting hole, the impurity region at the anode side of the thruster being composed of a p-type impurity region, an n-type impurity region, p-type impurity region, and an n-type impurity region, which are formed sequentially in the depth wise direction, with the lowermost n-type impurity region receiving the same voltage as that applied to the anode at the time of data holding.Type: GrantFiled: August 30, 2006Date of Patent: December 16, 2008Assignee: Sony CorporationInventor: Ikuhiro Yamamura
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Patent number: 7462922Abstract: A semiconductor device provided with a temperature detection function having a high temperature detection accuracy for improving the ESD resistance of a temperature detection diode. The semiconductor device has a semiconductor element. A temperature detection diode is used to detect the temperature of the semiconductor element and an ambient temperature of the semiconductor element. A protection diode is connected between a cathode of the temperature detection diode and a ground side of the semiconductor element when the semiconductor element is activated.Type: GrantFiled: December 10, 2004Date of Patent: December 9, 2008Assignee: Kabushiki Kaisha Toyota JidoshokkiInventors: Shogo Mori, Kenji Ono
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Publication number: 20080191238Abstract: According to the invention there is provided a semiconductor device including: at least one cell including a base region of a first conductivity type having disposed therein at least one emitter region of a second conductivity type; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; a collector region of a first conductivity type; a collector contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; the device further including: a first gate in communication with a base region so that a MOSFET channel can be formed between an emitter region and the first well region; and at least one embedded region embedded in the first well region; in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region can extend to a junction between the first wellType: ApplicationFiled: August 10, 2005Publication date: August 14, 2008Applicant: ECO SEMICONDUCTORS LIMITEDInventors: Sankara Narayanan Ekkanath Madathil, Mark Robert Sweet, Konstantin Vladislavovich Vershinin
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Patent number: 7326969Abstract: A semiconductor memory device may comprise a thyristor-based memory having some portions formed in strained silicon, and other portions formed in relaxed silicon. In a further embodiment, a thyristor in the thyristor-based memory may be formed in a region of relaxed silicon germanium, while an access device to the thyristor-based memory may have a body region incorporating a portion of a layer of strained silicon. In yet a further embodiment, different regions of the thyristor may be formed in vertical aligned relationship relative to an upper surface of the relaxed silicon germanium. For this embodiment, the thyristor may be formed substantially within the depth of the relaxed silicon germanium layer. In a method of forming the semiconductor device, relaxed silicon may be deposited over exposed regions of a silicon substrate, and a thin layer of strained silicon formed over a portion of the substrate having silicon germanium.Type: GrantFiled: December 2, 2004Date of Patent: February 5, 2008Assignee: T-RAM Semiconductor, Inc.Inventor: Andrew E. Horch
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Patent number: 7253486Abstract: In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.Type: GrantFiled: July 31, 2002Date of Patent: August 7, 2007Assignee: Freescale Semiconductor, Inc.Inventors: Bruce M. Green, Ellen Lan, Phillip Li
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Publication number: 20070158680Abstract: A semiconductor device includes: a semiconductor substrate having first and second semiconductor layers; an IGBT having a collector region, a base region in the first semiconductor layer, an emitter region in the base region, and a channel region in the base region between the emitter region and the first semiconductor layer; a diode having an anode region in the first semiconductor layer and a cathode electrode on the first semiconductor layer; and a resistive region. The collector region and the second semiconductor layer are disposed on the first semiconductor layer. The resistive region for increasing a resistance of the second semiconductor layer is disposed in a current path between the channel region and the cathode electrode through the first semiconductor layer and the second semiconductor layer with bypassing the collector region.Type: ApplicationFiled: January 3, 2007Publication date: July 12, 2007Applicant: DENSO CORPORATIONInventors: Yoshihiko Ozeki, Norihito Tokura, Yukio Tsuzuki
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Patent number: 7227197Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.Type: GrantFiled: June 3, 2004Date of Patent: June 5, 2007Assignee: Third Dimension (3D) Semiconductor, Inc.Inventor: Xingbi Chen
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Patent number: 7224002Abstract: Disclosed herein is an improved thyristor-based memory cell. In one embodiment, the cell is formed in a floating substrate using Silicon-On-Insulator (SOI) technology. The cell preferably incorporates a lateral thyristor formed entirely in the floating substrate, and which is gated by a second word line. The cathode of the thyristor also comprises a source of an access transistor, whose drain is connected to the bit line of the device, and which is gated by a first word line. A trapping layer is built into the floating substrate, and when writing to the cell, pulses are added to cause holes to be trapped on the trapping layer for a logic state ‘1’ and to cause electrons to be trapped on the trapping layer for a logic state ‘0.’ Trapping of charges on the trapping layer adds extra margin to the stored data states, prevents their degradation, and renders the cell non-volatile.Type: GrantFiled: May 6, 2004Date of Patent: May 29, 2007Assignee: Micron Technology, Inc.Inventor: Arup Bhattacharyya
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Patent number: 7173290Abstract: A semiconductor switch includes a thyristor and a current shunt, preferably a transistor in parallel with and controlled by the thyristor, which shunts thyristor current at turn-off. The thyristor includes a portion of a bottom drift layer, with a p-n junction formed below a gate adjacent to the bottom drift layer to establish a depletion region with a high potential barrier to thyristor current flow at turn-off. The bottom drift layer also provides the transistor base, as well as a current path allowing the transistor base current to be controlled by the thyristor. The switch is voltage-controlled device using an insulated gate for turn-on and turn-off.Type: GrantFiled: August 15, 2003Date of Patent: February 6, 2007Assignee: Teledyne Licensing, LLCInventor: Hsueh-Rong Chang