Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: In a power semiconductor device, an n-base is formed on a p-emitter layer. On the n-base layer, a p-base layer, an n-emitter layer, and a high-concentration p-layer are formed laterally. In the p-base layer, an n-source layer is formed a specified distance apart from the n-emitter layer. In the n-emitter layer, a p-source layer is formed a specified distance apart from the high-concentration p-layer. A first gate electrode is formed via a first gate insulating film on the region sandwiched by the n-source layer and the n-emitter layer. A second gate electrode is formed via a second gate insulating film on the region sandwiched by the high-concentration p-layer and the p-source layer. On the p-emitter layer, a first main electrode is formed. A second main electrode is formed so as to be in contact with the p-base layer, the n-source layer, and the p-source layer.

Abstract: An auxiliary MOSFET is integrated into a lateral IGBT structure with the source and drain of the auxiliary MOSFET in parallel with the emitter-base circuit of the IGBT. A driver, integrated with the IGBT chip, turns off the base emitter voltage to the IGBT before turning off the auxiliary MOSFET during turn off. The auxiliary MOSFET is turned off again at the beginning of the conduction period to ensure full conductivity modulation of the DMOS drain and maximum gain of the PNP transistor. Short circuit protection and overtemperature protection circuits are also integrated into the chip.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to edges of the hexagon that are separated by other edges. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the other edges of the hexagon. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: A semiconductor controlled rectifier is disclosed herein. In a preferred embodiment, a first n-doped region 112 is formed in a p-doped semiconductor layer 126. A first n-well region 122 is formed within the first doped region 112. This well 122 extends through the region 112 and into the layer 126. A second n-doped region 114 is also formed in the layer 126. The second region 1114 is spaced from the first region 112. A second n-well 142 is formed in the layer 126 such that it partially overlaps the second region 114. A n-doped region 144 and a p-doped region 146 are each formed in the second n-well 142 and abut one another.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. In some embodiments, the device has two gate drives and is a four terminal device. In other embodiments, the device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: In a collector side portion of an insulated gate bipolar transistor, there are provided, for example, a p-type collector layer diffused into an n-type semiconductor region, an n-type carrier extraction layer diffused into the semiconductor region opposite to an emitter side portion and a field effect transistor portion having an auxiliary gate disposed between the collector layer and the carrier extraction layer. The field effect transistor portion is controlled by the auxiliary gate in such a manner that during its "off" state the collector layer is separated from the carrier extraction layer connected to a collector terminal to cause its potential to float so that the majority carriers flowing in a transverse direction below the collector layer prevent minority carriers from being injected from the collector layer into the semiconductor region, thereby shortening the "off" operation time.

Abstract: A composite integrated circuit device includes a semiconductor element chip, a positioning guide formed on the semiconductor element chip, and an electronic element set in a preset position on the semiconductor element chip in a self-alignment manner by means of the positioning guide and mounted thereon. Also disclosed is are lateral, thin film devices with tapered shapes to reduce breakdown.

Abstract: An insulated-gate bipolar transistor (IGBT) is connected in reverse-parallel with a current-regenerative diode which, for economy of manufacture, is integrated with the IGBT. Such a diode may extend laterally on an IGBT chip, with two conductivity regions forming the diode respectively connected to emitter and collector electrodes of the IGBT. Alternatively, the diode may be formed by short-circuiting a buffer layer and a collector layer. By such integration, greater device packing density can be realized.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with, but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: A MOS-controlled thyristor which has current saturation characteristics and does not have any parasitic thyristor structure. The device requires only a single gate drive and is a three terminal device. The device can be constructed in a cellular geometry. In all embodiments, the device has superior turn-off characteristics and a wider Safe-Operating-Area because the N.sup.++ emitter/P base junction is reverse biased during turn-off.

Abstract: A semiconductor device functioning as a diode, includes an insulated-gate field effect transistor for determining a breakdown voltage, and a bipolar transistor connected to the field effect transistor for amplifying a drain current of the field effect transistor. The field effect transistor and the bipolar transistor are formed in the same semiconductor substrate.

Abstract: The protection device comprises a MOS transistor formed on the substrate of the integrated circuit and connected between a circuit pad and a reference terminal of the integrated circuit. A thyristor formed on the substrate is connected between the pad and the reference terminal. The control electrode of this thyristor consists of a region of the substrate in such a way that the thyristor can be triggerred by a current of charge carriers produced in the substrate by avalanche when a voltage rise occurs between the substrate and the drain of the MOS transistor.

Abstract: A high voltage MIS transistor includes a well region of a second conduction type formed by a step of injecting ions from the surface side of a semiconductor substrate of a first conduction type and a thermal diffusion step after the ion injecting step; an MIS part including a base layer of a first conduction type formed in one end portion of the well region, a base contact layer of a first conduction type which is formed in the base layer of a first conduction type and to which an emitter potential is applied, and a gate electrode provided so as to extend from an emitter layer of a second conduction type to the well region through an insulation gate film; and, a collector part including a base layer of a second conduction type formed in the other end portion of the well region, a collector layer of a first conduction type formed in the base layer of a second conduction type, and a high concentration contact layer of a first conduction type which is formed in the collector layer and to which a collector potent

Abstract: A constant-voltage diode has a first semiconductor region of a first conductivity type, an adjoining semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type adjoining the second semiconductor region, and a fourth semiconductor region of the first conductivity type partially surrounded by the second semiconductor region. At low reverse biases between a cathode electrode and an anode electrode, the behavior of the device is determined by the pn junction between the first and second semiconductor regions. As the reverse biasing increases, the depletion layers of that junction will reach the fourth semiconductor region, but the reverse bias at this time is insufficient to break down that junction. A further increase of reverse bias causes breakdown of the pn junction between the third and fourth semiconductor regions. This effect is achieved by suitable impurity concentrations in the semiconductor regions.

Abstract: In a semiconductor device having insulated gate field effect transistors and bipolar transistors, a buried layer of a first conductivity type having an impurity concentration higher than that of a second layer of the first conductivity type is disposed in at least a lower region between a second layer of a second conductivity type and a third layer of the second conductivity type and in the vicinity of a boundary between the second layer of the first conductivity type, which serves as back gates of the field effect transistors and base layers of the bipolar transistors, and the first layer of the second conductivity type.

Abstract: The semiconductor device is composed of a thyristor and a MOSFET cascade-connected. The thyristor includes a bipolar transistor cascade-connected with the MOSFET, the base (p.sup.-- semiconductor region) of which is adapted to be punched through by the application of a working voltage. Thus, the thyristor can easily be latched and unlatched in response to the turn-on and turn-off of the MOSFET. Thus the semiconductor device can be securely on/off controlled by only the single gate (G) of the MOSFET. By using such semiconductor device as a switching element in a flash control device, a high performance flash control device with high flashing efficiency is provided.

Abstract: The semiconductor device is formed of an EST part and an IGBT part, wherein the EST part has a first MOSFET and a second MOSFET synchronously switching, and the IGBT part has a third MOSFET controllable independently from them. At a turn-off of the semiconductor device, when turning off the first and second MOSFETs while keeping the third MOSFET at an on-state, IGBT operation remains. Thus, the current path which tends to flow to an emitter region changes toward an emitter electrode side even if the recovery of the potential barrier is late due to the junction in the emitter region, and the charge accumulation to the emitter region is restrained. After the potential barrier is recovered, the third MOSFET is turned off. Controllable turn-off current can be enlarged and turn-off time can be shortened.

Abstract: To avoid peripheral current-density overshoots in a turn-off power semiconductor device, in particular an MOS-controlled thyristor MCT having a multiplicity of separate MCT cells ((M1, . . . , M3), the unit cells (here: MCT cells (M1, . . . , M3)) are combined in groups to form segments (SE) and are surrounded peripherally by peripheral short-circuit regions (10, 15) which are embedded in the semiconductor substrate (1) from the cathode side and are directly connected to the cathode contact (2). At the same time, the peripheral short-circuit regions (10) are of the same conductivity type as the anode-side emitter layer (8).

Abstract: A channel in which electron current is supplied from n.sup.+ type source layer to an n.sup.- type base layer is formed in a thyristor portion by using a first gate electrode to have an electrical connection in a thyristor state. Injection of hole current to a p type base layer, which is necessary to maintain the thyristor state is extracted to a source terminal by a control MOSFET portion including a second gate electrode a turn-off time and the state of this device is changed to the transistor state similar to that in the IGBT so that a short switching time turn-off is realized.

Abstract: An insulated gate bipolar transistor comprises an insulation film (7) formed on a channel region (6) and a gate electrode (8) formed on the insulation film (7). The end portion of the gate electrode (8) has recesses so that the gage electrode (8) covers part of the channel region (6) at a predetermined rate. The rate may be made small to increase a channel resistance so that an excessive current at the time of load short-circuiting can be suppressed. In place of the recesses, a step structure may be provided. Further the gate electrode (8) may cover part of the channel region (6) without providing the recesses.

Abstract: A semiconductor device including a switching device such as a MOSFET or an IGBT, and an avalanche device for protecting the switching device by generating an avalanche current when an overvoltage is applied to the switching device. The avalanche device shares a drift layer, that is, an epitaxial layer with the switching device. With this arrangement, the avalanche voltage of the avalanche device follows changes in the withstanding voltages of the switching device due to variations in the thickness or impurity concentration of the epitaxial layer or temperature. This makes it possible to reduce the margin between the avalanche voltage of the avalanche device and the withstanding voltage of the switching device, and to positively protect the switching device from damage.

Abstract: A semiconductor integrated circuit is provided which can have a high holding current without the penalty of a high gate current. Such a circuit includes a PNPN device and junction bipolar transistor in which a further doped region of the same conductivity type as the transistor collector region and more heavily doped than the collector region prevents the devices affecting each other. The junction bipolar transistor has a current gain of at least 10 and base-collector and base-emitter junctions with reverse breakdown voltages of at least 50 volts. A PN diode can also be used in the circuit.

Abstract: A turn-off power semiconductor component subdivided into unit cells (EZ), including between an anode (A) and a cathode (K) in a semiconductor substrate (1) five layers in p-n-p-n-p sequence, namely an anode layer (10) an n-type base layer (9), a p-type base layer (8), a turn-off region (6), a cathode region (7) adjoining the turn-off region, and a p-doped short-circuit region (5). On the cathode side in every unit cell (EZ), a first MOSFET (M1) which can be driven via a first insulated gate electrode (G1) is provided for the purpose of switching between the five-layer structure and a conventional thyristor four-layer structure. A second MOSFET (M2) having a second gate electrode (G2) prevents a breakdown between the p-type short-circuit region (5) and the turn-off region (6) during turn-off.

Abstract: A semiconductor switching device that is suitable for use as a remote isolation device (RID) in telephone networks. The semiconductor switching device is a two-terminal voltage sensitive device that switches from an open-circuit condition to a short-circuit condition at a fixed breakover voltage, appears as an open-circuit below the breakover voltage, and appears as a short-circuit above the breakover voltage. When semiconductor switching devices are installed in a telephone network, they are held in their short-circuit condition by the network voltage supply and do not affect the normal operation of the network but will switch to their open-circuit condition if the network voltage supply is reduced to below the breakover voltage, and therefore, parts of the network may be isolated from each other by reducing the voltage supply. Isolation of the parts of the network from each other facilitates testing for maintenance purposes.

Abstract: A bidirectional protection component comprises two reverse connected thyristors, each of which is in anti-parallel with a diode, the gates of the two thyristors being interconnected and floating. This component, which can be monolithic comprises two vertical thyristors having the same orientation and two vertical diodes having the same orientation, opposite that of the thyristors. Semiconductor regions (P3, N2, P1) constituting the thyristors are common except for their cathode regions (N11, N12). The component comprises three metallizations: a rear surface metallization (M1) connecting the common anodes of the thyristors with the cathodes of the diodes, a first front surface metallization (A1) connecting the cathode (N11) of a thyristor to the anode (P21) of a diode, and a second front surface metallization (A2) connecting the cathode (N12) of the other thyristor to the anode (P22) of the other diode.

Abstract: A conductivity modulation type MISFET, and a control circuit thereof are provided. A semiconductor device 1 comprises a conductivity modulation type MOSFET 1a and a built-in MOSFET 1b which is designed to control a source electrode 12a and a control electrode 13 of a parasitic transistor to be in a short state or an open state, said conductivity modulation type MOSFET 1a having a polysilicon gate 6 on an obverse surface of n.sup.- -type conductivity modulation layer 4, a p-type channel diffusion area 7, n.sup.+ -type source diffusion area 8 and a parasitic transistor control electrode 13 conductively connected to the p-type channel diffusion area 7 through a p.sup.+ -type contact area 9.

Abstract: In an MOS-controlled thyristor MCT comprising a multiplicity of adjacently disposed individual MCT cells (MC) having a cell width and which are electrically connected in parallel, either the MCT cells (MC) themselves or cell clusters (15) comprising a few closest-packed MCT cells (MC) are mutually separated by nonemitting gaps (2) which do not inject charge carriers into the cathode base layer and which have lateral linear dimensions greater than or at least equal to the cell width of the MCT cells (MC). As a result of this separation, the full performance of the individual MCT cell (MC) is achieved even in large-area components containing many cells.

Abstract: A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias.

Abstract: In a large-area controlled-turn-off high-power semiconductor component containing a multiplicity of finely structured individual components, a semiconductor device (12) is formed by a multiplicity of small-area semiconductor chips (7) which are accommodated alongside one another in a common housing (13) and connected in parallel. This achievement avoids problems of yield with structures which are becoming finer.

Abstract: A base resistance controlled thyristor with single-polarity and dual-polarity turn-on and turn-off control includes a turn-off device provided between the second base region and the cathode of a thyristor. Controlled turn-off is provided by either a near-zero positive bias or a negative bias being applied to the turn-off device. In the preferred embodiment, the turn-off device is a P-channel depletion-mode MOSFET in the surface of a semiconductor substrate. Accordingly, an accumulation-layer channel can be formed between the second base region and the cathode in response to a negative bias. Alternatively, if single-polarity control is desired, the P-type channel is provided to turn-off the device in response to a near-zero positive bias. In either type of operation, however, advantages are obtained over conventional turn-off devices wherein inversion-layer channels are used.