Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).

Abstract: An inverter apparatus constituted by one or more series connections of plural semiconductor devices each having a pair consisting of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from a conduction state to a blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of the blocking state.

Abstract: A vertical semiconductor component has an integrated switching device, which delivers an electric value correlating with the rear potential. The semiconductor component includes a doping region with a hole, which is free of the doping atoms of the doping region. The hole, when properly sized and contacted, can supply an electric current correlating with the rear potential.

Abstract: In an emitter-switched thyristor with a main thyristor (TH) composed of a p+ anode emitter (1), a drift zone (3') of opposite conductivity type, a zone (4) which has in the switched-off state a blocking zone with respect to zone (3) and an emitter zone (5) at the cathode side, again with an opposite conductivity type, so that a p+n-pn+ zone sequence results, a transistor structure (T) composed of the first three zones of alternating conductivity is provided in parallel thereto with an emitter (1), base (3) and a collector (8). This structure contains a NMOSFET (M1) for directly driving the cathode emitters (5) through the cathode connection (KA). The source of this transistor is contacted by the cathode, as well as the collector zone (8) which forms the channel zone of the MOSFET at the surface of the semiconductor. The corresponding drain zone is connected to the n+ cathode emitter (5) of the main thyristor (TH) by an electric conductor (6).

Abstract: The RBSOA of a device is improved. A gate electrode (10) is linked to a p base layer (4) which is formed in a cell region (CR), and a p semiconductor layer (13) is formed to surround the cell region (CR). An emitter electrode (11) is connected to a top surface of a side diffusion region (SD) of the p semiconductor layer (13) and to a top surface of a margin region (MR) which is adjacent to the side diffusion region (SD), through a contact hole (CH). Further, in these regions, an n.sup.+ emitter layer (5) is not formed. Most of avalanche holes (H) which are created in the vicinity of the side diffusion region (SD) when a high voltage is applied pass through the side diffusion region (SD), while some of the avalanche holes (H) pass through the margin region (MR) and are then ejected to the emitter electrode (11). Since there is no n.sup.+ emitter layer (5) in these paths, a flow of the holes (H) does not conduct a parasitic bipolar transistor. As a result of this, the RBSOA is improved.

Abstract: A memory cell is provided. The memory cell includes a field-effect transistor having a source region, a drain region and a gate coupled to a wordline. The memory cell also includes a vertical bipolar junction transistor that is biased for use of the reverse base current effect to store data. The bipolar junction transistor has an emitter region formed within a source/drain region of the field-effect transistor. The emitter region is self-aligned with a minimum dimension isolation region adjacent to the memory cell and is coupled to a ground line. A portion of the source/drain region acts as the base of the bipolar junction transistor.

Abstract: Methods of forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells therein includes the steps of forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and then forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is then formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is then formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to thereby define a plurality of vertical IGBT cells.

Abstract: The present invention relates to a monolithic assembly of a vertical IGBT transistor and a vertical fast diode connected to the drain of the IGBT transistor, implemented in an N-type semiconductor substrate. The rear (or lower) surface of the structure is uniformly formed of a P-type layer having many openings through which the N-type substrate appears. This rear surface is covered with a material for establishing a Schottky contact with the substrate and an ohmic contact with the P-type layer.

Abstract: An electrostatic discharge protection circuit comprises a semiconductor layer of a first conductivity type, a floating semiconductor layer of a second conductivity type, a first doped region of the first conductivity type, a first doped region of the second conductivity type, a second doped region of the second conductivity type, a gate structure, and a second doped region of the first conductivity type. The floating semiconductor layer of a second conductivity type is in contact with the semiconductor layer of a first conductivity type to establish a junction therebetween. The first doped region of the first conductivity type is formed in the semiconductor layer of a second conductivity type and connected to a first node. The first doped region of the second conductivity type is formed in the semiconductor layer of a first conductivity type and connected to a second node. The second doped region of the second conductivity type spans the junction.

Abstract: In a composite controlled semiconductor device having an insulated gate and a power conversion device using the same, a p type semiconductor region forming no channel is provided in the composite device structure between a plurality of p type semiconductor regions forming a channel and the potential of the p type semiconductor region in an ON state takes a value high enough to inject holes into an n type semiconductor region adjacent to the p type semiconductor region.

Abstract: A first metal electrode layer is formed to be electrically connected with a p base region formed in an n drift region. A second metal electrode layer which is electrically connected with an emitter region provided in the p base region is formed. A direct current power supply unit is provided to be electrically connected with the first and second metal electrode layers. The direct current power supply unit functions as means for applying forward bias to a pn junction between the n emitter region and the p base region.

Abstract: AN IGBT including a collector positioned on one surface of a substrate and a doped structure having a buried region therein positioned on the other surface of the substrate. The buried region defining a drift region in the doped structure extending vertically from the substrate and further defining a doped region in communication with the drift region and adjacent the surface of the doped structure. An emitter positioned on the doped structure in communication with the doped region. An insulating layer positioned on the doped structure with a metal gate positioned on the insulating layer so as to define a conduction channel extending laterally adjacent the control terminal and communicating with the drift region and the emitter. The substrate and buried region are the same conductivity and opposite the doped region to form a bipolar transistor therebetween.

Abstract: Emitter-switched transistor structures are described which have only three terminals. A part of the drain current is used to provide the base current of an emitter-switched NPN transistor and to concurrently cause the injection of holes to conductivity-modulate the emitter-switching MOSFET of the NPN transistor. The reduced on-resistance of the emitter-switching MOSFET causes the emitter-switched NPN transistor to inject more electrons, which in turn leads to more hole injection via a positive feedback mechanism, resulting in a low on-state voltage drop for the device. In another embodiment of the invention, a thyristor structure is provided with the anode switched by a high-voltage MOSFET. Yet another embodiment of the invention provides a four terminal bidirectional device with no diffusions required on the backside of the wafer.

Abstract: A semiconductor device is provided which includes a first-conductivity-type collector layer having a rear surface on which a collector electrode is formed, a second-conductivity-type buffer layer laminated on the collector layer, a second-conductivity-type conductivity modulation layer formed on the buffer layer, a first-conductivity-type emitter layer formed as a well in a surface of the conductivity modulation layer, a second-conductivity-type source region formed in a surface of a well edge portion of the emitter layer, a gate electrode formed through a gate insulating film to overlap the source region and the conductivity modulation layer, and an emitter electrode that is in ohmic contact with both the emitter layer and the source region.

Abstract: A semiconductor device comprises a main switching element, an electric field detector and an on-voltage application unit. The main switching element includes a high-voltage main electrode, at least a low-voltage main electrode and at least a first gate electrode. The electric field detector has a MOS structure making conductive between the high-voltage main electrode and the first gate electrode in a path other than the main switching element in accordance with a predetermined electric field generated in the main switching element. The on-voltage application unit applies an on-voltage to the first gate electrode on the basis of the conductive state.

Abstract: A monolithic semiconductor component has a first thyristor having a gate, an anode and a cathode. The gate is connected to the cathode through a first resistor and to the anode through the series connection of a zener diode and a second thyristor. The thyristors are of the vertical type and the zener diode is of the lateral type. The cathode of the zener diode is connected to the cathode of the second thyristor through a metallization forming an output terminal.

Abstract: A MOS-gate switched power semiconductor component with a semiconductor body that has a number of unit cells arranged side-by-side and switched in parallel and consisting of a p-emitter zone adjacent to the anode, an adjoining, weakly doped n-base zone, then a p-base zone and an adjoining n-emitter zone. Incorporated in the n-emitter zone of the unit cells are pairs of p.sup.+ zones (5a, 5b) which, together with the n zone between them and an insulated gate situated above, form a lateral p-channel MOSFET (M1). The n-emitter zone (4) is equipped with a floating cathode contact (K') which at the same time constitutes the electrode of the p.sup.+ region serving as source. The p+ region serving as drain is connected to an external cathode (K), which has no contact with the n-emitter zone. Another MOSFET is formed by the surface region of the p-base zone (3) and the intervening region of the n-emitter zone (4b) together with an insulating gate.

Abstract: A reverse conducting gate-turnoff thyristor includes a switching device section, a diode section, and an isolating section located between the switching device section and the diode section. The isolating section includes an impurity layer formed by controlling impurity diffusion and having an impurity concentration lower than those of the switching device section and the diode section.

Abstract: A silicon carbide gate turn off thyristor (GTO) has a silicon carbide junction field effect transistor (JFET) connected between the gate of the GTO and one of its anode or cathode electrodes thereby minimizing cooling requirements while providing for rapid switching.

Abstract: An N-channel MOSFET is fabricated with its source, body and gate connected together and biased at a positive voltage with respect to its drain. The resulting two-terminal device functions generally in the manner of a diode but has a significantly lower turn-on voltage than a conventional PN diode. The device is therefore referred to as a "pseudo-Schottky diode". Pseudo-Schottky diodes have numerous uses, but they are particularly useful when connected to shunt current from a conventional PN diode or MOSFET and thereby prevent such conditions as snapback and latchup which can result from the storage of minority carriers in a forward-biased PN junction. Also, because the pseudo-Schottky diode is a majority carrier device, the diode recovery time, amount of stored charge, and peak reverse current are much lower than in a conventional PN diode.

Abstract: A self scanning light-emitting array is disclosed. A coupled array of light-emitting elements is constituted so that a light-emitting element in a minimal conducting state influences the next light-emitting element so that its threshold level is changed. When each element is driven by a common clock pulse, the change in threshold level is shifted in the longitudinal direction, so that a minimal conducting state is transferred in a clock period of the clock pulse.

Abstract: An integrated circuit chip with multiple switching element segments that cooperatively provide high power switching is provided with circuitry for isolating each individual switching element segment. The individual isolation of switching element segments enables bond wire continuity testing.

Abstract: In a composite controlled semiconductor device having an insulated gate, a p type semiconductor region forming no channel is provided between a plurality of p type semiconductor regions forming a channel and the potential of the p type semiconductor region in an ON state takes a value high enough to inject holes into an n type semiconductor region adjacent to the p type semiconductor region.

Abstract: An n-drift region, a p-base region, and an n-emitter region are formed in a semiconductor substrate. A trench is formed to be in contact with n-emitter region and p-base region, and a gate electrode is formed in trench with an insulated gate layer interposed. A first metal electrode layer electrically connected to n-emitter region, and a second metal electrode layer electrically connected to p-base region are provided. A direct current power source apparatus is connected to first and second metal electrode layers. Accordingly, on-state voltage can be reduced.

Abstract: An integrated circuit arrangement includes an IGBT, provided with a secondary contact connected with the drift area, and a diode connected between the secondary contact and the anode of the IGBT. The cathode of the diode is connected with the anode of the IGBT and the anode of the diode is connected with the secondary contact of the IGBT. In this way the pn-junction of the IGBT, formed through the drift area and the channel area, can be used as an internal free-running diode of the IGBT.

Abstract: A thyristor structure in which the DMOSFET connecting the N.sup.+ emitter to the N.sup.- drift region is eliminated and instead replaced with a DMOSFET connecting the N.sup.+ cathode to the N- drift region providing the base drive for the PNP transistor of the thyristor structure. The thyristor structure of the present invention provides lower on-state voltage drop as compared to prior art EST structures.

Abstract: A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.

Abstract: The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz->2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor.

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: A semiconductor device made of a lightly doped region of a first conductivity type has a well formed of a second conductivity type. The well extends to the surface of the device. First, second and third heavily doped regions of the first conductivity type are in the surface of the well. An electrode is fixed to the first heavily doped region of the first conductivity type. The third heavily doped region of the first conductivity type adjoins the lightly doped region of the first conductivity type. The first and second heavily doped regions of the first conductivity type are spaced apart from one another so that a portion of the well extends to the surface of the device therebetween. A first gate electrode is fixed via an insulating layer to a portion of the well extending between the first and second heavily doped regions. The first and third heavily doped regions of the first conductivity type are spaced apart from one another so that a portion of the well extends therebetween.

Abstract: A low-voltage trigger electrostatic discharge protection circuit with different layout structure, smaller chip area for better performance and space saving is connected, to the bonding pad of an IC to protect an internal circuit of an IC from electrostatic discharge damage using at least one NMOS transistor and at least two SCR connected in parallel between the bonding pad and a circuit ground point. When the electrostatic discharge stress is applied to the bonding pad, the NMOS will breakdown before breakdown of the gate oxide layer of the internal circuit to trigger the SCRs into snapback mode operation. Then the electrostatic discharge stress on the bonding pad is released by two SCRs (or more). Because the electrostatic discharge stress can be released by two SCRs at the same time, the invention can protect the SCRs from damage as well rather than the prior art using just one SCR and lead to better ESD performance. Furthermore, the chip area of the invention is about 150 .mu.m.sup.

Abstract: MOS-gate controlled thyristor structures which have current saturation characteristics, do not have any parasitic thyristor structure, and require only a single gate drive. A resistive structure such as a MOSFET, Schottky diode, PN junction diode, diffused resistor or punch-through device (e.g. punch through PNP structure) is incorporated in series with the N.sup.+ emitter of the thyristor. In the on-state of the device, with a positive gate voltage, when operating at high currents, because of the voltage drop in the resistive structure in series with the N.sup.+ emitter, the potential of the N.sup.+ emitter, and along with it the potential of the P base, increases. When the potential is increased beyond a certain predetermined value, diversion of current is accomplished by one of the following ways: (i) the smallest distance between the P base region and the P.sup.+ cathode is such that punch-through occurs in these regions.

Abstract: The invention concerns a field-effect controlled semiconductor component with at least four regions of alternating opposite performance types: an anode-side emitter region, a first and a second base region connected to the emitter region, and a cathode-side emitter region; the cathode-side emitter region and the first base region from the source and drain of an MOS field effect transistor. The component also comprises an anode contact, a contact at the cathode-side emitter region and a control electrode contact of the MOS field effect transistor. The invention lies in the fact that a p+ region (36) which is adjacent to the cathode-side base region, separate, and accomodated in the anode-side n- base region (20), is connected via a separate component as a coupling element (80) with non-linear current/voltage characteristics to the cathode contact, the said region (36) being directly surrounded by the anode-side base region (20).

Abstract: The present invention provides a semiconductor device comprising, at least a pair of an insulated gate bipolar transistor, and a diode, both of which are in a reverse parallel connection with each other, wherein the resistivity of the base layer of the lowest impurity concentration in the diode is lower than that of the base layer of the lowest impurity concentration in the insulated gate bipolar transistor, and wherein a breakdown voltage of said insulated gate bipolar transistor at the time of switching from conduction state to blocking state is lower than a breakdown voltage of said insulated gate bipolar transistor and said diode at the time of blocking state.

Abstract: A protection device against overloads that may occur on an interface between a telephone exchange and line switches connected to a subscriber's line, comprises a single protection circuit on the subscriber side of the line switches with respect to the interface. The overvoltage protection circuit ensures an overvoltage protection when the line switches are off, and an overcurrent protection when the switches are on. A controlled switch, disposed between each conductor and ground, is switched on in response to the detection of an overvoltage or overcurrent.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first terminal and a second terminal are formed in the active area adjacent to edges of the hexagon that are separated by another edge. First to third gates are formed between the first and second terminals, and have gate terminals formed outside the active area adjacent to other edges of the hexagon. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired AND, NAND, OR or NOR function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: Provided is a compounded power MOSFET which has a high positive and negative withstand voltages for the drain terminal relative to the source terminal, and can be formed on a single chip based on the conventional fabrication process of power MOSFETs. Power MOSFETs 10 and 11 have their drains connected together, the MOSFET 10 has its source and gate used for the source terminal 0 and gate terminal 1, respectively, of the compounded power MOSFET 60, and the MOSFET 11 has its source used for the drain terminal 2. The compounded power MOSFET includes a voltage comparator 50 which drives the MOSFET 11 to turn off when the terminal 2 has a negative voltage, and a voltage transmitter 51 which is connected between the terminal 1 and the gate of the MOSFET 11 to block a current flowing from the terminal 2 to the terminal 1 by way of the circuit 50 and transfer the voltage of the terminal 1 to the gate of the MOSFET 11.

Abstract: A controlled turn-off power semiconductor device is proposed which is subdivided into unit cells and which comprises five layers in a p-n-p-n-p sequence, namely a p-type emitter layer (9), an n-type base layer (8), a p-type base layer (7), an n-type emitter layer (6) and a p-doped contact region (5) between an anode (a) and a cathode (K). In every unit cell a first MOSFET (M1) which can be driven via a first insulated gate (G1) is provided on the cathode side for switching between the five-layer structure and a conventional thyristor four-layer structure. Further, a breakdown between the contact region (5) and the n-type emitter layer (6) is prevented during turning-off. As a result of the switchable five-layer structure, a current filamentation is effectively avoided during turning-off.

Abstract: A semiconductor device which reduces the turn-off time and the accompanying switching loss in a switching semiconductor device in which conductivity modulation is used to provide a low ON-state voltage. The conductivity modulation is provided by injection of minority carriers. A minority carrier injection-control structure is provided in part of a semiconductor device to change the polarity of a voltage applied to a gate electrode to start or stop the injection of minority carriers. During the ON-state, minority carriers are injected to obtain a low ON-state voltage, while during the OFF-state, the injection of minority carriers are stopped and a channel for majority carriers is formed to eliminate the accumulation of excess carriers and to accelerate discharge, thereby reducing the turn-off time and thus the switching loss.

Abstract: In a complex semiconductor device, an IGBT and a thyristor are formed in an identical semiconductor substrate to be connected in parallel with each other between main electrodes such that an end of the thyristor on the cathode side is connected to the main electrode via an insulated gate electrode of the IGBT. Thanks to the complex of the IGBT and the thyristor, there is attained a semiconductor device having a satisfactory ignition characteristic, a low on-state voltage, and a high breakdown voltage.

Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.

Abstract: A semiconductor device and a method for operating the same includes a first P-type semiconductor layer and a first N-type semiconductor layer provided thereon. A plurality of second P-type semiconductor layers and a plurality of third P-type semiconductor layers are formed on the surface of the first N-type semiconductor layer. A plurality of second N-type semiconductor layers are formed on their respective surfaces of the third P-type semiconductor layers. Emitter electrodes are provided on the second P-type semiconductor layers and second N-type semiconductor layers. A plurality of first gate electrodes is each provided above the first N-type semiconductor layer between the adjacent third P-type semiconductor layers. A plurality of second gate electrodes are each provided above the first N-type semi-conductor layer between the second P-type semiconductor layer and the third P-type semiconductor layer. A collector electrode is provided under the first P-type semiconductor layer.

Abstract: An insulating film having a through hole aligned with an electrode on a first semiconductor element is formed on a first semiconductor substrate and a metal is disposed in the through hole. A second semiconductor element on a second semiconductor substrate is placed on the insulating film in such a way that an electrode of the second semiconductor element contacts the metal. Thus, a plurality of transistors having different performance characteristics and functions can be easily disposed adjacent to each other for improved integration.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: A monolithic semiconductor power switching device and a method of separating plural thyristor based active areas therein includes reverse conducting diode regions between the active areas. The reverse conducting diode regions influence current flow at the edges of the operable ones of the active areas so that current from an operable one of the active areas does not flow into and turn on an inoperable one of the active areas. The reverse conducting diode regions have a width so that substantially all of the carriers of the current from an operable one of the active areas recombine before reaching an adjacent active area.

Abstract: A polysilicon gate resistor consists of a plurality of parallel polysilicon strips extending from gate finger to gate pad. Different numbers of parallel strips can be selected during manufacture by using different contact masks.

Abstract: To provide thermal relief, particularly of the edge of disk-shaped gate-turn-off GTO thyristors (GTO) as are used in converters in power electronics, at least one cooling segment which is isolated from a GTO cathode metallization of the GTO thyristor segment (GTO) by a gate electrode metallization of a gate electrode is arranged on the edge and laterally adjacent to the GTO thyristor segment (GTO). An insulation layer is provided between a cooling segment metallization and the gate electrode metallization. Cooling segments in an lo outer annular zone can be alternately arranged with GTO thyristor segments (GTO) or offset towards the outside in the radial direction or perpendicular direction thereto. Instead of cooling segments, a p.sup.+ -type GTO emitter layer of the GTO thyristor segments (GTO) can be shortened at the edge in the outer annular zone.

Abstract: High withstand voltage, low on-voltage, low turn-off loss, and high switching speed are realized in semiconductor bidirectional switches in which the potential of the substrate is floating. A switch has a p-type substrate without an electrode, and an n-layer on the substrate. At least one pair of p-well regions and at least one p-region are formed in a surface layer of the n-layer. An n.sup.+ region is formed in the p-well region, and a gate electrode is fixed via an insulation film to the p-well region. A main electrode is fixed to a part of the surface of the n.sup.+ region and the surface of a p.sup.+ contact region in the p-well region.

Abstract: This thyristor comprises a main current-carrying portion in the form of a semiconductor body having four layers, with contiguous layers being of different P and N conductivity types and with three back-to-back PN junctions between contiguous layers. One end layer constitutes an anode layer, an opposite end layer constitutes a cathode layer, and an intermediate layer contiguous with the cathode layer constitutes a gate layer. The cathode layer is divided into many elongated fingers, thereby dividing the PN junction between the cathode layer and the gate layer into many discrete PN subjunctions between the fingers and the gate layer. These subjunctions are effectively in parallel with each other so as to share the main current through the thyristor when the thyristor is "on". The gate layer has predetermined surface regions adjacent the cathode layer that are uncovered by the cathode-layer fingers and that respectively surround the PN subjunctions between the fingers and the gate layer.