Abstract: A method of triggering avalanche breakdown in a semiconductor device includes providing an electrical coupling and an optical coupling between an auxiliary semiconductor device configured to emit radiation and the semiconductor device including a pn junction between a first layer of a first conductivity type buried below a surface of a semiconductor body and a doped semiconductor region of a second conductivity type disposed between the surface and the first layer. The electrical and optical coupling includes triggering emission of radiation by the auxiliary semiconductor device and triggering avalanche breakdown in the semiconductor device by absorption of the radiation in the semiconductor device.

Abstract: An ESD protection device includes a Si substrate and a rewiring layer. The rewiring layer includes Ti/Cu/Ti electrodes are electrically connected through contact holes to an ESD protection circuit with Al electrodes films, which is formed at the surface of the Si substrate. The Al electrode film is electrically connected to the Ti/Cu/Ti electrode, whereas the Al electrode film is electrically connected to the Ti/Cu/Ti electrode. A diode forming region is formed between Al electrode films, whereas a diode forming region is formed between Al electrode films. The Ti/Cu/Ti electrode has no overlap with the diode forming region, whereas the Ti/Cu/Ti electrode has no overlap with the diode forming region. Thus, a semiconductor device is provided which is able to reduce the generation of parasitic capacitance, and able to be applied up to a higher frequency band.

Abstract: An ESD protection device and a method of forming the same, the ESD device includes a substrate, a first doped well, a second doped well, a source and drain regions and a guard ring. The first doped well with a first conductive type is disposed in the substrate. The source and drain regions with the second conductive type are disposed in the first doped well. The guard ring with the first conductive type is also disposed in the first doped well and has a first portion extending along a first direction and a second portion extending along a second direction different from the first direction. The second doped well with the second conductive type is also disposed in the first doped well between the drain region and the second portion of the guard ring to in contact with the drain region in the first direction.

Abstract: A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the adjacent metal lines. A second level is formed including at least one dielectric layer atop the first level. A plurality of trench structures is formed in the at least on dielectric layer. At least one of the plurality of trench structures opens the air gap. A conductive material is formed within the trenches. The conductive material deposited in the open air gap provides a vertical fuse.

Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a first doped region formed in the drain region. The source region and the drain region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The first doped region is electrically connected to a ground potential.

Abstract: Embodiments relate to a semiconductor device, including a channel area; a gate line extending along the channel area so that the channel area can be set into a conductive state by activating the gate line; a plurality of terminals including an electrical connection to the channel area, so that the plurality of terminals is connectable to a predetermined voltage by activating the gate line.

Abstract: An ESD protection device includes a zener diode, and a series circuit of diodes and a series circuit of diodes that are connected in parallel with the zener diode. At the connection point between the diodes, an Al electrode film is formed on the surface of a Si substrate, and at the connection point between diodes, an Al electrode film is formed on the surface of the Si substrate. The diodes are formed on the surface of the Si substrate, and the diodes are formed in the thickness direction of the Si substrate. The Si substrate has a longitudinal direction and a shorter direction orthogonal to the longitudinal direction in planar view, and the Al electrode films are formed respectively at both ends in the shorter direction of the Si substrate. Thus, provided is an ESD protection device which suppresses the ESL, and keeps the clamp voltage low.

Abstract: An ESD monitor device may take the form of an integrated circuit with a plurality of monitor components available at each I/O site of the ESD monitor device. Each monitor component has a physical structure which provides scalable ESD robustness. The monitor components are connected in parallel to an ESD bus. An integrated circuit may be formed by processing an ESD monitor device through one or more process steps of an integrated circuit manufacturing line, and subsequently measuring the ESD monitor device. Parameters of a process step of the manufacturing line may be adjusted to reduce ESD events at the process step, based on measurement results from the ESD monitor device. The integrated circuit may subsequently be processed through the adjusted process step.

Abstract: The present disclosure provides an array substrate, a display panel and a display device. The array substrate includes: a plurality of data lines and a plurality of gate lines configured to divide a display region into a plurality of display sub-regions; a pixel electrode arranged at each display sub-region; and a TFT arranged at each display sub-region, a source electrode of the TFT being electrically connected to the data line, a drain electrode thereof being electrically connected to the pixel electrode and a gate electrode thereof being electrically connected to the gate line, wherein a parasitic capacitor is formed between the gate electrode and the drain electrode of the TFT. The array substrate further includes a switch circuit configured to enable both ends of the parasitic capacitor to be electrically connected when a gate driving signal of the TFT is changed from a high level to a low level.

Abstract: An embodiment integrated circuit (e.g., diode) and method of making the same. The embodiment integrated circuit includes a well having a first doping type formed over a substrate having the first doping type, the well including a fin, a source formed over the well on a first side of the fin, the source having a second doping type, a drain formed over the well on a second side of the fin, the drain having the first doping type, and a gate oxide formed over the fin, the gate oxide laterally spaced apart from the source by a back off region of the fin. The integrated circuit is compatible with a FinFET fabrication process.

Abstract: Embodiments of the present disclosure provide a contact structure in a split-gate trench transistor device for electrically connecting the top electrode to the bottom electrode inside the trench. The transistor device comprises a semiconductor substrate and one or more trenches formed in the semiconductor substrate. The trenches are lined with insulating materials along the sidewalls inside the trenches. Each trench has a bottom electrode in lower portions of the trench and a top electrode in its upper portions. The bottom electrode and the top electrode are separated by an insulating material. A contact structure filled with conductive materials is formed in each trench in an area outside of an active region of the device to connect the top electrode and the bottom electrode. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: An ESD protection device 1 includes an insulating member 10, first and second discharge electrodes 21 and 22, a first outer electrode 31, a second outer electrode 32, and inner conductors 41 and 42. The first and second discharge electrodes 21 and 22 are provided in the insulating member 10. The first outer electrode 31 is provided on an outer surface of the insulating member 10. The first outer electrode 31 is electrically connected to the first discharge electrode 21. The second outer electrode 32 is provided on an outer surface of the insulating member 10. The second outer electrode 32 is electrically connected to the second discharge electrode 22. The inner conductors 41 and 42 are provided in the insulating member 10. The inner conductors 41 and 42 are connected to the first outer electrode 31 or the second outer electrode 32.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

Abstract: The present invention relates to an electronic device comprising a fingerprint sensing system including a plurality of sensing elements, each being configured to capacitively couple to a finger arranged adjacent to the sensing element and to provide a sensing signal indicative of a response to a time-varying finger excitation signal provided to the finger; and an electrically conducting housing at least partly enclosing an interior of the electronic device. The electronic device further comprises housing connection circuitry connected to the electrically conducting housing, and arranged and configured to at least intermittently allow a potential of the electrically conducting housing to follow the finger excitation signal. Hereby the housing can be used to enhance the functionality of the fingerprint sensing system.

Abstract: A semiconductor system for a current sensor in a power semiconductor includes: on a substrate, a multiple arrangement of transistor cells having an insulated gate electrode, whose emitter terminals are connected in a first region via a first conductive layer to at least one output terminal and whose emitter terminals are connected in a second region via a second conductive layer to at least one sensor terminal, which is situated outside of a first cell region boundary, which encloses the transistor cells of the first region and the second region, a trench structure belonging to the first cell region boundary being developed between the transistor cells of the second region and the sensor terminal.

Abstract: A method for manufacturing a transient voltage suppressing (TVS) array substantially following a manufacturing process for manufacturing a vertical semiconductor power device. The method includes a step of opening a plurality of isolation trenches in an epitaxial layer of a first conductivity type in a semiconductor substrate followed by applying a body mask for doping a body region having a second conductivity type between two of the isolation trenches. The method further includes a step of applying an source mask for implanting a plurality of doped regions of the first conductivity type constituting a plurality of diodes wherein the isolation trenches isolating and preventing parasitic PNP or NPN transistor due to a latch-up between the doped regions of different conductivity types.

Abstract: An embodiment integrated circuit includes a switch and a conductive line over the switch. The switch includes a gate, a first source/drain region at a top surface of a semiconductor substrate, and a second source/drain region at the top surface of the semiconductor substrate. The first source/drain region and the second source/drain region are disposed on opposing sides of the gate. At least a portion of the first conductive line is aligned with the gate, and the first conductive line is electrically coupled to ground.

Abstract: Circuits and methods of fabricating circuits that provide electrostatic discharge protection, as well as methods of protecting an integrated circuit from electrostatic discharge. The protection circuit may include a power clamp device, a timing circuit including a resistor and a capacitor that is coupled with the resistor at a node, and a power clamp device coupled with the timing circuit at the node. The capacitor includes a plurality of capacitor elements. The protection circuit further includes a plurality of electronic fuses. Each electronic fuse is coupled with a respective one of the capacitor elements. A field effect transistor may be coupled in parallel with the resistor of the timing circuit, and may be used to bypass the resistor to provide a programming current to any electronic fuse coupled with a capacitor element of abnormally low impedance.

Abstract: The present invention discloses an electrostatic discharge protection circuit, comprising a diode and a N-type metal-oxide-semiconductor (NMOS) transistor. The diode locating on a N-well comprises an high P-doping concentration region and an nonadjacent high N-doping concentration region. The NMOS transistor, locating on a P-well, comprises a drain, a source and a gate, and the drain and the source are formed by the high N-doping concentration region. Wherein the P-well further comprises a high P-doping concentration region near the source, the drain of the NMOS is electrically connected to the high N-doping concentration region of the diode, the source of the NMOS and the adjacent high P-doping concentration region are electrically connected to a ground, the gate of the NMOS transistor electrically connected to a trigger point.

Abstract: A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal.

Abstract: A protective diode is provided above a first guard ring region which surrounds an active region, with a field oxide film interposed there between. The protective diode may include a series pn zener diode in which a p+ layer and an n? layer are adjacent to each other. In a semiconductor device having the first guard ring region provided below the protective diode, cracks in the surface protective film may be prevented by providing a surface protective film that may be a polyimide film. The first guard ring region is provided below the protective diode and is connected to a second guard ring region that is provided in a portion other than the portion provided below the protective diode through a third guard ring region which is an intermediate region (R). Thus, when a surge voltage is applied, concentration of electric field on the outermost guard ring may be reduced.

Abstract: An ESD protection device is provided which experiences only small increases in discharge start voltage and discharge protection voltage and relatively free of scorching or peeling at the ends of the discharge electrodes thereof even if a discharge repeatedly occurs. The ESD protection device has an insulating substrate with a cavity, and in the cavity first and second discharge electrodes are so disposed that the ends thereof face each other with a gap therebetween. A first outer electrode is on the outer surface of the insulating substrate and electrically connected to the first discharge electrode, and a second outer electrode is on the outer surface of the insulating substrate and electrically connected to the second discharge electrode. The ends of the first and second discharge electrodes are thicker than any other portion of the first and second discharge electrodes.

Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.

Abstract: A semiconductor device includes a first electrode, a second electrode, a first semiconductor region that is formed between the first electrode and the second electrode and is in contact with the first electrode, a second semiconductor region that is formed between the first semiconductor region and the second electrode, a contact region that is formed between the second semiconductor region and the second electrode and is in contact with the second semiconductor region and the second electrode, a plurality of third semiconductor regions that are formed between the second electrode and the first semiconductor region and are in contact with the second electrode, and a wiring that is in contact with the second electrode, a portion of the wiring bonded to the second electrode being positioned above the third semiconductor region and not positioned above the contact region.

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract: Provided is an ESD protection device having excellent discharge characteristics at a low applied voltage. An ESD protection device includes a first discharge electrode and a second discharge electrode that are disposed so as to face each other, a discharge auxiliary electrode formed so as to span between the first discharge electrode and the second discharge electrode, and an insulator base that holds the first discharge electrode, the second discharge electrode, and the discharge auxiliary electrode. The discharge auxiliary electrode includes a plurality of metal particles (22) containing a first metal as a main component. Fine irregularities are formed on the surfaces of the metal particles (22). More specifically, the metal particles (22) has a fractal dimension D of 1.03 or more. Since electric charges are concentrated on the fine irregularities, discharge can be generated in the discharge auxiliary electrode by applying a relatively low voltage.

Abstract: Provided is an ESD protection device having high insulation reliability and good discharge characteristics. An ESD protection device includes a first discharge electrode and a second discharge electrode that are disposed so as to face each other, a discharge auxiliary electrode (18) formed so as to span between the first discharge electrode and the second discharge electrode, and an insulator base that holds the first discharge electrode, the second discharge electrode, and the discharge auxiliary electrode (18). The discharge auxiliary electrode (18) includes an aggregate of a plurality of metal particles (24) each having a core-shell structure including a core portion (22) that contains, as a main component, a first metal and a shell portion (23) that contains, as a main component, a metal oxide containing a second metal. A pore (26) is present in at least part of the shell portion (23).

Abstract: An electrostatic discharge (ESD) protection device is disclosed, which includes a substrate of a positive dopant type; a p-well defined in the substrate; a depletion inducing structure of a negative dopant type having a gap defined in a bottom portion thereof disposed in the p-well, and a n-channel device disposed in a planar encircled region defined by the depletion inducing structure. The well region is in connection with the substrate through the depletion inducing structure. Upon an ESD stress, the depletion inducing structure induces an expanded depletion region in the substrate under the well region, thus providing a substrate trigger mechanism that reduces the triggering voltage of the ESD protection device.

Abstract: A CMOS inverter is provided. The CMOS inverter includes a substrate. The CMOS inverter also includes an NMOS transistor having a first active region, a first isolation structure surrounding the first active region, a first connect structure, a plurality of the first metal interconnect structure and a first shunted gate structure to reduce a delay time and increase a saturation current. Further, the CMOS inverter includes a PMOS transistor having a second active region with a reduced area to reduce the delay time and increase the saturation current, a second isolation structure surrounding the second active region, a second connect structure, a plurality of metal interconnect structure and a second gate structure connecting with the first gate structure through the first connect structure and/or the second connect structure.

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

Abstract: Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.

Abstract: An ESD protection device includes an alumina multilayer substrate, a hollow portion, a discharge electrode pair, discharge-assisting electrodes, and a vitreous substance. The hollow portion is disposed inside of the alumina multilayer substrate. The electrodes of the discharge electrode pair are disposed opposite to each other at an interface between the hollow portion and the alumina multilayer substrate. The discharge-assisting electrodes are disposed dispersedly between the opposite electrodes of the discharge electrode pair. The vitreous substance covers the discharge-assisting electrodes in the inside of the hollow portion. A trial discharge is executed so as to induce creepage discharge between the electrodes of the discharge electrode pair in advance.

Abstract: Disclosed is a tunable capacitor which includes: a variable capacitor unit placed between a first terminal and a second terminal; and an ESD protection circuit which is inserted either between the first terminal and a ground terminal or between the second terminal and the ground terminal, or is inserted both between the first terminal and a ground terminal and between the second terminal and the ground terminal.

Abstract: In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

Abstract: A device comprises a high voltage N well and a high voltage P well over an N+ buried layer, a high voltage P-type implanted region in the high voltage N well, a first N+ region over the high voltage P-type implanted region and a P+ region and a second N+ region over the high voltage P well.

Abstract: An electrostatic discharge protection device may include a first conductivity type well, a second conductivity well; a first doping region and a second doping region which are formed in the first conductivity type well and have different conductivity types from each other; a third doping region and a fourth doping region which are formed in the second conductivity type well and have different conductivity types from each other; and a fifth doping region formed in the second conductivity type well between the first and second doping regions and the third and fourth doping regions.

Abstract: An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions.

Abstract: An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side, and a bump connected with the through silicon via.

Abstract: A semiconductor device includes an SCR ESD device region disposed within a semiconductor body, and a plurality of first device regions of the first conductivity type disposed on a second device region of the second conductivity type, where the second conductivity type is opposite the first conductivity type. Also included is a plurality of third device regions having a sub-region of the first conductivity type and a sub-region of the second conductivity type disposed on the second device region. The first regions and second regions are distributed such that the third regions are not directly adjacent to each other. A fourth device region of the first conductivity type adjacent to the second device region and a fifth device region of the second conductivity type disposed within the fourth device region are also included.

Abstract: A semiconductor integrated circuit device includes a TSV (Through Silicon Via) extending through a substrate, a first well in the substrate adjacent a first surface of the substrate, a gate of an active device on the first well, a charging protection well, and a charging protection gate on the charging protection well. The charging protection well is disposed in the substrate adjacent the first surface of the substrate, is interposed between the TSV hole and the first well, and surrounds the TSV hole. The charging protection gate prevents the gate of the active device from being damaged when the TSV is formed especially when using a plasma etch process to form a TSV hole in the substrate.

Abstract: An electrostatic discharge protection device has a substrate, a P-well, a N-well, and an isolation portion. The P-well and N-well formed in the substrate are neighboring to each other. Along a specific direction, the P-well has a first N-type, a first P-type, a second N-type, a second P-type, and a third N-type high doping regions sequentially located thereon, and the N-well has a third P-type, a fourth N-type, a fourth P-type, a fifth N-type, and a fifth P-type high doping regions sequentially located thereon. The first N-type, the third N-type, the first P-type, and the second P-type high doping regions are coupled to a ground end, the third P-type, the fifth P-type, the fourth N-type, and the fifth N-type high doping regions are coupled to a voltage supply end, and the second N-type and the fourth P type high doping regions are coupled to an input/output end.

Abstract: A semiconductor device includes a plurality of cells in a main region, a plurality of cells in a sensing region, a transistor, and a gate shut-off time for the sensing region. The transistor is configured to drive each of the plurality of cells in the main region and each of the plurality of cells in the sensing region. The gate shut-off time for the sensing region is set according to D=(Cgs/Cgm)*(Rgs/Rgm) to be earlier than a gate shut-off time for the main region. D indicates a CR delay ratio, Rgm indicates a gate resistance value for the main region and Rgs indicates a gate resistance value for the sensing region in the transistor, and Cgm indicates a parasitic capacitance for the main region and Cgs indicates a parasitic capacitance for the sensing region in the transistor.

Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. In an example method, a thyristor is triggered to conduct current from a signal node to a reference voltage node using leakage currents provided by a transistor formed in a semiconductor doped well shared with the base of the thyristor. The leakage currents are responsive to a noise event (e.g., electrostatic discharge (ESD) event) at the signal node, and increase the voltage of the semiconductor doped well to forward bias the base and the collector of the thyristor. The triggered thyristor conducts the current resulting from the ESD event to the reference voltage node.