Abstract: The present invention disclosed herein is a Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) device incorporating a reverse diode. This device includes a plurality of source regions isolated from a drain region. A source region in close proximity to the drain region is a first diffusion structure in which a heavily doped diffusion layer of a second conductivity type is formed in a body region of a second conductivity type. Another source region is a second diffusion structure in which a heavily doped diffusion layer of a first conductivity type and a heavily doped diffusion layer of the second conductivity type are formed in the body region of the second conductivity type. An impurity diffusion structure of the source region in close proximity to the drain region is changed to be operated as a diode, thereby forming a strong current path to ESD (Electro-Static Discharge) or EOS (Electrical Over Stress). As a result, it is possible to prevent the device from being broken down.

Abstract: A semiconductor integrated circuit device according to the present invention includes a diode in a second island region. The anode region of the diode and the dividing region in a first island region having a horizontal PNP transistor are electrically connected to each other; the cathode region of the diode and the collector region of a power NPN transistor are electrically connected to each other. Accordingly, the dividing region in the first island region having a horizontal PNP transistor becomes lower in potential than the dividing regions in the other island regions, so that the inflow of free carriers (electrons) to the horizontal PNP transistor can be prevented.

Abstract: Methods and apparatuses to selectively deposit a dielectric on a self-assembled monolayer (“SAM”) adsorbed metal are described. A wafer includes a device having a first electrode. A first self-assembled monolayer is deposited on the wafer covering the first electrode. Next, a portion of the first self-assembled monolayer is removed to expose the first electrode. The first self-assembled monolayer includes a hydrophobic layer. Further, second self-assembled monolayer is deposited on the first electrode. The second self-assembled monolayer includes a hydrophilic layer. Next, an insulating layer is deposited on the second self-assembled monolayer. Further, self-aligned contacts to one or more second electrodes of the device are formed.

Abstract: A method for forming a film pattern by disposing a functional liquid in a pattern forming region partitioned by a bank includes: disposing a first bank forming material to a substrate so as to form a first bank layer; and forming a second bank layer on the first bank layer, wherein the first bank forming material is an organic material while the second bank layer is made of a fluorine resin material covering the first bank layer.

Abstract: In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS.

Abstract: A triac including on its front surface side an autonomous starting well of the first conductivity type containing a region of the second conductivity type arranged to divide it, in top view, into a first and a second well portion, the first portion being connected to a control terminal and the second portion being connected with said region to the main front surface terminal.

Abstract: A thyristor and a method for manufacturing the thyristor that includes providing a semiconductor substrate that has first and second major surfaces. A first doped region is formed in the semiconductor substrate, wherein the first doped extends from the first major surface into the semiconductor substrate. The first doped region has a vertical boundary that has a notched portion. A second doped region is formed in first doped region, wherein the second doped region extends from the first major surface into the first doped region. A third doped region is formed in the semiconductor substrate, wherein the third doped region extends from the second major surface into the semiconductor substrate.

Abstract: A semiconductor device that permits an increase in static destruction resistance while preventing an increase in the chip size includes a protective element formed by a polysilicon layer in which JFETs are serially connected in three stages and which is inserted between a gate electrode and source electrode of a power-MOSFET or IGBT semiconductor device. The gate insulation film of a semiconductor active element portion of the semiconductor device is protected regardless of whether the polarity of static electricity or another high voltage is positive or negative.

Abstract: A current-jump-control circuit including an abrupt metal-insulator phase transition device is proposed, and includes a source, the abrupt metal-insulator phase transition device and a resistive element. The abrupt metal-insulator phase transition device includes first and second electrodes connected to the source, and shows an abrupt metal-insulator phase transition characteristic of a current jump when an electric field is applied between the first electrode and the second electrode. The resistive element is connected between the source and the abrupt metal-insulator phase transition device to control a jump current flowing through the abrupt metal-insulator phase transition device. According to the above current control circuit, the abrupt metal-insulator phase transition device can be prevented from being failed due to a large amount of current and thus the current-jump-control circuit can be applied in various application fields.

Abstract: Switching operations, such as those used in memory devices, are enhanced using a thyristor-based semiconductor device adapted to switch between a blocking state and a conducting state. According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a thyristor having first and second base regions coupled between first and second emitter regions, respectively. A first control port capacitively couples a first signal to the first base region, and a second control port capacitively couples a second signal to the second base region. Each of the first and second signals have a charge that is opposite in polarity, and the opposite polarity signals effect the switching of the thyristor at a lower power, relative to the power that would be required to switch the thyristor having only one control port.

Abstract: A semiconductor component is arranged in a semiconductor body and has at least one integrated radially symmetrical lateral resistance having a location-dependent sheet resistance, the radial dependence of which is preferably configured such that the differential resistance dR is radially constant or the power dissipated in the resistance is radially constant.

Abstract: A thyristor-based semiconductor device includes a filled trench separating and electrically insulating adjacent thyristor control ports. According to an example embodiment of the present invention, the filled trench is formed in a substrate adjacent to at least one thyristor body region. The filled trench includes a conductive filler material, an insulative material formed on the conductive filler material and at least two laterally-adjacent thyristor control ports separated from one another by the conductive filler material and the insulative material. One of the control ports is adapted for capacitively coupling to the thyristor body region for controlling current in the thyristor. With this approach, two or more control ports can be formed in a single filled trench and electrically isolated by the conductive filler material/insulative material combination.

Abstract: The invention concerns a bidirectional electronic switch of the pulse-controlled bistable type comprising a monolithic semiconductor circuit including a vertical bidirectional switch structure (TR; ACS) provided with a gate terminal (G1), first (Th1) and second (Th2) thyristor structures whereof the anodes are formed on the front face side, the first thyristor anode region containing a supplementary P-type region (6), and a metallization (A1, A2) connected to the main surface of the front face of the vertical bidirectional component and to the second thyristor anode; a capacitor (C) connected to the first thyristor anode and to the second thyristor supplementary N-type region; and a switch (SW) for short-circuiting the capacitor.

Abstract: A the present invention provides an electrostatic discharge protection element to be used in a semiconductor integrated circuit providing MOSFET, comprising a thyristor and a trigger diode for triggering the thyristor into an ON-state, wherein the trigger diode provides an n-type cathode high concentration impurity region, a p-type anode high concentration impurity region and a gate formed between the two high concentration impurity regions, the gate being composed of the same material as that of a gate of MOSFET forming the semiconductor integrated circuit, and the thyristor provided with a p-type high concentration impurity region that forms a cathode and an n-type high concentration impurity region that forms an anode, and the p-type high concentration impurity region provides in a p well and connected to a resistor and/or the n-type high concentration impurity region provided in an n well and connected to a resistor.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

Abstract: A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.

Abstract: An ESD protection circuit has a VDD bus, a VSS bus, an IC pad, a PMOS transistor coupled to the IC pad and the VDD bus, and an NMOS transistor coupled to the IC pad and the VSS bus. The pitch of the PMOS can smaller than the pitch of the NMOS, and the drain-contact-to-gate-spacing (DCGS) for the PMOS can be smaller than the DCGS for the NMOS.

Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.

Abstract: An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

Abstract: The present invention is directed to a novel semiconductor device, which can be efficiently fabricated for use in Zener diode applications. Precision Zener diodes and the method for manufacturing the same are provided. The Zener diodes of the present invention are made from a semiconductor substrate layer having a range or resistivity, on which is grown an epitaxial layer. The epitaxial layer has a resistivity greater than that of the substrate. The diode also has an interior region of doped semiconductor material of the same conductivity type as the substrate. The interior region extends through the epitaxial layer and into the substrate layer. The diode also has a junction layer of a conductivity type different from the substrate. The junction layer is formed in the epitaxial surface, and the junction layer forms an interior P/N junction with the interior region and a peripheral P/N junction with a peripheral portion of the device.

Abstract: A semiconductor device having a thyristor is manufactured and arranged in a manner that reduces or eliminates difficulties commonly experienced in the formation and implementation of such devices. According to an example embodiment of the present invention, a thyristor (e.g., a thin capacitively-coupled thyristor) is formed having some or all of the body of the thyristor formed inlayed in a semiconductor device substrate. A trench is provided in the substrate, and a semiconductor material is formed in the trench. One or more layers of material are formed in the trench and used to form a portion of a body of the thyristor. The thyristor is formed having adjacent regions of different polarity, wherein at least one of the adjacent regions includes a portion of the semiconductor material and at least one of the adjacent regions includes a portion of the substrate.

Abstract: The present invention provides a PMSCR (bridging modified lateral modified silicon controlled rectifier having first conductivity type) with a guard ring controlled circuit. The present invention utilizes controlled circuit such as switch to control functionally of guard ring of PMSCR. In normal operation, the switch is of low impedance such that the guard ring is short to anode and collects electrons to enhance the power-zapping immunity. Furthermore, during the ESD (electrostatic discharge) event, the switch is of high impedance such that the guard ring is non-functional. Thus, the PMSCR with guard ring control circuit can enhance both the ESD performance and the power-zapping immunity in the application of the HV (high voltage) pad.

Abstract: A protective circuit for protecting an IGBT from a stress due to application of an overvoltage which is induced by a surge such as static electricity is provided. The protective circuit allows for improvement in a voltage tolerance to a stress due to application of an overvoltage induced by a surge while ensuring a current tolerance to flow of a direct current from an external power supply when the external power supply is improperly connected in a direction contrary to a normal direction. The protective circuit includes a resistor having one end connected to a terminal for connecting to the external power supply and the other end connected to a semiconductor element, and a first zener diode including a cathode connected to the other end of the resistor. The protective circuit further includes a plurality of second zener diodes connected in series between the one end of the resistor and a generator of a constant potential such as a ground.

Abstract: A gate driver includes a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch and a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay.

Abstract: Electrostatic discharge protection device comprising a first highly p-doped region with a base contact, a first highly n-doped region with a collector contact, a second highly n-doped region with an emitter contact and located between the first highly p-doped region and the second highly n-doped region, the first highly p-doped region and the second highly n-doped region being applied in a weakly p-doped region which a has a lateral overlap extending towards the first highly n-doped region, the lateral overlap having a width, the first highly n-doped region being applied in a weakly n-doped region, the weakly p-doped region and the weakly n-doped region being applied in a more weakly n-doped region, and a highly n-doped buried layer located underneath the more weakly n-doped region and extending below at least a portion of the weakly n-doped region and at least a portion of the weakly p-doped region.

Abstract: An electronic device (10) comprises an array of pixels (12), arranged in rows and columns (14,16) with row and column address lines (18,20) for addressing each pixel (12). Each row and column address line is connected to two discharge lines (30,32) through a discharge circuit (38). The circuit allows the passage of charge between the address line and the first discharge line (30) when the address line is at a potential below that of the first discharge line, and allows the passage of charge between the address line and the second discharge line (32) when the address line is at a potential above that of the second discharge line. This provides electrostatic discharge protection against an increase or decrease in voltage on the row or column address lines during manufacture of the device. By providing suitable voltages on the two discharge lines during operation of the manufactured device, it is possible to prevent the discharge circuit from operating, thereby saving power.

Abstract: The present invention reveals an electrostatic discharge protection apparatus including a silicon controlled rectifier, a triggering voltage adapter network and a holding voltage adapter network. Additionally, the triggering voltage adapter network and the holding voltage adapter network are coupled to the silicon controlled rectifier. The present invention can change the characteristic of current vs. voltage by adjusting the triggering voltage and the holding voltage of the silicon controlled rectifier to meet the special requirement of various chips, and effectively prevent the chips from being damaged caused by the electrostatic discharging.

Abstract: A precision low-power crystalline semiconductor device is disclosed that has a crystalline structure. The semiconductor device has a semiconductor substrate layer of, for example N-type conductivity. The device also has a first region of doped semiconductor material that is also, for example, N-conductivity type. Further, the device has a second region of a doped semiconductor material having a conductivity that is, for example, P-type conductivity. Consistent with the present invention, the second region forms a P/N junction with the first region. Additionally, a noise-reducing minority carrier controlling substance is provided within the crystalline structure of the semiconductor device, and the substance imparts an operational parameter of a low-noise breakdown voltage at reverse currents below a threshold current.

Abstract: The present invention reveals an electrostatic discharge protection apparatus including a silicon controlled rectifier, a triggering voltage adapter network and a holding voltage adapter network. Additionally, the triggering voltage adapter network and the holding voltage adapter network are coupled to the silicon controlled rectifier. The present invention can change the characteristic of current vs. voltage by adjusting the triggering voltage and the holding voltage of the silicon controlled rectifier to meet the special requirement of various chips, and effectively prevent the chips from being damaged caused by the electrostatic discharging.

Abstract: A semiconductor chip provided, at a lateral face thereof, with an electrode for external electric connection. Where a semiconductor chip has a plurality of electrodes, all the electrodes are preferably formed at one or more lateral faces of the semiconductor chip. Each electrode is preferably embedded in a groove which is formed in a lateral face of the semiconductor chip and which is opened laterally of the semiconductor chip. The semiconductor chip may be a discrete bipolar transistor element. In this case, each of the base electrode, the emitter electrode and the collector electrode is preferably formed at a lateral face of the semiconductor chip.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: A monolithic bidirectional switch formed in a semiconductor substrate of type N, including a first main vertical thyristor, the rear surface layer of which is of type P, a second main vertical thyristor, the rear surface layer of which is of type N, an auxiliary vertical thyristor, the rear surface layer of which is of type P and is common with that of the first main thyristor, a peripheral region of type P especially connecting the rear surface layer of the auxiliary thyristor to the layer of this thyristor located on the other side of the substrate, a first metallization on the rear surface side, a second metallization on the front surface side connecting the front surface layers of the first and second thyristors. An additional region has a function of isolating the rear surface of the auxiliary thyristor and the first metallization.

Abstract: An embedded SCR in conjunction with a Gated-NMOS is created for protecting a chip input or output pad from ESD, by inserting a p+ diffusion and the n-well in the drain side and a part of the drain to forms a low-trigger, high efficiency SCR. The device layout is such that the drain connection is tightly tied together at the p+ diffusion and the n+ drain making that connection very short and, thereby, preventing latch-up. The parasitic SCR is contained entirely within the n+ diffusion (the source of the grounded gate NMOS transistor) at either side of the structure and, therefore, called an embedded SCR. For a 12 volt I/O device each of two n+ drains is placed in its own n-type doped drain (ndd) area straddling halfway the n-well. The structure is repeated as required and a p+ diffusion is implanted at both perimeters and connected to the nearest n+ source and a reference voltage.

Abstract: Described is a MOS gate-controlled SCR (UGSCR) structure with a U-shaped gate (UMOS) for an ESD protection circuit in an IC device which is compatible with shallow trench isolation (STI) and self-aligned silicide (salicide) fabrication technology. The UMOS gate is located in a p-substrate and is surrounded by an n-well on either side. Adjacent to one side of the UMOS gate, a first n+ diffusion is formed which straddles the first n-well. The n+ diffusion together with a p+ pickup diffused next to it form the cathode of the SCR (thyristor). Adjacent to the other side of the UMOS gate, a second n+ and p+ diffusion are formed in a second n-well. The second n+ and p+ diffusion together with the UMOS gate form the anode of the SCR and the input terminal of the circuit to be protected. The SCR is formed by the first n+ diffusion/n-well (cathode), the p-substrate, the second n-well and the second p+/n+ diffusion (anode).

Abstract: Providing a semiconductor device for use in a ignition circuit, which prevents an increase in clamp voltage and allows application of a constant voltage across an ignition plug. In a semiconductor device which comprises a transistor and a zener diode connected between a collector and a gate of the transistor, a glass coat layer coating the zener diode is made of silicon oxide.

Abstract: A protection circuit in a semiconductor integrated circuit having a master slice I/O circuit comprises an internal circuit, a pad, and a desired number of protection elements connected in parallel between the internal circuit and the pad. Each protection element includes a P-channel MOS transistor which outputs a first power supply voltage level signal on the basis of an output signal of the internal circuit, a N-channel MOS transistor which outputs a second power supply voltage level signal on the basis of the output signal of the internal circuit, a resistor connected between a signal line connected to the pad and an output terminal of the P-channel MOS transistor, and a resistor connected between the signal line and an output terminal of the N-channel MOS transistor.

Abstract: A semiconductor rectifier includes a substrate of a first conductivity type; a current path layer of the first conductivity type formed near the surface of the substrate; a current block layer of a second conductivity type laterally enclosing the current path layer and extending to a depth deeper than the current path layer; and first and second metal layers formed respectively contacting upper and lower surfaces of the substrate. The current path layer has an impurity concentration higher than that of the substrate, and the current block layer has an impurity concentration higher than that of the current path layer. The current path layer is small enough for the portion below the current path layer to be completely blocked by the depletion region formed around the current block layer when a reverse bias or no is applied to the rectifier.

Abstract: Providing a semiconductor device for use in an ignition circuit, which prevents an increase in clamp voltage and allows application of a constant voltage across an ignition plug. In a semiconductor device which comprises a transistor and a zener diode connected between a collector and a gate of the transistor, a glass coat layer coating the zener diode is made of silicon oxide.

Abstract: An N-MOSFET is formed on an SOI substrate consisting of a semiconductor substrate, an insulating layer and an n−-active layer. A p-well layer, an n-RESURF layer, and an n-diffusion layer are formed in the surface of the n−-active layer between a source electrode and a drain electrode by means of impurity diffusion. The diffusion regions of the p-well layer and the n-RESURF layer overlap with each other. An end of the n-RESURF layer reaches a position below a gate electrode. The diffusion regions of the p-well layer and the n-diffusion layer do not overlap with each other, so that the n-RESURF layer has a region in direct contact with the n−-active layer between the p-well layer and the n-diffusion layer.

Abstract: A semiconductor overcurrent limiter having input and output terminals includes a depletion type vertical MOSFET, a depletion type lateral MOSFET, and a zener diode. A back gate of the lateral MOSFET is formed in common with a drain electrode of the vertical MOSFET to provide the input terminal, and a gate of the vertical MOSFET is connected to an anode of the zener diode to provide the output terminal. Further, a source electrode of the vertical MOSFET is connected to source and gate electrodes of the lateral MOSFET and a cathode electrode of the zener diode.

Abstract: On a semiconductor integrated circuit chip, multiple equipotential power-line conductors are provided to supply power to circuit elements. First protecting elements are provided for interconnecting the power-line conductors for protecting the circuit elements. A number of input/output pads are also connected to the power-line conductors via second protecting elements. The arrangement is such that the contact positions of any of the first protecting elements and any of the second protecting elements on the power-line conductors are nearer to respective end portions of the conductors than the contact position of any of the circuit elements on the conductors. Each of the contact positions serves as a dividing point for dividing a high potential electrostatic charge into at least two low potential charges.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: A protection device for trench isolated technologies. The protection device includes a lateral SCR (100) that incorporates a triggering MOS transistor (120) with a first gate electrode (116) connected to the cathode (112) of the SCR (100). The anode (110) of the lateral SCR (100) is separated from the nearest source/drain region (122) of the triggering MOS transistor (120) by a second gate electrode (132) rather than by trench isolation. By using the second gate electrode (132) for isolation instead of trench isolation, the surface conduction of the lateral SCR (100) in unimpeded.

Abstract: Given too great a dU/dt load of a thyristor, this can trigger in uncontrolled fashion in the region of the cathode surface. Since the plasma only propagates poorly there and the current density consequently reaches critical values very quickly, there is the risk of destruction of the thyristor due to local overheating. The proposed thyristor has a centrally placed BOD structure and a plurality of auxiliary thyristors (1.-5. AG) annularly surrounding the BOD structure. The resistance of the cathode-side base (8) is locally increased under the emitter region (11) allocated to the innermost auxiliary thyristor (1. AG). Since the width (L) and the sheet resistivity of this annular zone (15) critically influences the dU/dt loadability of the first auxiliary thyristor (1.

Abstract: In a bidirectional photothyristor formed on a single N type silicon substrate, a distance between a P-gate diffusion region of one thyristor and an anode diffusion region of another thyristor opposed thereto is set to be 40 to 1,000 .mu.m, preferably, 70 to 600 .mu.m, thereby eliminating a malfunction caused by a noise due to a differentiation circuit which is composed of parasitic resistors and junction capacitances. In a field portion between the P-gate diffusion region and the anode diffusion region, an oxygen-doped semi-insulating film is formed via an SiO.sub.2 film, and an Al conductor is removed to form a field light receiving portion. Unlike a P-gate light receiving portion formed in the P-gate diffusion region, the field light receiving portion does not involve a junction capacitance. Therefore, a light sensitivity can be enhanced without lowering a dV/dt resistance.

Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.

Abstract: Disclosed is a floating gate neuron MOS transistor that may be incorporated into devices such as low voltage silicon control rectifiers for protection of internal circuits against electrostatic discharge. The transistor includes two or more input gates capacitively coupled to the floating gate. By adjusting the coupling ratio of the input gates, it is possible to control the transistor drain turn-on voltage very precisely and thereby turn on the rectifier without relying on avalanche breakdown of the transistor.

Abstract: A monolithic component for protection against over-currents liable to occur on a line in series with which is connected a detection resistor, comprises a first cathode-gate thyristor associated with an avalanche diode and a second anode-gate thyristor of the gate triggering type or forward breakover type, its breakover voltage being substantially equal to the avalanche voltage of the avalanche diode.

Abstract: The invention provides a silicon controlled rectifier having an anode and a cathode and including an NPN transistor and a PNP transistor. The NPN transistor has an emitter coupled to the cathode, a base and a collector. The PNP transistor has a base coupled to the NPN collector, an emitter coupled to the anode, a first collector coupled to the NPN base and a second collector coupled to the NPN collector.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.