Abstract: A protection semiconductor component includes at least two pairs of main Shockley diodes, each pair including two parallel diodes, head-to-tail connected between a front surface metallization and a rear surface metallization, the rear surface metallization being common to the two pairs of diodes. Each of the main diodes whose blocking junction corresponds to a distinct well on the side of the front surface is associated with at least one auxiliary Shockley diode having the same polarity and a lower triggering threshold, the triggering of one auxiliary diode thus causing the triggering of the other auxiliary diode and of the associated main Shockley diodes.

Abstract: An SCR circuit formed on a semiconductor substrate includes a well region, a first diffusion region and a second diffusion region in the well region, and a third diffusion region in the substrate. The SCR circuit also includes a capacitor connected between the first diffusion region and the third diffusion region. The junction region between the well region and the diffusion region is forward biased when an electrostatic force is applied to the SCR circuit, thereby triggering the SCR circuit to discharge the electrostatic force.

Abstract: A dV/dt clamp circuit is connected to a base of a phototransistor for triggering a control electrode of a thyristor, thereby making an attempt to prevent an operation error. A control electrode voltage of the thyristor is applied to the gate of the MOSFET via a high breakdown voltage capacitor. The gate electrode voltage of the MOSFET can be continuously held at a threshold value or more by adjusting a zener voltage of a zener diode and a resistance value of a resistor. Since with a high dV/dt the MOSFET can be operated at a high speed to allow conduction between the drain and source of the MOSFET, the phototransistor does not trigger the thyristor, thereby preventing an operation error.

Abstract: A semiconductor substrate is partitioned into a main IGBT region and a protection circuit region by a p-type well portion which is formed therebetween in contact with an emitter electrode and which acts as a cut-off region. Both a detection IGBT and protection circuit elements are formed within the protection circuit region. Since excessive carriers flowing from the main IGBT into the protection circuit region can efficiently be extracted through the p-type well portion, a highly reliable and high precision protection circuit built-in insulated gate semiconductor device is realized that can precisely detect any overcurrent, and operate without causing malfunction in the protection circuit and time delay.

Abstract: A protection device against overloads that may occur on an interface between a telephone exchange and line switches connected to a subscriber's line, comprises a single protection circuit on the subscriber side of the line switches with respect to the interface. The overvoltage protection circuit ensures an overvoltage protection when the line switches are off, and an overcurrent protection when the switches are on. A controlled switch, disposed between each conductor and ground, is switched on in response to the detection of an overvoltage or overcurrent.

Abstract: When an abrupt voltage noise is applied across an anode electrode (A) and a cathode electrode (K), displacement currents (I.sub.10 to I.sub.30) which are responsive to junction capacitances (C.sub.10 to C.sub.30) of respective unit thyristors (ST.sub.1, ST.sub.2, MT) are generated. The displacement currents (I.sub.10 to I.sub.30) flow into a compensation electrode (C) through paths in a P base layer (2) having resistances (R.sub.10 to R.sub.30), and further flow to an external power source through the cathode electrode (K) which is short-circuited with the compensation electrode (C). The paths of the three displacement currents (I.sub.10 to I.sub.30) are separated from each other by resistances (R.sub.12, R.sub.23). Therefore, a forward bias voltage of a junction (D.sub.10) caused by the displacement current (I.sub.10) is attenuated by the displacement current (I.sub.20), while a forward bias voltage of a junction (D.sub.20) caused by the displacement current (I.sub.

Abstract: An electrostatic discharge (ESD) circuit for protecting a semiconductor integrated circuit (IC) device is disclosed. One ESD circuit is located between each I/O buffering pad that connects to one lead pin and the internal circuitry of IC. The ESD circuit is connected to both power terminals. The ESD circuit comprises first and second low-voltage-trigger SCRs (LVTSCRs), each having an anode, a cathode, an anode gate and a cathode gate. The anode and anode gate of the first SCR are connected to a first power terminal, the cathode of the first SCR is connected to its I/O buffering pad, and the cathode gate of the first SCR is connected to the second power terminal. The ESD circuit further comprises a PMOS transistor having drain, source, gate, and bulk terminals. The PMOS transistor's gate, source and bulk terminals are connected to the first power terminal, the PMOS transistor drain terminal is connected to the cathode gate of the first SCR.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: An object of the present invention is to provide a semiconductor device which is designed so as to increase a maximum controllable current and decrease hold current without degrading its characteristic and to provide a method of manufacturing such a semiconductor device. A transistor formation region 3 and a P diffusion region 15 are selectively formed through an insulating film 4 between gate electrodes 5 on an N.sup.- epitaxial layer 2. In a transistor formation region 3, an N.sup.+ diffusion region 12 is formed on a P diffusion region 11, a P diffusion region 13 is formed on the N.sup.+ diffusion region 12, and an N.sup.+ diffusion region 14 is selectively formed on a surface of the P diffusion region 13. Then, a cathode electrode 7 is formed on the P diffusion region 13, N.sup.+ diffusion region 14 and P diffusion region 15, and an anode electrode 8 is formed on a second major surface of the P.sup.+ substrate 1.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with, but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: The sensitivity of breakdown voltage to temperature and dV/dT induced currents is reduced in semiconductor power devices having a wide base transistor. The sensitivity is reduced by diverting current from the emitter of the wide base transistor to the base of the wide base transistor (an emitter short that does not reduce breakdown voltage) or by injecting a current into the base of the wide base transistor to its collector (an injected current that may lower the breakdown voltage, but no more than that related to temperature and capacitive current). The invention finds application in both epitaxial grown and substrate based devices.

Abstract: A non-planar MOS-controlled thyristor (MCT) which improved turn-off capabilities. The unique non-planar geometry brings the MOS channel region closer to the active thyristor junction, thereby reducing an "effective" resistance which inhibits turn-off of prior art devices 10. This effective resistance is a combination of the resistance through the MOS and the parasitic resistance between the MOS and active thyristor junction. For efficient thyristor turn-off at high current, the effective resistance should be about 0.6 v or less. Both the recessed gate 30 and the MCT with built-up cathode 60 have effective resistances of about 0.6 v or less.

Abstract: A semiconductor component for limiting transient voltages on the signal or other supply lines of a system, includes, in a common semiconductor body, a plurality of multi-junction diodes connected in the same sense between a common terminal and respective input means which are for connection to the respective supply lines of the system, and a respective further diode connected in shunt with each multi-junction diode with the opposite sense to the multi-junction diode.

Abstract: A thyristor comprised of a vertical thyristor including, on its front surface, a localized anode region, and on its rear surface, a cathode metallization substantially coating the whole rear surface region, and, on its front surface region, a lateral thyristor. The thyristor gate corresponds to the cathode region or to the cathode-gate region of the lateral thyristor. The cathode-gate region or cathode region, respectively, of the lateral thyristor is connected to the cathode of the vertical thyristor.

Abstract: A MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped P-type region. The transistor comprises an N-type drain region, an N-type source region, and a region contacting the for region. The drain, cource and contacting regions are formed at the surface of the first region. The source and contacting regions are interconnected. An N-type highly doped region extends from the drain region through the first low-doped P-type region to the second more highly doped P-type region.

Abstract: The hold current of a breakover type surge protection device is increased by irradiating the device with .gamma. or x rays so as to form crystal lattice defects in the semiconductor regions thereof.

Abstract: An integrated protective structure provides protection from electrostatic discharges of structures to an integrated circuit functionally connected to a certain external pin. The protective structure is formed in a single epitaxial tub and includes a triggering Zener diode and a vertical bipolar transistor. The collector region of the vertical bipolar transistor is connected to the pin and constitutes also one of the two terminal regions of the triggering Zener. Around the emitter region and separated therefrom by the smallest distance feasible, is an annular region, having a heavier doping than the base region of the transistor formed with the purpose of intercepting the avalanche current of the Zener junction and distributing it in a uniform manner into the base region of the vertical transistor as well as acting as a shield for eventual electrons moving from the emitter region toward the breakdown junction.

Abstract: An N.sup.+ buffer layer (2) and an N.sup.- layer (3) are provided on a P.sup.+ silicon substrate (1) in this order. On an upper portion of the N.sup.- layer (3), a P.sup.- layer (4b) is selectively formed, and on the P.sup.- layer (4b), a P.sup.+ layer (4a) is provided. On part of an top surface of the P.sup.+ layer (4a), a plurality of N.sup.+ layers (5a) are provided, and a trench (13) is formed extending through each of the N.sup.+ layers (5a) and P.sup.+ layer (4a) downwards to the P.sup.- layer (4b). In the P.sup.- layer (4b), an N.sup.+ floating layer (5b) is provided covering the bottom face of each trench (13). In the inner hollow of the trench (13), a gate electrode (8a) is provided through a gate oxidation film (7a), while an emitter electrode (9a) is provided extending between the top surfaces of the adjacent N.sup.+ layers (5a) with the surface of the P.sup.+ layer (4a) interposed so as to electrically short circuit them. A collector electrode (10) is provided on a lower major surface of the P.

Abstract: Locking devices are made by using a floating gate cell which is put into a state of being never programmable electrically by placing a voltage limiter between its drain zone and the ground and between its source zone and the ground. The cell can no longer ever be programmed by ultra-violet rays because of the interposition of a metal pad above its control gate. A voltage limiter is made by using a Zener diode made by the joining, to the drain and source zones, of a zone with opposite doping, placed outside the channel zone and connected to the ground.

Abstract: A conductivity modulation type MISFET, and a control circuit thereof are provided. A semiconductor device 1 comprises a conductivity modulation type MOSFET 1a and a built-in MOSFET 1b which is designed to control a source electrode 12a and a control electrode 13 of a parasitic transistor to be in a short state or an open state, said conductivity modulation type MOSFET 1a having a polysilicon gate 6 on an obverse surface of n.sup.- -type conductivity modulation layer 4, a p-type channel diffusion area 7, n.sup.+ -type source diffusion area 8 and a parasitic transistor control electrode 13 conductively connected to the p-type channel diffusion area 7 through a p.sup.+ -type contact area 9.

Abstract: A semiconductor device includes a thyristor (4,5,8,9) in which connection is made to the cathode region (9) of the thyristor by means of an MOS structure. The MOS structure is provided by a fifth region (11) forming a pn junction with the cathode region (9), a sixth region (13) in contact with the cathode electrode (C) and forming a pn junction (14) with the fifth region (11), and an insulated gate (15) overlying a conduction channel area (110) of the fifth region (11) for defining a gateable conductive path for charge carriers into the cathode region (9) to initiate thyristor action. The conductive path is thus controlled by the voltage applied to the insulated gate (15), enabling the flow of charge carriers to the cathode region (9) to be stemmed by application of an appropriate gate voltage oxide. The fifth region (11) is electrically connected to provide a path for extraction of charge carriers during turn-off of the thyristor, thereby improving the controllable current capability of the thyristor.