Abstract: The present invention provides an oxide semiconductor electrode which can realize a combination of high transparency with large surface area and is highly responsive to ultraviolet light, as well as to visible light. The oxide semiconductor electrode comprises a conductive substrate and an oxide semiconductor layer provided on the conductive substrate. The oxide semiconductor layer is a porous layer comprising porous titania particles which have been joined to each other to define interparticulate communicating pores. Preferably, the pores possessed by the titania particles per se have a diameter of 10 to 40 nm, the interparticulate communicating pores have a diameter of 10 to 70 nm, and the titania particles have an average diameter of 10 to 70 nm.

Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.

Abstract: The present invention relates to power semiconductor devices and particularly to a power semiconductor device which contains a plurality of power semiconductor elements, and an object of the invention is to provide a power semiconductor device which is capable of reducing differences in impedance caused by differences in length among wire interconnections, facilitating the electric connection between the main circuit terminals and the outside, and lightening restrictions on the number and layout of the power semiconductor elements installed.

Abstract: A turn-off high power semiconductor device with the inner pnpn-layer structure of a Gate-Commutated Thyristor and a first gate on the cathode side has an additional second gate on the anode side, said second gate contacting the n-doped base layer and having a second gate contact. A second gate lead which is of rotationally symmetrical design and is disposed concentrically with respect to the anode contact is in contact with said second gate contact. Said second gate lead is brought out of the component and electrically insulated from the anode contact.

Abstract: A semiconductor device including a substrate, a mesa post overlying the substrate and having a substantially cylindrical shape, a resin member surrounding the mesa post and a stress moderating member received in the mesa post for moderating stress between the mesa post and the resin member. The stress applied to the mesa post is reduced because the entire volume of the resin member is divided by the stress moderating member and each of the divided resin members reduces the stress.

Abstract: A stackable ball grid array (BGA) or fine ball grid array (FBGA) semiconductor package particularly suitable for board-on-chip or chip-on-board applications in which a low-profile BGA or FBGA semiconductor package is needed. The stackable ball grid array (BGA) or fine ball grid array (FBGA) provides a semiconductor package that is capable of being burned-in and tested in a more efficient and cost-effective manner than prior known BGA or FBGA semiconductor packages. A high-density, low-profile memory module incorporating a plurality of the disclosed BGA or FBGA semiconductor packages in a stacked arrangement is further disclosed.

Abstract: In accordance with a press contact type semiconductor device, a metallic body having macroscopic vacancies inside is arranged between a main electrode of the semiconductor device and a main electrode plate, or between an intermediate electrode plate arranged on a respective main plane of the semiconductor element and a main electrode plate.

Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.

Abstract: A multilayer board free from breakage at connecting parts due to thermal fatigue is provided. A multilayer board 1 of the present invention comprises alternating polyimide films 11-16 and copper films 21-26. The polyimide films 11-16 have a thermal expansion coefficient of 2-5 ppm/° C. so that the multilayer board 1 has a total thermal expansion coefficient of less than 10 ppm/° C. Because of the thermal expansion coefficient close to that of the semiconductor element to be mounted, no breakage occurs at connecting parts to the semiconductor element. The multilayer board 1 of the present invention may be used as both interposer and motherboard.

Abstract: An electro-optical device such as a liquid crystal device comprises a transparent substrate and a plurality of thin film transistors for driving pixel electrodes. In order to prevent an undesirable influence of light incident on the thin film transistors, a light shielding layer is interposed between the thin film transistors and the transparent substrate. Another portion of the light-shielding layer which corresponds to the pixel electrodes, has been changed to transparent by selectively oxidizing or nitriding the layer.

Abstract: An apparatus comprising a volume of memory material and a pair of spacedly disposed conductors. An electrode coupled to the volume of memory material and disposed between the volume of memory material and one conductor. The electrode comprises a first portion having a first thermal coefficient of resistivity and a second portion having a different second thermal coefficient of resistivity. A method including modifying the thermal coefficient of resisting of a portion of an electrode.

Abstract: A connecting device for power semiconductor modules with compensation for mechanical stresses includes a sleeve connected to a substrate and having a region with a given very small diameter. A wire pin is provided for insertion into the region of the sleeve during operation to form an electrical connection for a board. The wire pin has a diameter greater than the given diameter for clamping the wire pin upon insertion in the region. Axial freedom of movement of the wire pin in the sleeve makes it possible to avoid mechanical stresses resulting from different material characteristics when a temperature change takes place.

Abstract: High power semiconductor module device constituted in such a manner that a circuit board to which semiconductor pellets are bonded is bonded onto a heat sink, and an electrically insulating case with elasticity which has a tubular portion surrounding the sides of the circuit board is mounted on the heat sink, wherein there is provided a push member which is composed of an electrically insulating material and pushes the respective pellet wholly or partially from above with a predetermined pressure. By thus pushing the pellet by means of the push member, the destruction of the module device due to the thermal fatigue of the bonded portions of the circuit board and the pellets, the bonded portion of the circuit board and heat sink, and the bonded portions of the bonding wires is prevented even when the temperature of the whole module is repeatedly raised and lowered by the repetition of heating and cooling during the operation of the pellets.

Abstract: A pressure assembled power module is provided with first and second die, the first and second die being stacked atop one another and sandwiched between first and second conductive sheets, where the die are separated by a relatively flat central conductive lead. Integral to the central conductive lead are spring elements which bias the die against both the conductive sheets and the central conductive lead. Consequently, electrical and thermal interconnections are achieved between semiconductor devices and between the semiconductor devices and a heat sink or substrate.

Abstract: A semiconductor device is provided which includes a plurality of semiconductor chips each of which has a first main electrode and a control electrode on a first main surface and a second main electrode on a second main surface, and a plurality of support plates each of which is secured to the second main surface of the corresponding semiconductor chip. These semiconductor chips and support plates constitute individual semiconductor elements. The semiconductor elements are accommodated in the flat package that includes first and second common electrode plates and an insulating sleeve interposed between the common electrode plates, such that the semiconductor chip and the support plates are positioned by positioning guides. The first common electrode plate is in contact under pressure with the support plates.

Abstract: In the present invention, by virtue of heat buffer plates respectively located on the major surfaces of IGBT chips and FRD chips arranged in a single plane, the total thickness of each chip and a corresponding one of the heat can be set to a substantially predetermined value. A thickness-correcting member having elongated projections corresponding to the chips is provided on those surfaces of the heat buffer plates which is remote from the chips. A heat buffer disk plate is provided on those surfaces of the chips which are opposite to the major surfaces thereof. The thickness-correcting member, the heat buffer plates and the IGBT and FRD chips are held and simultaneously pressed between an emitter press-contact electrode plate and a collector press-contact electrode plate.

Abstract: In a pressure contact housing for semiconductor components, the gate electrode contact ring 4 is provided with spiral recesses 5. The latter can absorb axial movements produced during the assembly of the housing, without loading the material. A good and durable electrical contact between the gate electrode and the gate electrode contact ring is obtained thereby.

Abstract: In a semiconductor device comprising a semiconductor chip on which semiconductor elements are formed, the semiconductor device further comprises a thermal resistance detector for detecting an increase of thermal resistance of a heat radiating path which is provided to radiate the heat generated in the semiconductor device during operation, and a thermal resistance detection result output circuit for outputting a result of a detection by the thermal resistance detector to an output of the semiconductor device. The semiconductor device can detect at the early stage the increase of the thermal resistance of the heat radiating path, and the deterioration of the semiconductor device due to the crack in the solder layer bonding the chip mounting insulation substrate and heat sink during the operation of the device.

Abstract: An alloy-free pressure contact type semiconductor device maintains a high reliability during transportation even without a pressure contact tool such as a simplified stack and therefore does not require a high transportation cost. Through holes (H1) and (H2) each having a circular cross section are formed in distortion buffer plates (21A) and (21K) at the center. A first and a second bottomed holes (i.e., recesses) (N1) and (N2) are formed in an anode electrode plate (41A) and a cathode electrode plate (41K). From the through hole (H1) up to the first bottomed hole (N1), a pressure contact pin (9) biased by a coil spring (8) is disposed. From the through hole (H2) down to the second bottomed hole (N2), a fixing pin (90) is disposed. Without applying external pressure upon the device, it is possible to prevent displacement of the first and the second distortion buffer plates due to vibration or impact during transportation and damage to a semiconductor body.

Abstract: An insulated gate type semiconductor device has a gate electrode which controls current flow between two regions of the same conductivity type in a semiconductor substrate. A main electrode has a first portion contacting a first one of the two regions, a second portion extending above the gate electrode and a third portion providing a raised external contact surface to contact an external electrode. The gate electrode is insulated above and below by insulating films. To prevent damage to the gate electrode and the lower insulating films due to the pressure of the external electrode, there is a supporting insulating layer on the surface of the substrate underlying the contact portion of the main electrode and having a thickness substantially greater than the thickness of the insulating film below the gate electrode and the contact surface is more remote from the substrate than the second portion of said main electrode.

Abstract: A plurality of segments of small-sized IGBT devices are arranged concentrically in a plurality of rows in a pellet substrate. Each segment has an independent polysilicon gate electrode layer. A gate electrode terminal lead-out portion is provided at a central portion of the pellet substrate. A metal gate electrode layer electrically connects the polysilicon gate electrode layer of at least one of the segments of a unit, which unit is constituted by at least one of the segments arranged radially from the central portion of the pellet substrate towards a peripheral portion of the pellet substrate, to the gate electrode terminal lead-out portion. The metal gate electrode layer includes a trunk wiring portion extending radially from the gate electrode terminal lead-out portion, and a branch wiring portion extending from the trunk wiring portion in a circumferential direction of the pellet substrate and electrically connected to the polysilicon gate electrode layer of each segment.

Abstract: An optically-triggered silicon controlled rectifier (SCR) device (21) mounted on a lead frame (34). The SCR device contains a cathode layer (24), an optical gate or control layer (23), and an anode layer (31) formed on a semiconductor substrate (22). The device is soldered onto a pedestal (33) formed on the lead frame. To connect the device to the lead frame, solder is deposited upon the anode layer and the solder fixes the anode layer to the pedestal on the lead frame. The pedestal may be formed by etching or stamping a depression (35) in the lead frame. The device is centered on the pedestal such that the edges of the device are located adjacent the depression, and are spaced from the lead frame.

Abstract: A method of forming an insulated gate semiconductor device (10). A field effect transistor and a bipolar transistor are formed in a portion of a monocrystalline semiconductor substrate (11) that is bounded by a first major surface (12). A control electrode (19) is isolated from the first major surface by a dielectric layer (18). A first current conducting electrode (23) contacts a portion of the first major surface (12). A second current conducting electrode (24) contacts another portion of the monocrystalline semiconductor substrate (11) and is capable of injecting minority carriers into the monocrystalline semiconductor substrate (11). In one embodiment, the second current conducting electrode contacts a second major surface (13) of the monocrystalline semiconductor substrate (11).

Abstract: A MOS semiconductor device which exhibits high switching operations including high turn-on and an excellent self-cooling capability. The device prevents damage to insulation films and electrodes thereof. An IGT includes a multi-layer structure having a p type emitter layer, an n type base layer, a p type base layer and an n type emitter layer superimposed therein. A gate electrode and an overlying gate oxide film are disposed on a recessed surface of the multi-layer structure. A cathode electrode is located only in and around a cathode surface so that most of the top surface of the gate electrode is uncovered. Via an intervening cathode distortion snubbering plate, the cathode electrode is in pressure contact with a cathode electrode body. The gate and the cathode electrodes have a reduced capacitance therebetween. The cathode electrode body serves to cool the cathode electrode. The gate electrode and the gate oxide film are protected from stress, and hence, will not be damaged by stress.