Staircase (including Graded Composition) Device Patents (Class 257/185)
  • Patent number: 10797193
    Abstract: According to some implementations, an avalanche photodiode may include a photon absorbing layer to absorb photons of an optical beam and to provide a response. The avalanche photodiode may include a gain response layer to provide a gain to the response. The avalanche photodiode may include a bias control structure connected to the gain response layer to control an electric field in the photon absorbing layer and the gain response layer.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Lumentum Operations LLC
    Inventors: Alireza Samani, David Plant, Michael Ayliffe
  • Patent number: 10720455
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 10680138
    Abstract: A light-emitting device comprises a semiconductor stack comprising a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first pad on the semiconductor stack; a second pad on the semiconductor stack, wherein the first pad and the second pad are separated from each other with a distance, which define a region between the first pad and the second pad on the semiconductor stack; and multiple vias penetrating the active layer to expose the first semiconductor layer, wherein the first pad and the second pad are formed on regions other than the multiple vias.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 9, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Bo-Jiun Hu, Tsung-Hsun Chiang, Wen-Hung Chuang, Kuan-Yi Lee, Yu-Ling Lin, Chien-Fu Shen, Tsun-Kai Ko
  • Patent number: 10600931
    Abstract: An avalanche photodiode includes: a first contact layer; a light absorbing layer located on the first contact layer and having a multi-quantum well structure; a first electric field control layer located on the light absorbing layer; and a carrier multiplication layer located on the first electric field control layer. At least one of the multi-quantum well structure includes a well layer that includes Ga1-xAlxN (0?X?0.3), and a barrier layer that includes Ga1-xAlxN (0.7?X?1) and a doping portion doped with a p-type dopant.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 24, 2020
    Assignee: WOORIRO CO., LTD.
    Inventors: Chan Yong Park, Seoung Hwan Park
  • Patent number: 10177231
    Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Hung Chen, Shih-Hsien Huang, Yu-Ru Yang, Huai-Tzu Chiang, Hao-Ming Lee, Sheng-Hao Lin, Cheng-Tzung Tsai, Chun-Yuan Wu
  • Patent number: 10141356
    Abstract: An image sensor may include an array of image sensor pixels. Each pixel may have a photodiode, a floating diffusion node, and a charge transferring transistor. The charge transferring transistor may be a dual gate transistor having first and second gate terminals. A suitable bias may be applied to the second gate terminal to alter the capacitance of the floating diffusion node. The amount of electrons that may be accommodated by the floating diffusion node may be altered with application of a varying voltage level bias at the second gate terminal. By implementing a dual gate transistor, dynamic range compression and anti-blooming charge overflow may be implemented directly in the pixel to reduce image sensor pixel size and cost.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 27, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 10074778
    Abstract: Disclosed herein are a light emitting diode package and a method of manufacturing the same. The light emitting diode package includes: a substrate, a light-emitting layer disposed on a surface of the substrate and including a first type semiconductor layer, an active layer, and a second type semiconductor layer, a first bump disposed on the first type semiconductor layer and a second bump disposed the second type semiconductor layer, a protective layer covering at least the light-emitting layer, and a first bump pad and a second bump pad disposed on the protective layer and connected to the first bump and the second bump, respectively.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: September 11, 2018
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chi Hyun In, Jun Yong Park, Kyu Ho Lee, Dae Woong Suh, Jong Hyeon Chae, Chang Hoon Kim, Sung Hyun Lee
  • Patent number: 9865686
    Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 9, 2018
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Huilong Zhu, Xiaolong Ma
  • Patent number: 9859425
    Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more ART trenches, and recessing the first semiconductor material down into the ART trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9704883
    Abstract: A fin structure on a substrate can have a lower portion formed from the substrate, a middle portion, and an upper portion. The middle portion can include a dielectric region having a dielectric composition and a concentrated region of a first material. The first material can be an element of the dielectric composition. The concentrated region can be located at an interface of the middle portion and lower portion. The structure can also include isolation regions in the substrate on opposing sides of the fin. The structure can also include a gate structure over the upper portion of the fin that are exposed from the isolation regions. The gate structure can include a gate dielectric and gate material over the gate dielectric. The structure can also include source/drain regions extending laterally from the upper portion and the middle portion of the fin.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Chi-Wen Liu, Kuo-Cheng Ching, Jhon Jhy Liaw, Wai-Yi Lien
  • Patent number: 9647155
    Abstract: The disclosure provides a photo-detection device for use in long-wave infrared detection and a method of fabrication. The device comprises a GaSb substrate, a photo absorbing layer comprising InAs/InAsSb superlattice type-II, a barrier layer comprising AlAsSb, and a contact layer comprising InAs/InAsSb superlattice type-II. The barrier layer is configured to allow minority carrier holes current flow while blocking majority carrier electrons current flow between the photo-absorbing and contact layers. The disclosure further provides a method of producing the photo-detector using photolithography which includes selective etching of the contact layer that stops on the top of the barrier so no etching is made to the barrier layer so the barrier may operate as a passivator too. The disclosure presents an x-ray and photoluminescence results for InAs/InAsSb superlattice type-II material.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 9, 2017
    Inventor: Shimon Maimon
  • Patent number: 9640421
    Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 2, 2017
    Assignee: ARTILUX, INC.
    Inventors: Szu-Lin Cheng, Shu-Lu Chen
  • Patent number: 9634154
    Abstract: In some embodiments, a semiconductor device includes a first well region configured to be an anode of the semiconductor device, a first doped region configured to be a cathode of the semiconductor device, a second doped region configured to be another cathode of the semiconductor device, and a conductive region. The first well region is disposed between the first doped region and the second doped region, and is configured for electrical connection of the conductive region.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hui-Ting Lu, Yu-Chang Jong, Pei-Lun Wang
  • Patent number: 9406717
    Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Stephen W. Bedell, Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9391225
    Abstract: Avalanche photodiodes (APDs) and single photon avalanche detectors (SPADs) are provided with a lateral multiplication region that provides improved amplification through increased impact ionization.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: July 12, 2016
    Assignee: Sandia Corporation
    Inventors: Paul Davids, Douglas Chandler Trotter, Christopher DeRose
  • Patent number: 9379243
    Abstract: In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more ART trenches, and recessing the first semiconductor material down into the ART trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: June 28, 2016
    Assignee: Intermational Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9257577
    Abstract: A light receiving element includes a substrate of a first conduction type, a light absorbing layer of the first conduction type formed on the substrate, a diffusion layer of a second conduction type formed on a portion of the light absorbing layer, a window layer of the first conduction type formed on the light absorbing layer so as to surround the diffusion layer and having a bandgap larger than that of the light absorbing layer, an anode electrode formed on the diffusion layer, and a cathode electrode provided on the substrate so as to contact the substrate without contacting each of the window layer and the light absorbing layer, wherein a groove is formed which surrounds a boundary between the diffusion layer and the window layer as viewed in plan and extends through the window layer and the light absorbing layer as viewed in section.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: February 9, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Matobu Kikuchi, Masaharu Nakaji, Ryota Takemura, Kazuki Yamaji
  • Patent number: 9202870
    Abstract: A semiconductor device includes first conductive layers and first interlayer insulating layers stacked alternately with each other, at least one second conductive layer and at least one second interlayer insulating layer formed on the first conductive layers and the first interlayer insulating layers and stacked alternately with each other, a first semiconductor layer passing through the first conductive layers and the first interlayer insulating layers and including polysilicon, and a second semiconductor layer coupled to the first semiconductor layer and passing through the at least one second conductive layer the at least one second interlayer insulating layer, wherein the second semiconductor layer includes silicon germanium.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 1, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Jin Ho Bin
  • Patent number: 9117727
    Abstract: Example embodiments disclose transistors, methods of manufacturing the same, and electronic devices including transistors. An active layer of a transistor may include a plurality of material layers (oxide layers) with different energy band gaps. The active layer may include a channel layer and a photo sensing layer. The photo sensing layer may have a single-layered or multi-layered structure. When the photo sensing layer has a multi-layered structure, the photo sensing layer may include a first material layer and a second material layer that are sequentially stacked on a surface of the channel layer. The first layer and the second layer may be alternately stacked one or more times.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: I-hun Song, Yin Huaxiang, Sang-hun Jeon, Sung-ho Park
  • Publication number: 20150028386
    Abstract: Various embodiments of a germanium-on-silicon (Ge—Si) photodiode are provided along with the fabrication method thereof. In one aspect, a Ge—Si photodiode includes a doped bottom region at the bottom of a germanium layer, formed by thermal diffusion of donors implanted into a silicon layer. The Ge—Si photodiode further includes a doped sidewall region of Ge mesa formed by ion implantation. Thus, the electric field is distributed in the intrinsic region of the Ge—Si photodiode where there is low dislocation density. The doped bottom region and sidewall region of the Ge layer prevent electric field from penetrating into the Ge—Si interface and Ge mesa sidewall region, where a large amount of dislocations are distributed. This design significantly suppresses dark current.
    Type: Application
    Filed: July 23, 2014
    Publication date: January 29, 2015
    Inventors: Tuo Shi, Liangbo Wang, Pengfei Cai, Ching-yin Hong, Mengyuan Huang, Wang Chen, Su Li, Dong Pan
  • Publication number: 20140312370
    Abstract: An optoelectronic device comprising a first semiconductor layer having a first lattice constant; a second semiconductor layer having a second lattice constant, wherein the second lattice constant is smaller than the first lattice constant; and a first buffer layer formed between the first semiconductor layer and the second semiconductor layer, wherein a lattice constant of one side of the first buffer layer near the second semiconductor layer is smaller than the second lattice constant.
    Type: Application
    Filed: April 21, 2014
    Publication date: October 23, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: Shiuan-Leh LIN, Shih-Chang LEE
  • Patent number: 8835906
    Abstract: A sensor includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat, where the photothermal absorber outputs an electric signal in response to incident light to be introduced into the photothermal absorber or heat to be applied to the photothermal absorber. A semiconductor wafer includes: a base wafer containing silicon; a seed member provided directly or indirectly on the base wafer; and a photothermal absorber that is made of a Group 3-5 compound semiconductor lattice-matching or pseudo lattice-matching the seed member and being capable of generating a carrier upon absorbing light or heat.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 16, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiko Hata, Tomoyuki Takada, Sadanori Yamanaka, Taro Itatani
  • Patent number: 8816461
    Abstract: A dichromatic photodiode and method for dichromatic photodetection are disclosed. A wide bandgap junction comprises a lattice matched junction operable to detect a first light spectrum. A narrow bandgap junction is coupled to the wide bandgap junction, and comprises a photodiode structure. The narrow bandgap junction is operable to detect a second light spectrum.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: August 26, 2014
    Assignee: The Boeing Company
    Inventors: Ping Yuan, Xiaogang Bai, Rengarajan Sudharsanan
  • Publication number: 20140197454
    Abstract: TA photo detection device, including a substrate, a band-pass filter layer formed over the substrate, a light absorption layer formed over the band-pass filter layer, a Schottky layer formed on a portion of the light absorption layer, a first electrode layer formed on a portion of the Schottky layer, and a second electrode layer formed on the light absorption layer and spaced apart from the Schottky layer.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Applicant: Seoul Viosys Co., Ltd.
    Inventors: Ki Yon PARK, Chang Suk HAN, Hwa Mok KIM, Hyo Shik CHOI, Daewoong SUH
  • Patent number: 8628989
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8525229
    Abstract: A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0?y?1, 0?z?1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: September 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Yuji Ando, Takashi Inoue, Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 8507787
    Abstract: A solar cell includes a base layer; an emitter layer disposed on one side of the base layer; a first electrode in electrical communication with the base layer; and a second electrode in electrical communication with the emitter layer, wherein the base layer has a higher doping concentration with increasing distance from the interface between the base layer and the emitter layer, and the base layer has a doping concentration change slope that is further decreased with increasing distance from the interface between the base layer and the emitter layer.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung Gyun Suh
  • Patent number: 8399910
    Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: March 19, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jeffrey W. Scott, Colin E. Jones, Ernie J. Caine, Charles A. Cockrum
  • Patent number: 8378384
    Abstract: A wafer includes a wafer frontside surface and a region adjacent to the wafer frontside surface. The region includes oxygen precipitates and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: February 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Hans-Joerg Timme, Helmut Strack
  • Patent number: 8362520
    Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: January 29, 2013
    Assignee: Lockheed Martin Corporation
    Inventors: Jeffrey W. Scott, Colin E. Jones, Ernie J. Caine, Charles A. Cockrum
  • Patent number: 8354693
    Abstract: A solid state imaging device includes a pixel having a photoelectric conversion element formed on a semiconductor substrate. The photoelectric conversion element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer and forming a junction therebetween; a third semiconductor layer formed on the second semiconductor layer and having a smaller band gap energy than the second semiconductor layer, the third semiconductor layer being made of a single-crystal semiconductor and containing an impurity; and a fourth semiconductor layer of the first conductivity type covering a side surface and an upper surface of the third semiconductor layer. Provision of the fourth semiconductor layer can reduce a current flowing in dark conditions.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: January 15, 2013
    Assignee: Panasonic Corporation
    Inventors: Mitsuyoshi Mori, Toru Okino, Daisuke Ueda, Toshinobu Matsuno
  • Patent number: 8344359
    Abstract: A semiconductor structure having a transistor and a thermo electronic structure. The transistor has a control electrode for controlling a flow of carriers through a semiconductor layer between a pair of electrodes. The thermo electronic structure has a first portion disposed on at least one of the pair of electrodes and a second portion disposed over a region of the semiconductor layer proximate the control electrode between the control electrode and said at least one of the pair of electrode. The thermo electronic structure extends from the first portion to the second portion for removing heat generated heat from said region in the semiconductor layer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: January 1, 2013
    Assignee: Raytheon Company
    Inventors: John P. Bettencourt, Nicholas J. Kolias
  • Patent number: 8330192
    Abstract: In broad terms the present invention is a semiconductor junction comprising a first material (102) and a second material (104), in which a surface of one or both of the junction materials has a periodically repeating structure that causes electron wave interference resulting in a change in the way electron energy levels within the junction are distributed.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: December 11, 2012
    Assignee: Borealis Technical Limited
    Inventors: Avto Tavkhelidze, Amiran Bibilashvili, Rodney T. Cox
  • Patent number: 8227291
    Abstract: A method of manufacturing a stacked-layered thin film solar cell with a light-absorbing layer having a band gradient is provided. The stacked-layered thin film solar cell includes a substrate, a back electrode layer, a light-absorbing layer, a buffer layer, a window layer, and a top electrode layer stacked up sequentially. The light-absorbing layer has a band gradient structure and is essentially a group I-III-VI compound, wherein the group III elements at least include indium (In) and aluminum (Al). Moreover, the Al/In ratio in the upper half portion of the light-absorbing layer is greater than that in the lower half portion of the light-absorbing layer, wherein the upper half portion is proximate to a light incident surface.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: July 24, 2012
    Assignee: Nexpower Technology Corp.
    Inventor: Feng-Chien Hsieh
  • Patent number: 8212285
    Abstract: The invention specifies a radiation detector for detecting radiation (8) according to a predefined spectral sensitivity distribution (9) that exhibits a maximum at a predefined wavelength ?0, comprising a semiconductor body (1) with an active region (5) serving to generate a detector signal and intended to receive radiation, in which according to one embodiment the active region (5) includes a plurality of functional layers (4a, 4b, 4c, 4d) that have different band gaps and/or thicknesses and are implemented such that they (4a, 4b, 4c, 4d) at least partially absorb radiation in a range of wavelengths greater than ?0. According to a further embodiment, disposed after the active region is a filter layer structure (70) comprising at least one filter layer (7, 7a, 7b, 7c), said filter layer structure determining the short-wave side (101) of the detector sensitivity (10) according to the predefined spectral sensitivity distribution (9) by absorbing wavelengths smaller than ?0.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 3, 2012
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Arndt Jaeger, Peter Stauβ, Reiner Windisch
  • Patent number: 8163651
    Abstract: The invention discloses a method of fabricating a first substrate and a method of recycling a second substrate during fabrication of the first substrate. The second substrate is heterogeneous for the first substrate. First, the fabricating method according to the invention is to prepare the second substrate. Subsequently, the fabricating method is to deposit a buffer layer on the second substrate. Then, the fabricating method is to deposit a semiconductor material layer on the buffer layer. The buffer layer assists the epitaxial growth of the semiconductor material layer, and serves as a lift-off layer. Finally, with an etching solution, the fabricating method is to only etch the lift-off layer to debond the second substrate away from the semiconductor material layer, where the semiconductor material layer serves as the first substrate.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: April 24, 2012
    Assignees: Sino-American Silicon Products Inc.
    Inventors: Miin-Jang Chen, Wen-Ching Hsu, Suz-Hua Ho
  • Patent number: 8110427
    Abstract: A stacked-layered thin film solar cell and a manufacturing method thereof are provided. The stacked-layered thin film solar cell includes a front electrode layer, a stacked-layered light-absorbing structure, and a back electrode layer. The stacked-layered light-absorbing structure has a p-i-n-type layered structure and consists essentially of I-III-VI compounds, wherein the group III elements at least include indium (In) and aluminum (Al). The p-type layer of the stacked-layered light-absorbing structure is near the front electrode layer while the n-type layer is near the back electrode layer. The Al/In concentration ratio in the p-type layer is higher than that in the n-type layer.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: February 7, 2012
    Assignee: Nexpower Technology Corp.
    Inventor: Feng-Chien Hsieh
  • Publication number: 20110291109
    Abstract: An avalanche photodetector comprising a multiplication layer formed of a first material having a first polarization; the multiplication layer having a first electric field upon application of a bias voltage; an absorption layer formed of a second material having a second polarization forming an interface with the multiplication layer; the absorption layer having a second electric field upon application of the bias voltage, the second electric field being less than the first electric field or substantially zero, carriers created by light absorbed in the absorption layer being multiplied in the multiplication layer due to the first electric field; the absorption layer having a second polarization which is greater or less than the first polarization to thereby create an interface charge; the interface charge being positive when the first material predominately multiplies holes, the interface charge being negative when the first material predominately multiplies electrons, the change in electric field at the inte
    Type: Application
    Filed: May 26, 2011
    Publication date: December 1, 2011
    Applicant: U.S. Government as represented by the Secretary of the Army
    Inventors: MICHAEL WRABACK, Paul H. Shen, Anand V. Sampath
  • Patent number: 8053815
    Abstract: Disclosed herein is a solid-state image pickup device including, a plurality of light receiving units, a transfer channel, a first transfer electrode, a second transfer electrode, first wiring, and second wiring.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: November 8, 2011
    Assignee: Sony Corporation
    Inventor: Takeshi Takeda
  • Patent number: 8044435
    Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: October 25, 2011
    Assignee: Lockheed Martin Corporation
    Inventors: Jeffrey W. Scott, Colin E. Jones, Ernie J. Caine, Charles A. Cockrum
  • Patent number: 8013381
    Abstract: A semiconductor device has a semiconductor substrate of a first conductivity type; first to third high-voltage insulated-gate field effect transistors formed on a principal surface of the semiconductor substrate; a first device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the second high-voltage insulated-gate field effect transistor from each other; a second device isolation insulating film that is formed in the semiconductor substrate and isolates the first high-voltage insulated-gate field effect transistor and the third high-voltage insulated-gate field effect transistor from each other; a first impurity diffusion layer of the first conductivity type that is formed below the first device isolation insulating film; and a second impurity diffusion layer of the first conductivity type that is formed below the second device isolation insulating film.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norio Magome, Toshifumi Minami, Tomoaki Hatano, Norihisa Arai
  • Patent number: 7928473
    Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: April 19, 2011
    Assignee: An Elbit Systems-Rafael Partnership
    Inventor: Philip Klipstein
  • Patent number: 7915640
    Abstract: A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 29, 2011
    Assignee: Sony Corporation
    Inventor: Masaya Uemura
  • Publication number: 20110049566
    Abstract: A dual band photodetector for detecting infrared and ultraviolet optical signals is disclosed. Aspects include homojunction and heterojunction detectors comprised of one or more of GaN, AlGaN, and InGaN. In one aspect ultraviolet/infrared dual-band detector is disclosed that is configured to simultaneously detect UV and IR.
    Type: Application
    Filed: October 19, 2010
    Publication date: March 3, 2011
    Applicant: GEORGIA STATE UNIVERSITY RESEARCH FOUNDATION, INC.
    Inventors: A.G. Unil Perera, Steven George Matsik
  • Patent number: 7875961
    Abstract: A semiconductor substrate, of GaAs with a semiconductor layer sequence applied on top of the substrate. The semiconductor layer sequence comprises a plurality of semiconductor layers of Al1-yGayAs1-xPx with 0?x?1 and 0?y?1. A number of the semiconductor layers respectively comprising a phosphorus component x which is greater than in a neighboring semiconductor layer lying thereunder in the direction of growth of the semiconductor layer sequence. Two semiconductor layers directly preceding the uppermost semiconductor layer of the semiconductor layer sequence have a smaller lattice constant than the uppermost layer.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: January 25, 2011
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Norbert Linder, Günther Grönninger, Peter Heidborn, Klaus Streubel, Siegmar Kugler
  • Patent number: 7851824
    Abstract: A light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a composition modulation layer provided on the n-type contact layer; and a transparent electrode provided on the composition modulation layer. The composition modulation layer consists of a plurality of elements which constitute the compound. A composition ratio of one of the plurality of elements is higher in the composition modulation layer than in the compound. Alternatively, the light emitting device includes: a light emitting layer; an n-type contact layer made of a compound provided on the light emitting layer; a metal layer provided on the n-type contact layer; and a transparent electrode provided on the metal layer. The metal layer is made of a metal having a lower work function than the compound.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Sawada, Akihiro Ooishi
  • Patent number: 7834379
    Abstract: The invention relates to an avalanche photodiode having enhanced gain uniformity enabled by a tailored diffused p-n junction profile. The tailoring is achieved by a two stage doping process incorporating a solid source diffusion in combination with conventional gas source diffusion. The solid source diffusion material is selected for its solubility to the dopant compared to the solubility of the multiplication layer to dopant. The solid source has a diameter between the first and second diffusion windows. Thus, there are three distinct diffusion regions during the second diffusion. The dopant in the multiplication layer at the edge region, the dopant from the solid source material with a relatively higher dopant concentration (limited by the solubility of the dopant in the solid source material) at the intermediate region, and the central region exposed to an infinite diffusion source from the solid source material as it is continually charged with new dopant from the external gas source.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 16, 2010
    Assignee: JDS Uniphase Corporation
    Inventors: Zhong Pan, David Venables, Craig Ciesla
  • Patent number: 7808065
    Abstract: A semiconductor photosensitive element comprises: a semiconductor substrate of a first conductivity type; a first light absorption layer, a first semiconductor layer of a second conductivity type, a first semiconductor layer of the first conductivity type, a second light absorption layer, and a second semiconductor layer of a second conductivity type, arranged in this order on the semiconductor substrate; a first electrode connected the second semiconductor layer of the second conductivity type; a second electrode connected to the semiconductor substrate; and a third electrode electrically connecting the first semiconductor layer of the first conductivity type to the first semiconductor layer of the second conductivity type. The third electrode is located outside a light detection region for detecting optical signals.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: October 5, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eitaro Ishimura, Masaharu Nakaji
  • Patent number: 7799592
    Abstract: Semiconductor structures include a trench formed proximate a substrate including a first semiconductor material. A crystalline material including a second semiconductor material lattice mismatched to the first semiconductor material is formed in the trench. Process embodiments include removing a portion of the dielectric layer to expose a side portion of the crystalline material and defining a gate thereover. Defects are reduced by using an aspect ratio trapping approach.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: September 21, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 7795640
    Abstract: The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: September 14, 2010
    Assignee: Semi-Conductor Devices-An Elbit Systems-Rafael Partnership
    Inventor: Philip Klipstein