Light Responsive Structure Patents (Class 257/184)
  • Patent number: 10727267
    Abstract: A method of assembling a photodetector assembly includes depositing bumps on a read out integrated circuit (ROIC) without depositing bumps on a photodiode array (PDA). The method includes assembling the PDA and ROIC together wherein each bump electrically interconnects the ROIC with a respective contact of the PDA. A photodetector assembly includes a PDA. A ROIC is assembled to the PDA, wherein the ROIC is electrically interconnected with the PDA through a plurality of electrically conductive bumps. Each bump is confined within a respective pocket between the ROIC and a respective contact of the PDA. The disclosed methods can enable focal plane array manufacturers to achieve low-cost production of ultra-fine pitch, large format imaging arrays.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: July 28, 2020
    Assignee: Sensors Unlimited, Inc.
    Inventors: Wei Zhang, Douglas Stewart Malchow, Michael J. Evans, Wei Huang, Paul L. Bereznycky, Namwoong Paik
  • Patent number: 10686532
    Abstract: An optical receiver component, wherein the receiver component comprises a first type of partial-voltage source with a first absorption edge and a second type of partial-voltage source with a second absorption edge, and the first absorption edge lies at a higher energy than the second absorption edge. Each partial-voltage source produces a partial voltage, provided a photon flux at a specific wavelength strikes the partial-voltage source, and the two partial-voltage sources are connected in series. A first number of series-connected sub-partial-voltage sources of the first type and a second number of series-connected sub-partial-voltage sources of the second type are provided. The first number and/or the second number are greater than one, and the respective deviation of the source voltages of the sub-partial-voltage sources among themselves is less than 20% in both types. Each sub-partial-voltage source comprises a semiconductor diode with a p-n junction.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 16, 2020
    Assignee: AZUR SPACE Solar Power GmbH
    Inventors: Wolfgang Guter, Daniel Fuhrmann, Christoph Peper
  • Patent number: 10686101
    Abstract: Provided is a semiconductor light emitting device which includes: a light emitting structure including a plurality of semiconductor layers and configured to generate and emit light to an outside of the light emitting structure; a transparent electrode layer disposed on the light emitting structure; a transparent protective layer disposed on the transparent electrode layer; a distributed Bragg reflector (DBR) layer disposed on the transparent protective layer and covering at least a part of the transparent electrode layer; and at least one electrode pad connected to the transparent electrode layer through a hole or via.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Ha Yeong Son, Young Sub Shin
  • Patent number: 10680086
    Abstract: A heterojunction bipolar transistor is integrated on radio frequency (RF) dies of different sizes. The heterojunction bipolar transistor includes an emitter on a first-side of a semiconductor-on-insulator (SOI) layer of an SOI substrate. The emitter is accessed from the first-side while a collector is accessed from a second-side of the SOI substrate. One or more portions of a base of the heterojunction bipolar transistor is between the emitter and one or more portions of the collector. The heterojunction bipolar transistor also includes a compound semiconductor layer between the collector and the emitter. The compound semiconductor layer carries a charge between the emitter and the collector.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 9, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, George Pete Imthurn, Stephen Alan Fanelli
  • Patent number: 10680124
    Abstract: Disclosed are systems and methods for improving applications involving the generation and detection of electromagnetic radiation at terahertz (THz) frequencies. Embodiments of the systems and methods include the fabrication and use of plasmonic devices that enhance light-matter interaction at the nanometer scale by extreme focusing with nanostructured metals. This plasmonic enhancement is used to produce high efficiency THz photoconductive switches that combine the benefits of low-temperature grown GaAs while using mature 1.55 ?m femtosecond lasers operating with photon energy below the GaAs band-gap.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: June 9, 2020
    Assignee: UVic Industry Partnerships Inc.
    Inventors: Thomas E. Darcie, Reuven Gordon, Afshin Jooshesh
  • Patent number: 10680131
    Abstract: An example device includes a doped absorption region to receive optical energy and generate free electrons from the received optical energy. The example device also includes a doped charge region to increase an electric field. The example device also includes an intrinsic multiplication region to generate additional free electrons from impact ionization of the generated free electrons. The example device includes a doped contact region to conduct the free electrons and the additional free electrons.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: June 9, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Zhihong Huang, Raymond G Beausoleil
  • Patent number: 10644480
    Abstract: An optical module includes a light-forming part configured to form light; and a protective member that includes an output window configured to transmit light from the light-forming part and that is disposed so as to surround the light-forming part. The light-forming part includes a base member; a plurality of semiconductor light-emitting devices mounted on the base member and configured to emit light differing from each other in wavelength; and a filter mounted on the base member and configured to directly receive and coaxially multiplex diverging light from the plurality of semiconductor light-emitting devices.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 5, 2020
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hiromi Nakanishi
  • Patent number: 10608070
    Abstract: An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformize the potential of the upper electrode without reducing the light emission area.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 31, 2020
    Assignee: Japan Display Inc.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10580923
    Abstract: A disclosed optical semiconductor device includes a first semiconductor layer having a first refractive index and a first optical absorption coefficient; and a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a second refractive index and a second optical absorption coefficient. The second refractive index is larger than the first refractive index, and the second optical absorption coefficient is larger than the first optical absorption coefficient. The first semiconductor layer includes a first region of p-type, a second region of n-type, a third region of p-type or n-type between the first region and the second region, a fourth region of i-type between the first region and the third region, and a fifth region of i-type between the second region and the third region. The second semiconductor layer is formed on the first region, the fourth region, and the third region.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 3, 2020
    Assignees: FUJITSU LIMITED, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventor: Takasi Simoyama
  • Patent number: 10566576
    Abstract: This disclosure provides a display panel including a first substrate with pixel areas and emission areas defined by a plurality of gate lines and a plurality of data lines; and a second substrate on which partitions are formed to correspond with the emission areas. The present disclosure provides a method for improving luminance efficiency of a display device having a mirror or transmittance function.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 18, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Eui-Tae Kim, Ki-Seob Shin
  • Patent number: 10546663
    Abstract: An electrical conductor includes: a first conductive layer including a plurality of ruthenium oxide nanosheets, wherein at least one ruthenium oxide nanosheet of the plurality of ruthenium oxide nanosheets includes a halogen, a chalcogen, a Group 15 element, or a combination thereof on a surface of the ruthenium oxide nanosheet.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: January 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungwoo Hwang, Se Yun Kim, Jong Wook Roh, Woojin Lee, Jongmin Lee, Doh Won Jung, Chan Kwak
  • Patent number: 10529878
    Abstract: A Ge-on-Si photodetector constructed without doping or contacting Germanium by metal is described. Despite the simplified fabrication process, the device has responsivity of 1.24 A/W, corresponding to 99.2% quantum efficiency. Dark current is 40 nA at ?4 V reverse bias. 3-dB bandwidth is 30 GHz.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Wetteland Baehr-Jones, Yi Zhang, Michael J. Hochberg, Ari Novack
  • Patent number: 10455175
    Abstract: A voltage limiting unit of a solid state imaging device limits a voltage of a signal line so as not to become a predetermined value or less. A signal processing unit to which a pixel signal is input via a signal line. A controlling unit is disposed between the voltage limiting unit and the signal processing unit on the signal line. Further, the controlling unit causes the voltage limiting unit and the signal processing unit to be non-conductive in a period in which a transfer unit of a pixel transfers the electric charge converted by a photoelectric conversion unit of the pixel to a floating diffusion region of the pixel.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 22, 2019
    Assignee: NIKON CORPORATION
    Inventor: Hideaki Matsuda
  • Patent number: 10418409
    Abstract: Disclosed herein is an apparatus comprising: an array of avalanche photodiodes (APDs), each of the APDs comprising an absorption region and an amplification region; wherein the absorption region is configured to generate charge carriers from a photon absorbed by the absorption region; wherein the amplification region comprises a junction with an electric field in the junction; wherein the electric field is at a value sufficient to cause an avalanche of charge carriers entering the amplification region, but not sufficient to make the avalanche self-sustaining; wherein the junctions of the APDs are discrete.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 17, 2019
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10411149
    Abstract: A lateral Ge/Si APD constructed on a silicon-on-insulator wafer includes a silicon device layer having regions that are doped to provide a lateral electric field and an avalanche region. A region having a modest doping level is in contact with a germanium body. There are no metal contacts made to the germanium body. The electrical contacts to the germanium body are made by way of the doped regions in the silicon device layer.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 10, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Ari Novack, Yang Liu, Yi Zhang
  • Patent number: 10367284
    Abstract: According to an example, a socket to support a first board in a spaced relation to a second board may include a base section having openings to receive connectors that are to electrically connect the first board to the second board. The socket may also include a plurality of walls extending from the base section, in which each of the plurality of walls is angled with respect to the base section and in which the plurality of walls include air ducts to enable air to flow through the socket when the first board is positioned on the socket. The socket may further include socket alignment elements extending from the base section, in which the alignment elements are to be inserted into mating holes in the second board.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: July 30, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin B Leigh, George D Megason, John Norton
  • Patent number: 10361335
    Abstract: A method includes: forming a first mask having a first opening and a second opening; performing etching by using the first mask, to allow the etching to progress at a higher rate in the second opening than in the first opening; forming a second mask having a third opening and a fourth opening; performing etching by using the second mask, to form a mesa in a region interposed by the third opening, and an n-type contact region in the fourth opening; and forming a first electrode on the mesa and a second electrode on the n-type contact region, the first electrode being electrically connected to the third layer, the second electrode being electrically connected to the first layer, wherein a region covered with the first mask and exposed through the fourth opening of the second mask turns into the n-type contact region after the etching using the second mask.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: July 23, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Daisuke Kimura, Sundararajan Balasekaran
  • Patent number: 10361243
    Abstract: A method for making a CMOS image sensor may include forming a plurality of laterally adjacent infrared (IR) photodiode structures on a semiconductor substrate having a first conductivity type. Forming each IR photodiode structure may include forming a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may have the first conductivity type. A semiconductor layer may be formed on the superlattice, along with a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well above the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: July 23, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Marek Hytha
  • Patent number: 10340407
    Abstract: An avalanche photodetector (APD) includes a photo converter for signals to be demodulated into free charge carriers; and at least one avalanche amplifier for the free charge carriers. The photo converter and the avalanche amplifier are located next to each other on the same substrate and are in direct contact with each other. The avalanche amplifier includes a contact layer and a multiplier layer. The multiplier layer is made of a semiconductor of the same conductivity type as the photo converter and faces the substrate abutting the photo converter on one side. A first electrode is on the contact layer of the avalanche amplifier, while the second electrode is on a bottom of the substrate.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: July 2, 2019
    Assignee: LLC “Dephan”
    Inventors: Vitaly Emmanuilovich Shubin, Dmitry Alexeevich Shushakov, Nikolay Afanasievich Kolobov
  • Patent number: 10332931
    Abstract: The semiconductor device comprises a semiconductor wafer with an integrated circuit, formed by a plurality of dies, a further semiconductor wafer, which differs from the semiconductor wafer in diameter and semiconductor material, the semiconductor wafer and the further semiconductor wafer being bonded to one another by means of a bonding layer, and an electrically conductive contact layer arranged on the further semiconductor wafer opposite to the bonding layer.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: June 25, 2019
    Assignee: ams AG
    Inventors: Cathal Cassidy, Joerg Siegert, Franz Schrank
  • Patent number: 10326095
    Abstract: An organic light emitting display panel includes a substrate, a driving transistor provided on the substrate, a first insulation layer covering the driving transistor, a second insulation layer covering the first insulation layer, a first electrode provided on the second insulation layer and connected to a first conductor part of the driving transistor, a second electrode provided on the second insulation layer and connected to a second conductor part of the driving transistor, a passivation layer covering the first electrode, the second electrode, and the second insulation layer, and an organic light emitting diode provided on the passivation layer, an anode configuring the organic light emitting diode is connected to the first conductor part, and the anode protrudes convexly from an upper surface of the passivation layer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 18, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Min-Gu Kang, DaeHwan Kim
  • Patent number: 10312397
    Abstract: An Si/Ge SACM avalanche photodiodes (APD) having low breakdown voltage characteristics includes an absorption region and a multiplication region having various layers of particular thicknesses and doping concentrations. An optical waveguide can guide infrared and/or optical signals or energy into the absorption region. The resulting photo-generated carriers are swept into the i-Si layer and/or multiplication region for avalanche multiplication. The APD has a breakdown bias voltage of well less than 12 V and an operating bandwidth of greater than 10 GHz, and is therefore suitable for use in consumer electronic devices, high speed communication networks, and the like.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: June 4, 2019
    Assignee: Intel Corporation
    Inventors: Yimin Kang, Han-Din Liu
  • Patent number: 10276816
    Abstract: A semiconductor device that includes a layer of highly crystalline semiconductor material positioned on an insulating substrate. The semiconductor device also includes a source structure and a drain structure positioned on the layer of highly crystalline semiconductor material. The semiconductor device also includes a photoelectric element positioned on the layer of highly crystalline semiconductor material. The photoelectric element forms an electrical junction with the layer of highly crystalline semiconductor material. The photoelectric element is positioned between the source structure and the drain structure. The photoelectric element is also electrically floating.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Joel P. de Souza, Bahman Hekmatshoartabari, Daniel M. Kuchta, Devendra K. Sadana
  • Patent number: 10250282
    Abstract: A structure for radiofrequency applications includes: a semiconducting supporting substrate, and a trapping layer arranged on the supporting substrate. The trapping layer includes a higher defect density than a predetermined defect density. The predetermined defect density is the defect density beyond which the electric resistivity of the trapping layer is no lower than 10,000 ohm·cm over a temperature range extending from ?20° C. to 120° C.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 2, 2019
    Assignee: Soitec
    Inventors: Oleg Kononchuk, Didier Landru, Christophe Figuet
  • Patent number: 10186626
    Abstract: A two-terminal photon-effect transistor (PET) is described that simplifies the photo sensing pixel by combing photodiode and field effect transistor dual functions into one simple but effective unit. Photons excite electrons from the valance band of semiconducting material as the electrode-free gate to modulate resistivity between source and drain, which directly results in current amplification of photo signal without traditional photo-electrical conversion and electrical amplification dual processes. PET possesses significance in both structural simplification and functional enhancement. As an implementing example of PET, a nanowire camera (NC) with large sensing area and extremely high resolution is fabricated by integrating millions of vertically aligned nanowire arrays in-between of orthogonal top and bottom nano-stripe electrodes. Each nanowire works as independent three-dimensional (3D) PET pixel, enabling the NC an ultra-high resolution and much simplified architecture.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: January 22, 2019
    Assignee: Forwarding Technology LTD
    Inventors: Jinhui Song, Chengming Jiang
  • Patent number: 10170612
    Abstract: Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Niloy Mukherjee, Marko Radosavljevic, Robert S. Chau
  • Patent number: 10158035
    Abstract: A semiconductor stack includes a first-conductivity-type layer of a first conductivity type, the first-conductivity-type layer being formed of a III-V compound semiconductor; a quantum well light-receiving layer formed of a III-V compound semiconductor; and a second-conductivity-type layer of a second conductivity type different from the first conductivity type, the second-conductivity-type layer being formed of a III-V compound semiconductor. The first-conductivity-type layer, the quantum well light-receiving layer, and the second-conductivity-type layer are stacked in this order. The quantum well light-receiving layer has a thickness of 0.5 ?m or more. The quantum well light-receiving layer has a carrier concentration of 1×1016 cm?3 or less.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: December 18, 2018
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takuma Fuyuki, Suguru Arikata, Takashi Kyono, Yusuke Yoshizumi, Katsushi Akita
  • Patent number: 10141430
    Abstract: The present disclosure provides a method of forming a semiconductor device structure. The method includes determining a threshold voltage distribution profile along a height of a silicon germanium (SiGe) fin structure over a semiconductor substrate; determining a germanium (Ge) concentration profile to counteract the threshold voltage distribution profile according to a correlation between Ge concentration and threshold voltage in the SiGe fin structure; forming a SiGe epitaxial layer with the Ge concentration profile along a thickness of the SiGe epitaxial layer; etching the SiGe epitaxial layer to form the SiGe fin structure; and forming, on the SiGe fin structure, a field-effect transistor having a uniform threshold voltage along the height of the SiGe fin structure.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Ka-Hing Fung
  • Patent number: 10132996
    Abstract: A method forms a vertical output coupler for a waveguide, formed of waveguide material and disposed within a layer stack on a top surface of a wafer. The method includes etching through a portion of the wafer to form a via that exposes the waveguide material, and etching the waveguide material to remove at least a first portion of the waveguide. The etching forms a tilted plane in the waveguide material. The method further includes coating the first tilted plane with one or more reflective layers, to form a tilted mirror in contact with the first tilted plane in the waveguide material. The tilted mirror forms the vertical output coupler such that light propagating through the waveguide is deflected by the tilted mirror, and exits the waveguide.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Skorpios Technologies, Inc.
    Inventor: Damien Lambert
  • Patent number: 10134955
    Abstract: A light emitting element includes a semiconductor stacked body, an oxide film, and a reflecting film. The semiconductor stacked body has a body surface. The oxide film has an upper surface and a bottom surface opposite to the upper surface. The oxide film is provided on the semiconductor stacked body such that the bottom surface of the oxide film is opposite to the body surface of the semiconductor stacked body. The reflecting film is provided on the oxide film to be in contact with the upper surface of the oxide film and includes silver and oxide nanoparticles.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: November 20, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Shuji Shioji, Masafumi Kuramoto
  • Patent number: 10128954
    Abstract: A transceiver comprising a chip, a semiconductor laser, and one or more photodetectors, the chip comprising optical and optoelectronic devices and electronic circuitry, where the transceiver is operable to: communicate, utilizing the semiconductor laser, an optical source signal into the chip, generate first optical signals in the chip based on the optical source signal, transmit the first optical signals from the chip via a light pipe with a sloped reflective surface coupled to the chip, and receive second optical signals from the light pipe and converting the second optical signals to electrical signals via the photodetectors. The optical signals may be communicated out of and in to a top surface of the chip. The one or more photodetectors may be integrated in the chip. The optoelectronic devices may include the one or more photodetectors integrated in the chip. The light pipe may be a planar lightwave circuit (PLC).
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 13, 2018
    Assignee: Luxtera, Inc.
    Inventors: Peter DeDobbelaere, Thierry Pinguet, Mark Peterson, Mark Harrison, Alexander G. Dickinson, Lawrence C. Gunn
  • Patent number: 10121922
    Abstract: Embodiments of the present disclosure are directed to infrared detector devices incorporating a tunneling structure. In one embodiment, an infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a tunneling structure including a barrier layer adjacent to the absorber layer and a second contact layer adjacent to the barrier layer. The barrier layer has a tailored valence band offset such that a valence band offset of the barrier layer at the interface between the absorber layer and the barrier layer is substantially aligned with the valence band offset of the absorber layer, and the valence band offset of the barrier layer at the interface between the barrier layer and the second contact layer is above a conduction band offset of the second contact layer.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 6, 2018
    Assignee: L3 CINCINNATI ELECTRONICS CORPORATION
    Inventor: Yajun Wei
  • Patent number: 10121921
    Abstract: Embodiments of the present disclosure are directed to infrared detector devices incorporating a tunneling structure. In one embodiment, an infrared detector device includes a first contact layer, an absorber layer adjacent to the first contact layer, and a tunneling structure including a barrier layer adjacent to the absorber layer and a second contact layer adjacent to the barrier layer. The barrier layer has a tailored valence band offset such that a valence band offset of the barrier layer at the interface between the absorber layer and the barrier layer is substantially aligned with the valence band offset of the absorber layer, and the valence band offset of the barrier layer at the interface between the barrier layer and the second contact layer is above a conduction band offset of the second contact layer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 6, 2018
    Assignee: L3 CINCINNATI ELECTRONICS CORPORATION
    Inventor: Yajun Wei
  • Patent number: 10090293
    Abstract: An integrated device is provided. The integrated device includes a substrate having a doped upper surface section and an insulator to define first and second substrate regions on opposite sides thereof. Vertical transistors are operably arranged on the doped upper surface section at the first substrate region. P-I-N diodes are operably arranged on the doped upper surface section at the second substrate region.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10090426
    Abstract: A photosensor device for reducing dark current is disclosed. The photosensor device includes a photon absorbing layer and two or more photosensor diffusions in said absorbing layer. The photosensor diffusions in the absorbing layer have edges of their diffusions separated in said absorbing layer by less than two minority carrier diffusion lengths. The photosensor device also includes in one embodiment one or more diffusion control junction diffusions in the absorbing layer and in proximity to the photosensor diffusions. In another embodiment the photosensor diffusions are selectively biased to operate as photosensor diodes or as diffusion impediments.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: October 2, 2018
    Assignee: Trustees of Boston University
    Inventors: Adam R. Wichman, Enrico Bellotti, Benjamin James Pinkie
  • Patent number: 10090422
    Abstract: An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: October 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Bruce W. Porth, Steven M. Shank
  • Patent number: 10066158
    Abstract: A molded nanoparticle phosphor for light emitting applications is fabricated by converting a suspension of nanoparticles in a matrix material precursor into a molded nanoparticle phosphor. The matrix material can be any material in which the nanoparticles are dispersible and which is moldable. The molded nanoparticle phosphor can be formed from the matrix material precursor/nanoparticle suspension using any molding technique, such as polymerization molding, contact molding, extrusion molding, injection molding, for example. Once molded, the molded nanoparticle phosphor can be coated with a gas barrier material, for example, a polymer, metal oxide, metal nitride or a glass. The barrier-coated molded nanoparticle phosphor can be utilized in a light-emitting device, such as an LED. For example, the phosphor can be incorporated into the packaging of a standard solid state LED and used to down-convert a portion of the emission of the solid state LED emitter.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: September 4, 2018
    Assignee: Nanoco Technologies, Ltd.
    Inventors: Imad Naasani, Hao Pang
  • Patent number: 10043920
    Abstract: A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10026898
    Abstract: Methods of making solid-state semiconducting films. The methods include forming a mixture by mixing at least two monomers in a pre-determined proportion such that at least one of the at least two monomers contains at least one non-conjugation spacer. Polymerization of the mixture is achieved by reacting the monomers with one another resulting in a solid state polymer which is then purified. The purified solid state polymer is dissolved in an organic solvent to form a homogenous solution which is then deposited onto a substrate, forming a solid-state semiconducting film by evaporating the solvent. Alternatively, the purified solid state polymer is deposited onto a substrate and heated to form a liquid melt, and cooling the liquid melt results in a solid state semiconducting thin film. Also, films comprising a semiconducting polymer composition containing a minimum of one non-conjugation spacer and devices comprising such films.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: July 17, 2018
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Jianguo Mei, Yan Zhao
  • Patent number: 9985231
    Abstract: Systems and methods are described to form compositionally graded BHJ structures utilizing solvent-fluxing techniques. In implementations, the systems and methods described herein involve a high boiling point additive, a solution of a polymer donor and an acceptor, a substrate material, a working solvent, and a flux solvent for formation of compositionally graded BHJ structures.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 29, 2018
    Assignee: NUtech Ventures, Inc.
    Inventors: Jinsong Huang, Zhengguo Xiao
  • Patent number: 9978890
    Abstract: Embodiments herein describe a photonic device that includes a germanium photodetector coupled to multiple silicon waveguides. In one embodiment, the silicon waveguides optically couple to a layer of germanium material. In one embodiment, if the germanium material forms a polygon, then a respective silicon waveguide optically couple to each of the corners of the polygon. Each of the plurality of input silicon waveguides may be arranged to transmit light in a direction under the germanium that is offset relative to both sides of the germanium forming the respective corner. In another example, the germanium material may be a circle or ellipse in which case the silicon waveguides terminate at or close to a non-straight, curved surface of the germanium material. As described below, optically coupling the silicon waveguides at a non-straight surface can reduce the distance charge carriers have to travel in the optical detector which can improve bandwidth.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: May 22, 2018
    Assignee: Cisco Technology, Inc.
    Inventors: Igal I. Bayn, Vipulkumar Patel, Sean P. Anderson, Prakash Gothoskar
  • Patent number: 9960297
    Abstract: Embodiments of the invention describe apparatuses, optical systems, and methods related to utilizing optical cladding layers. According to one embodiment, a hybrid optical device includes a silicon semiconductor layer and a III-V semiconductor layer having an overlapping region, wherein a majority of a field of an optical mode in the overlapping region is to be contained in the III-V semiconductor layer. A cladding region between the silicon semiconductor layer and the III-V semiconductor layer has a spatial property to substantially confine the optical mode to the III-V semiconductor layer and enable heat dissipation through the silicon semiconductor layer.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: May 1, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Erik Johan Norberg, Anand Ramaswamy, Brian Koch
  • Patent number: 9952479
    Abstract: The present invention relates to a display substrate and a method for fabricating the same, a display panel and a display device. The display substrate comprises a plurality of pixels, each of which has a display region, a non-display region being between the plurality of pixels, and the display substrate further comprises a protection metal layer covering the non-display region. In the display substrate, the protection metal layer covers the non-display region of the display substrate so as to shield the structures of the thin-film transistors, signal lines and the like on the display substrate, and thus the stability of structure of the display panel as well as the high resolution of the display panel and excellent display effect thereof can be ensured, and, in the meantime, the procedure of fabrication process is simplified, the manufacture efficiency is improved, and the cost for manufacturing is reduced.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 24, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY, CO., LTD.
    Inventors: Binbin Cao, Peng Jiang, Peng Chen, Jongwon Moon, Yinhu Huang, Chengshao Yang, Haipeng Yang
  • Patent number: 9927572
    Abstract: Examples include hybrid silicon photonic device structures. Some examples include a method of integrating a photodetector with a photonic device on a silicon wafer to make a hybrid silicon photonic device structure. A dielectric layer is established on the silicon wafer. A pit is formed in a portion of the dielectric layer and the silicon wafer, wherein a bottom of the pit is silicon. A germanium layer is grown in the pit such that a top of the germanium layer is lower than a top of the silicon wafer. The germanium layer comprises the photodetector. A photonic device material that comprises the photonic device is bonded to the silicon wafer without planarization of the silicon wafer.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: March 27, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Geza Kurczveil, Di Liang, Zhihong Huang, Raymond G Beausoleil
  • Patent number: 9923114
    Abstract: An infrared detector is provided. The infrared detector includes an absorption layer sensitive to radiation in only a short wavelength infrared spectral band, and a barrier layer coupled to the absorption layer. The barrier layer is fabricated from an alloy including aluminum and antimony, and at least one of gallium or arsenic, and the composition of the alloy is selected such that valence bands of the absorption layer and the barrier layer substantially align.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: March 20, 2018
    Assignee: THE BOEING COMPANY
    Inventors: Terence J. de Lyon, Sevag Terterian, Hasan Sharifi
  • Patent number: 9922934
    Abstract: A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a notch at the periphery of the carrier, and the notch is light transmissive so as to expose the carrier to light in a normal direction of the carrier. A semiconductor manufacturing process is also provided.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hui Wang, Chih-Hung Cheng, Yung-Chi Lin, Wen-Chih Chiou
  • Patent number: 9904078
    Abstract: An optical modulator and a 3D image acquisition apparatus including an optical modulator are provided. The optical modulator is disposed in a multiple quantum well including a plurality of quantum wells and a plurality of quantum barriers, and includes at least one carrier block disposed in the multiple quantum well restricting the carrier movement between the multiple quantum wells.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: February 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-young Park, Yong-hwa Park, Sang-hun Lee
  • Patent number: 9906304
    Abstract: A transceiver comprising a chip, a semiconductor laser, and one or more photodetectors, the chip comprising optical and optoelectronic devices and electronic circuitry, where the transceiver is operable to: communicate, utilizing the semiconductor laser, an optical source signal into the chip via a light pipe with a sloped reflective surface, generate first optical signals in the chip based on the optical source signal, transmit the first optical signals from the chip via the light pipe, and receive second optical signals from the light pipe and converting the second optical signals to electrical signals via the photodetectors. The optical signals may be communicated out of and in to a top surface of the chip. The one or more photodetectors may be integrated in the chip. The optoelectronic devices may include the one or more photodetectors integrated in the chip. The light pipe may be a planar lightwave circuit (PLC).
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: February 27, 2018
    Assignee: Luxtera, Inc.
    Inventors: Peter DeDobbelaere, Thierry Pinguet, Mark Peterson, Mark Harrison, Alexander G. Dickinson, Lawrence C. Gunn
  • Patent number: 9887324
    Abstract: A light emitting device package is disclosed. The light emitting device package includes a package body including at least one ceramic layer, a submount disposed at the package body, a light emitting device disposed on the submount for emitting ultraviolet (UV)-wavelength light, and an anti-reflection (AR) coating layer disposed around the light emitting device, the AR coating layer being formed of an inorganic coating layer.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 6, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Baek Jun Kim, Hiroshi Kodaira, Byung Mok Kim, Ha Na Kim, Yuichiro Tanda, Satoshi Ozeki
  • Patent number: 9876946
    Abstract: An imaging device with low power consumption is provided. A pixel circuit has a configuration of detecting difference data between data of a reference frame and data of a target frame in a pixel, and a peripheral circuit has a configuration of efficiently converting the difference data by A/D conversion so as to obtain high compressibility. Difference data which is encoded by compression is written into a memory element and read sequentially. At this time, the frequency of a clock signal can be lowered in accordance with the amount of data. The read data is expanded and the expanded data is added to the reference frame to constitute an image.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki Ikeda