Having Graded Composition Patents (Class 257/191)
  • Patent number: 10777675
    Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: September 15, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Teruyuki Ohashi, Ryosuke Iijima, Hiroshi Kono, Tatsuo Shimizu
  • Patent number: 10778262
    Abstract: A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 15, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 10541321
    Abstract: In a manufacturing method of a semiconductor device according to the present invention, a buffer layer including a first nitride semiconductor layer, a channel layer including a second nitride semiconductor layer, and a barrier layer including a third nitride semiconductor layer are sequentially laminated, and a fourth nitride semiconductor layer is further laminated thereover. Then, a laminate of a gate insulating film and a gate electrode is formed over a first region of the fourth nitride semiconductor layer, and a silicon nitride film is formed over the fourth nitride semiconductor layer and the laminate. By bringing the fourth nitride semiconductor layers on both sides of the gate electrode into contact with the silicon nitride film in this way, the function of suppressing 2DEG can be lowered, and the 2DEG that has been eliminated after the formation of the fourth nitride semiconductor layer can be restored.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuhiro Okamoto
  • Patent number: 10355093
    Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Gopinath Bhimarasetti, Walid M. Hafez, Joodong Park, Weimin Han, Raymond E. Cotner, Chia-Hong Jan
  • Patent number: 10326481
    Abstract: A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 18, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 10319811
    Abstract: A finFET semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region further includes a condensed portion formed of a first semiconductor material and a second semiconductor material. The source/drain regions are formed of the first semiconductor material while excluding the second semiconductor material.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hong He, Effendi Leobandung, Gen Tsutsui, Tenko Yamashita
  • Patent number: 10312344
    Abstract: A semiconductor device includes a first semiconductor layer formed of a compound semiconductor, provided over a substrate; a second semiconductor layer formed of a compound semiconductor including In and Al, provided over the first semiconductor layer; source and drain electrodes provided on the second semiconductor layer; and a gate electrode provided between the source and drain electrodes, on the second semiconductor layer. The compound semiconductor in the second semiconductor layer has a first In composition ratio in a region on a side facing the substrate and a second In composition ratio in a region on an opposite side, the second In composition ratio being lower than the first In composition ratio, and the source and drain electrodes are provided in contact with the region having the first In composition ratio, and the gate electrode is provided on the region having the second In composition ratio.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 4, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shirou Ozaki
  • Patent number: 10249714
    Abstract: A semiconductor device including a gate structure on a channel region portion of a fin structure, and at least one of an epitaxial source region and an epitaxial drain region on a source region portion and a drain region portion of the fin structure. At least one of the epitaxial source region portion and the epitaxial drain region portion include a first concentration doped portion adjacent to the fin structure, and a second concentration doped portion on the first concentration doped portion. The second concentration portion has a greater dopant concentration than the first concentration doped portion. An extension dopant region extending into the channel portion of the fin structure having an abrupt dopant concentration gradient of n-type or p-type dopants of 7 nm per decade or greater.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: April 2, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Dechao Guo, Shogo Mochizuki, Andreas Scholze, Chun-Chen Yeh
  • Patent number: 10243086
    Abstract: A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 26, 2019
    Assignee: Lancaster University Business Enterprises Limited
    Inventor: Manus Hayne
  • Patent number: 10109729
    Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen, Chen-Hao Chiang
  • Patent number: 9960265
    Abstract: In one embodiment, a III-V high electron mobility semiconductor device includes a semiconductor substrate including a GaN layer, an AlGaN layer on the GaN layer wherein a 2 DEG is formed near an interface of the GaN layer and the AlGaN layer. An insulator may be on at least a first portion of the AlGaN layer and a P-type GaN gate region may be overlying a second portion of the AlGaN layer wherein the 2 DEG does not underlie the P-type GaN gate region.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: May 1, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Abhishek Banerjee, Peter Moens, Gordon M. Grivna
  • Patent number: 9953839
    Abstract: This invention relates to an apparatus, system, and method for creating a high-k gate stack structure that includes a passivation layer. The passivation layer can be constructed from a deposition of silicon carbide. The silicon carbide provides robustness against oxidation, which can reduce the capacity of the stack. The silicon carbide is thermodynamically stable during the deposition process and results in a clean interface.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Chiara Marchiori, Federico Zipoli
  • Patent number: 9917154
    Abstract: Embodiments are directed to a method of forming a feature of a semiconductor device. The method includes forming the feature from a semiconductor material having compressive strain that extends throughout a cut region of the feature and throughout a preserve region of the feature. The method further includes converting the cut region of the feature to a dielectric.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Peng Xu
  • Patent number: 9806194
    Abstract: A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a second fin area. A gate structure is disposed on the first fin area. A source region is in contact with the second fin area. The first fin area includes the first material at a first concentration, the second fin area includes the first material at a second concentration which is greater than the first concentration.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: October 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Patent number: 9679996
    Abstract: A semiconductor device and a process to form the same are disclosed. The semiconductor device includes a support, an active semiconductor stack including a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, the first to third semiconductor layers being sequentially stacked on the support, and an electrode on the third semiconductor layer. The first semiconductor layer and the second semiconductor layer provide a buried region in a portion under the electrode, the buried region being filled with a material having a first dielectric constant smaller than a second dielectric constant of the first semiconductor layer and a third dielectric constant of the second semiconductor layer.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 13, 2017
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Masataka Watanabe
  • Patent number: 9666702
    Abstract: Methods of manufacture of advanced electronic and photonic structures including heterojunction transistors, transistor lasers and solar cells and their related structures, are described herein. Other embodiments are also disclosed herein.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: May 30, 2017
    Inventor: Matthew H. Kim
  • Patent number: 9640260
    Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 2, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Jian Li, Chandra Mouli
  • Patent number: 9590084
    Abstract: A device includes a source region, a drain region, and a semiconductor channel connecting the source region to the drain region. The semiconductor channel includes a source-side channel portion adjoining the source region, wherein the source-side channel portion has a first bandgap, and a drain-side channel portion adjoining the drain region. The drain-side channel portion has a second bandgap different from the first bandgap.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Richard Kenneth Oxland
  • Patent number: 9553155
    Abstract: In an embodiment, a semiconductor device includes a High Electron Mobility Transistor (HEMT) including a floating gate. The floating gate includes two or more electrically separated floating gate segments.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Matthias Strassburg, Gerhard Prechtl
  • Patent number: 9455338
    Abstract: Integrated circuits with bipolar transistors are provided. In one embodiment, a bipolar transistor may include an emitter region, a first base region that surrounds the emitter region, a collector region that surrounds the first base region, and a second base region that surrounds the collector region. Respective well taps may be formed within the emitter, collector, and the second base regions. A deep doped well having the same doping type as the base regions may extend beneath the emitter, collector, and base regions. In another embodiment, the bipolar transistor may include an emitter region, a base region that surrounds the emitter region, and a collector region that surrounds the base region. Respective well taps may be formed within the emitter, base, and collector regions. A deep doped well having the same doping type as the base region may extend beneath the emitter and only a portion of the base region.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 27, 2016
    Assignee: Altera Corporation
    Inventors: Albert Ratnakumar, Yanzhong Xu
  • Patent number: 9443897
    Abstract: In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: September 13, 2016
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Keiji Mabuchi, Tomonori Mori
  • Patent number: 9425276
    Abstract: The present disclosure relates to a donor layer of bi-layer AlGaN and associated method of fabrication within a high electron mobility transistor (HEMT) configured to provide low-resistance ohmic source and drain contacts to reduce power consumption, while maintaining a high-mobility of a two-dimensional electron gas (2DEG) within a channel of the HEMT. The donor layer of bi-layer AlGaN comprises a mobility-enhancing layer of AlzGa(1-z)N, a resistance-reducing layer of AlxGa(1-x)N disposed over the mobility-enhancing layer, wherein the ohmic source and drain contacts connect to the HEMT. A channel layer of GaN is disposed beneath the mobility-enhancing layer, wherein a 2DEG resides, forming the channel of the HEMT.
    Type: Grant
    Filed: January 21, 2013
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen, Chen-Hao Chiang
  • Patent number: 9406517
    Abstract: The present disclosure relates to a transistor device having a germanium cap layer that is able to provide for a low interface trap density, while meeting effective oxide thickness scaling requirements, and a related method of fabrication. In some embodiments, the disclosed transistor device has a channel layer disposed within a semiconductor body at a location between a source region and a drain region. A germanium cap layer is disposed onto the channel layer. A gate dielectric layer is separated from the channel layer by the germanium cap layer, and a gate region is disposed above the gate dielectric layer. Separating the gate dielectric layer from the channel layer allows for the germanium cap layer to prevent diffusion of atoms from the channel layer into the gate dielectric layer, thereby provide for a low interface trap density.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Georgios Vellianitis
  • Patent number: 9401583
    Abstract: A method of forming a laser on silicon using aspect ratio trapping (ART) growth. The method may include; forming a first insulator layer on a substrate; etching a trench in the first insulator layer exposing a top surface of the substrate; forming a buffer layer in the trench using ART growth; forming a laser on the buffer layer, the laser includes at least an active region and a top cladding layer; and forming a top contact on the top cladding layer and a bottom contact on the substrate.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9362280
    Abstract: An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Gauri V. Karve, Mark D. Hall, Srikanth B. Samavedam
  • Patent number: 9293582
    Abstract: Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Matthew T. Currie
  • Patent number: 9293560
    Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: March 22, 2016
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Roza Kotlyar, Uday Shah, Charles C. Kuo
  • Patent number: 9276066
    Abstract: A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 1, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryosuke Tamura, Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryohei Makino, Jiang Li
  • Patent number: 9159835
    Abstract: Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: October 13, 2015
    Assignee: Intel Corporation
    Inventors: Jack T. Kavalieros, Nancy Zelick, Been-Yih Jin, Markus Kuhn, Stephen M. Cea
  • Patent number: 9129891
    Abstract: A semiconductor device includes a first semiconductor layer provided over a substrate; an electron transit layer contacting a top of the first semiconductor layer; and a second semiconductor layer contacting a top of the electron transit layer, wherein the electron transit layer has a dual quantum well layer having a structure where a first well layer, an intermediate barrier layer, and a second well layer are sequentially stacked, an energy of a conduction band of the intermediate barrier layer is lower than an energy of conduction band of the first semiconductor layer and the second semiconductor layer, and a ground level is generated in the first and second well layers, and a first excitation level is generated in the dual quantum well layer.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: September 8, 2015
    Assignees: FUJITSU LIMITED, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventors: Akira Endoh, Issei Watanabe
  • Patent number: 9093589
    Abstract: Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: July 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Zaiyuan Ren, Thomas Gehrke
  • Patent number: 9048363
    Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. The selective low temperature epitaxy process can be performed at a temperature lower than 600° C., thereby limiting diffusion of materials within the multi-quantum well and avoiding segregation of indium within the multi-quantum well. The light-emitting diode can generate a radiation of a wide range including blue and green lights in the visible wavelength range.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: June 2, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Wilfried Haensch, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 9048362
    Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers containing a nitride semiconductor and a light emitting layer. The emitting layer includes a barrier layer containing III group elements, and a well layer stacked with the barrier layer and containing III group elements. The barrier layer is divided into a first portion on an n-type semiconductor layer side and a second portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the second portion is lower than that of the first portion. The well layer is divided into a third portion on an n-type semiconductor layer side and a fourth portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the fourth portion is higher than that of the third portion.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: June 2, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Yoshiyuki Harada, Hajime Nago, Koichi Tachibana, Shinya Nunoue
  • Patent number: 9048379
    Abstract: A light-emitting device of an embodiment of the present application comprises a semiconductor layer sequence provided with a first main side, a second main side, and an active layer; a beveled trench formed in the semiconductor layer sequence, having a top end close to the second main side, a bottom end, and an inner sidewall connecting the top end and the bottom end. In the embodiment, the inner sidewall is an inclined surface. The light-emitting device further comprises a dielectric layer disposed on the inner sidewall of the beveled trench and the second main side; a first metal layer formed on the dielectric layer; a carrier substrate; and a first connection layer connecting the carrier substrate and the semiconductor layer sequence.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: June 2, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Yu-Chen Yang, Li-Ping Jou, Hui-Chun Yeh, Yi-Wen Ku
  • Patent number: 9018679
    Abstract: A semiconductor device includes: an operation layer that is provided on a substrate and is made of a GaAs-based semiconductor; a first AlGaAs layer provided on the operation layer; a gate electrode provided on the first AlGaAs layer; an second AlGaAs layer having n-type conductivity and provided on the first AlGaAs layer of both sides of the gate electrode, an Al composition ratio of the second AlGaAs layer being larger than that of the first AlGaAs layer and being equal to or more than 0.3 and equal to or less than 0.5; an n-type GaAs layer selectively provided on the second AlGaAs layer; and a source electrode and a drain electrode that contain Au and are provided on the n-type GaAs layer.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: April 28, 2015
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Yasuyo Kurachi
  • Patent number: 9018676
    Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and third and fourth semiconductor layers of the first conductivity type formed between the first and second semiconductor layer. The first, the third, the fourth, and the second semiconductor layers are coupled in this order. A band gap of the third semiconductor layer is narrower than that of the first semiconductor layer, and a band gap of the fourth semiconductor layer is narrower than that of the third semiconductor layer.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Limited
    Inventor: Tsuyoshi Takahashi
  • Patent number: 9006707
    Abstract: In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si) substrate that includes an indium gallium arsenide (InGaAs)-based stack including a first buffer layer, a second buffer layer formed over the first buffer layer, a first device layer formed over the second buffer layer. Further, the method may include forming a p-type semiconductor device over the Si substrate from the InGaAs-based stack and forming an isolation between the n-type semiconductor device and the p-type semiconductor device. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Mantu K. Hudait, Jack T. Kavalieros, Suman Datta, Marko Radosavljevic
  • Patent number: 8994071
    Abstract: We have observed anomalous behavior of II-VI semiconductor devices grown on certain semiconductor substrates, and have determined that the anomalous behavior is likely the result of indium atoms from the substrate migrating into the II-V layers during growth. The indium can thus become an unintended dopant in one or more of the II-VI layers grown on the substrate, particularly layers that are close to the growth substrate, and can detrimentally impact device performance. We describe a variety of semiconductor constructions and techniques effective to deplete the migrating indium within a short distance in the growth layers, or to substantially prevent indium from migrating out of the substrate, or to otherwise substantially isolate functional II-VI layers from the migrating indium, so as to maintain good device performance.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: March 31, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Thomas J. Miller, Michael A. Haase, Xiaoguang Sun
  • Patent number: 8963204
    Abstract: According to one embodiment, a semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, an insulating film, an ohmic electrode, and a Schottky electrode. A surface region of the third nitride semiconductor layer between the ohmic electrode and the Schottky electrode contains an element heterogeneous with the constituent element of the third nitride semiconductor layer at a higher concentration than a region of the third nitride semiconductor layer of the second nitride semiconductor layer side.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Toshiyuki Naka
  • Patent number: 8952419
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Patent number: 8946765
    Abstract: Semiconductor structures comprising a III-nitride (e.g., gallium nitride) material region and methods associated with such structures are provided. In some embodiments, the structures include an electrically conductive material (e.g., gold) separated from certain other region(s) of the structure (e.g., a silicon substrate) by a barrier material in order to limit, or prevent, undesirable reactions between the electrically conductive material and the other component(s) which can impair device performance. In certain embodiments, the electrically conductive material may be formed in a via. For example, the via can extend from a topside of the device to a backside so that the electrically conductive material connects a topside contact to a backside contact. The structures described herein may form the basis of a number of semiconductor devices including transistors (e.g., FET), Schottky diodes, light-emitting diodes and laser diodes, amongst others.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 3, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Joseph Therrien, Jerry Wayne Johnson, Allen W. Hanson
  • Patent number: 8946775
    Abstract: A nitride semiconductor structure is provided. The nitride semiconductor structure at least includes a silicon substrate, a AlN layer, a AlGaN layer and a GaN layer formed on the AlGaN layer. The silicon substrate has a surface tilted at 0<tilted?0.5° with respect to a axis perpendicular to a (111) crystal plane, and the AlN layer is formed on the surface. The AlGaN layer is formed on the AlN layer. Moreover, an Al content in the AlGaN layer is decreased gradually in a layer thickness direction from the silicon substrate side toward the GaN layer side.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 3, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chen-Zi Liao, Chih-Wei Hu, Yen-Hsiang Fang, Rong Xuan
  • Patent number: 8890207
    Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
  • Patent number: 8878244
    Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuichi Kondo, Wataru Hirasawa, Nobuyuki Sugii
  • Patent number: 8878251
    Abstract: The present invention provides a silicon-compatible compound junctionless field effect transistor enabled to be compatible to a bulk silicon substrate for substituting an expensive SOI substrate, to form a blocking semiconductor layer between a silicon substrate and an active layer by a semiconductor material having a specific difference of energy bandgap from that of the active layer to substitute a prior buried oxide for blocking a leakage current at an off-operation time and to form the active layer by a semiconductor layer having electron or hole mobility higher than that of silicon, and to operate perfectly as a junctionless device though the dopant concentration of the active layer is much lower than the prior junctionless device.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: November 4, 2014
    Assignees: Seoul National University R&DB Foundation, Kyungpook National University Industry-academic Cooperation Foundation, The Board of Trustees of the Leland Stanford Junior University
    Inventors: Byung-Gook Park, Seongjae Cho, In Man Kang
  • Patent number: 8866189
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: October 21, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventors: Jun Hu, Jing Shi, Wensheng Qian, Donghua Liu, Wenting Duan, Fan Chen, Tzuyin Chiu
  • Patent number: 8823055
    Abstract: A method of forming a template on a silicon substrate includes providing a single crystal silicon substrate. The method further includes epitaxially depositing a layer of rare earth oxide on the surface of the silicon substrate. The rare earth oxide being substantially crystal lattice matched to the surface of the silicon substrate. The method further includes forming an aluminum oxide layer on the rare earth oxide, the aluminum oxide being substantially crystal lattice matched to the surface of the rare earth oxide and epitaxially depositing a layer of aluminum nitride (AlN) on the aluminum oxide layer substantially crystal lattice matched to the surface of the aluminum oxide.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: September 2, 2014
    Assignee: Translucent, Inc.
    Inventors: Erdem Arkun, Michael Lebby, Andrew Clark, Rytis Dargis
  • Patent number: 8791542
    Abstract: According to an embodiment, a solid-state imaging device includes a photoelectric, conversion element. The photoelectric conversion element includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. In the solid-state imaging device, D2m3/L2m3×ni32/N2<D1M2/L1M2×ni22/N2 and D1m1/L1m1×ni12/N1<D1m2/L1m2×ni22/N1 are established.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shuichi Toriyama, Koichi Kokubun, Hiroki Sasaki
  • Patent number: 8785942
    Abstract: A nitride semiconductor substrate suitable for a normally-off type high breakdown-voltage device and a method of manufacturing the substrate are provided allowing both a higher threshold voltage and improvement in current collapse. In a nitride semiconductor substrate 10 having a substrate 1, a buffer layer 2 formed on one principal plane of the substrate 1, an intermediate layer 3 formed on the buffer layer 2, an electron transport layer 4 formed on the intermediate layer 3, and an electron supply layer 5 formed on the electron transport layer 4, the intermediate layer 3 has a thickness of 200 nm to 1500 nm and a carbon concentration of 5×1016 atoms/cm3 to 1×1018 atoms/cm3 and is of AlxGa1-xN (0.05?x?0.24), and the electron transport layer 4 has a thickness of 5 nm to 200 nm and is of AlyGa1-yN (0?y?0.04).
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: July 22, 2014
    Assignee: Covalent Materials Corporation
    Inventors: Akira Yoshida, Jun Komiyama, Yoshihisa Abe, Hiroshi Oishi, Kenichi Eriguchi, Shunichi Suzuki
  • Patent number: 8772623
    Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Mark W. Wanlass, Jeffrey J. Carapella