Abstract: A MOSFET structure utilizing strained silicon carbon alloy and fabrication method thereof. The MOSFET structure includes a substrate, a graded SiGe layer, a relaxed buffer layer, a strained silicon carbon alloy channel layer, a gate dielectric layer, a polysilicon gate electrode (or metal gate electrode) and a source/drain region.

Abstract: The present invention includes a photodiode having a first p-type semiconductor layer and an n-type semiconductor layer coupled by a second p-type semiconductor layer. The second p-type semiconductor layer has graded doping along the path of the carriers. In particular, the doping is concentration graded from a high value near the anode to a lower p concentration towards the cathode. By grading the doping in this way, an increase in absorption is achieved, improving the responsivity of the device. Although this doping increases the capacitance relative to an intrinsic semiconductor of the same thickness, the pseudo electric field that is created by the graded doping gives the electrons a very high velocity which more than compensates for this increased capacitance.

Abstract: A microelectronic device includes a substrate, and a patterned feature located over the substrate and a plurality of doped regions, wherein the patterned feature includes at least one electrode. The microelectronic device includes at least one sill region for the enhancement of electron and/or hole mobility.

Abstract: A method of manufacturing a semiconductor device having a connection terminal and a substrate on which a circuit section and an electrode are stacked in this order, the circuit section having a multilayer interconnect structure, the electrode being conductively connected to the circuit section, and the connection terminal penetrating the substrate and being conductively connected to the electrode. Part of the connection terminal is formed simultaneously with an interconnect in an interconnect layer of the circuit section.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: According to the present invention, there is a provided a semiconductor device having, a collector contact layer made of an n-type GaAs layer; a first collector layer formed on the collector contact layer and made of an n-type GaAs layer; a second collector layer formed on the first collector layer and made of a p-type GaAs layer; a third collector layer formed on the second collector layer and made of an n-type InGaP layer; a fourth collector layer formed on the third collector layer and made of an n-type InGaP layer having an impurity concentration higher than that of the third collector layer; a fifth collector layer formed on the fourth collector layer and made of an n-type GaAs layer; a base layer formed on the fifth collector layer and made of a p-type GaAs layer; and an emitter layer formed on the base layer and made of an n-type InGaP layer.

Abstract: This invention provides a double hetero-junction bipolar transistor (DHBT) in which a probability of the impact ionization at the interface between the base and the collector is reduced, thereby enhancing the break down voltage. In the present DHBT, a plurality of transition layers is inserted between the base layer and the collector layer. Each transition layers has an energy band gap gradually increasing from the base to the collector, and comprises a doped layer close to the base and an un-doped layer. Transition layers thus configured may bring both characteristics of the high break down voltage by the reduction of the average doping concentration and the capability of the high-speed operation by the reduction of the junction capacitance.

Abstract: A metamorphic device including a substrate structure upon which a semiconductor device can be formed. In the metamorphic device, a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading layer which grades past the desired lattice constant is configured at a low temperature. A reverse grading layer grades the lattice constant back to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in at least the grading layer and the reverse grading layer. Thereon a strained layer superlattice is created upon which a high-speed photodiode or other semiconductor device can be formed.

Abstract: A heterojunction bipolar transistor (HBT) with improved characteristics is provided. A III–V compound semiconductor having Bi added thereto is used for a base layer of a GaAs-based or InP-based HBT. For example, a GaAs-based HBT is formed by successively stacking a subcollector layer made of n+-GaAs, a collector layer made of n?-GaAs, a base layer made of p+-GaAsBi, an emitter layer made of n-InGaP, a first cap layer made of n-GaAs, and a second cap layer made of n+-InGaAs on a substrate 1 made of single crystal GaAs.

Abstract: A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.

Abstract: A semiconductor device and its manufacturing method. The semiconductor device has a semi-insulating GaAs substrate 310, a GaAs buffer layer 321 that is formed on the semi-insulating GaAs substrate 310, AlGaAs buffer layer 322, a channel layer 323, a spacer layer 324, a carrier supply layer 325, a spacer layer 326, a Schottky layer 327 composed of an undoped In0.48Ga0.52P material, and an n+-type GaAs cap layer 328. A gate electrode 330 is formed on the Schottky layer 327, and is composed of LaB6 and has a Schottky contact with the Schottky layer 327, and ohmic electrodes 340 are formed on the n+-type GaAs cap layer 328.

Abstract: The invention includes providing gallium nitride materials including thermally conductive regions and methods to form such materials. The gallium nitride materials may be used to form semiconductor devices. The thermally conductive regions may include heat spreading layers and heat sinks. Heat spreading layers distribute beat generated during device operation over relatively large areas to prevent excessive localized heating. Heat sinks typically are formed at either the backside or topside of the device and facilitate heat dissipation to the environment. It may be preferable for devices to include a heat spreading layer which is connected to a heat sink at the backside of the device. A variety of semiconductor devices may utilize features of the invention including devices on silicon substrates and devices which generate large amounts of heat such as power transistors.

Abstract: New pseudomorphic high electron mobility transistors (pHEMT's) with extremely high device linearity having an n+/p+/n camel-gate heterostructure and ?-doped sheet structure is disclosed. For the example of InGaP/InGaAs/GaAs ?-doped pHEMT's with an n+-GaAs/p+-InGaP/n-InGaP camel-gate structure, due to the p-n depletion from p+-InGaP gate to channel region and the presence of large conduction band discontinuity (?Ec) at InGaP/InGaAs heterostructure, the turn-on voltage of gate is larger than 1.7 V. Attributed to the applied gate voltage partly lying on the camel gate and influence of the carrier modulation, the change of total depletion thickness under gate bias is relatively small, and high drain current and linear transconductance can be achieved, simultaneously. The excellent device performances provide a promise for linear and large signal amplifiers and high-frequency circuit applications.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: A growth plane of substrate 1 is processed to have a concavo-convex surface. The bottom of the concave part may be masked. When a crystal is grown by vapor phase growth using this substrate, an ingredient gas does not sufficiently reach the inside of a concave part 12, and therefore, a crystal growth occurs only from an upper part of a convex part 11. As shown in FIG. 1(b), therefore, a crystal unit 20 occurs when the crystal growth is started, and as the crystal growth proceeds, films grown in the lateral direction from the upper part of the convex part 11 as a starting point are connected to cover the concavo-convex surface of the substrate 1, leaving a cavity 13 in the concave part, as shown in FIG. 1(c), thereby giving a crystal layer 2, whereby the semiconductor base of the present invention is obtained. In this case, the part grown in the lateral direction, or the upper part of the concave part 12 has a low dislocation region and the crystal layer prepared has high quality.

Abstract: Very fast integrated OPL circuits, such as pseudo-NMOS OPL and dynamic OPL, comprising CMOS gate arrays having ultra-thin vertical NMOS transistors are disclosed. The ultra-thin vertical NMOS transistors of the CMOS gate arrays are formed with relaxed silicon germanium (SiGe) body regions with graded germanium content and strained silicon channels.

Abstract: A highly reflecting back illuminated diode structure allows light that has not been absorbed by a semiconductor absorbing region to be back reflected for at least a second pass into the absorbing region. The diode structure in a preferred embodiment provides a highly reflecting layer of gold to be supported in part by a conducting alloyed electrode ring contact and in part by a passivation layer of SixNy. Conveniently this structure provides a window within the contact which allows light to pass between the absorbing region and the reflecting layer of gold.

Abstract: GaAs substrates with compositionally graded buffer layers for matching lattice constants with high-Indium semiconductor materials such as quantum well infrared photoconductor devices and thermo photo voltaic devices are disclosed.

Abstract: This invention provides a hetero-junction bipolar transistor (HBT) in which both a base resistance and a base-collector parasitic capacitance are decreased. The HBT has a collector (C) 18, a base (B) 20 and an emitter (E) 26. The collector comprises an outer collector region and an inner collector region, a thickness of the outer collector region is greater than that of the inner region. The base comprises an intrinsic region and an extrinsic region on the outer collector region, while the intrinsic base disposed on the inner collector region. The emitter is disposed on both the intrinsic base and the extrinsic base, and has a band gap energy greater than that of the base.

Abstract: The present invention provides a Hetero-Bipolar Transistor that suppresses a recombination current between electrons in the conduction band of an emitter and holes in the valence band of a base, which results on an enhancement of the current gain of the transistor. The HBT according to the present invention comprises a semi-insulating semiconductor substrate and a series of semiconductor layers on the substrate. The semiconductor layers are a buffer layer, a sub-collector layer a collector layer, a base layer, an emitter layer, an emitter contact layer, and an intermediate layer between the emitter layer and the emitter contact layer. The emitter layer has a carrier concentation of 1.0×1019 cm?3.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: An organic electroluminescent display in which a black matrix with a concentration gradient of a transparent material and a metallic material is formed on the same surface as a pixel electrode. The black matrix and a pixel electrode of the organic electroluminescent display are formed using only one masking operation. The black matrix has a concentration gradient of a continuous gradient structure in which constituents of the transparent material are continuously decreased while constituents of the metallic material are continuously increased as a thickness of the black matrix is increased, a step gradient structure in which the constituents of the transparent material are gradually decreased while the constituents of the metallic material are gradually increased as the thickness of the black matrix is increased, or a multi-gradient structure in which the continuous gradient structure and/or the step gradient structure are repeated.

Abstract: An optical semiconductor device with a multiple quantum well structure, is set out in which well layers and barrier layers, comprising various types of semiconductor layers, are alternately layered. The device well layers comprise a first composition based on a nitride semiconductor material with a first electron energy. The barrier layers comprise a second composition of a nitride semiconductor material with electron energy which is higher in comparison to the first electron energy. The well and barrier layers are in the direction of growth, by a radiation-active quatum well layer which with the essentially non-radiating well layers (6a) and the barrier layers (6b), arranged in front, form a supperlattice.

Abstract: A Group III nitride based high electron mobility transistors (HEMT) is disclosed that provides improved high frequency performance. One embodiment of the HEMT comprises a GaN buffer layer, with an AlyGa1?yN (y=1 or y 1) layer on the GaN buffer layer. An AlxGa1?xN (0?x?0.5) barrier layer on to the AlyGa1?yN layer, opposite the GaN buffer layer, AlyGa1?yN layer having a higher Al concentration than that of the AlxGa1?xN barrier layer. A preferred AlyGa1?yN layer has y=1 or y˜1 and a preferred AlxGa1?xN barrier layer has 0?x?0.5. A 2DEG forms at the interface between the GaN buffer layer and the AlyGa1?yN layer. Respective source, drain and gate contacts are formed on the AlxGa1?xN barrier layer. The HEMT can also comprising a substrate adjacent to the buffer layer, opposite the AlyGa1?yN layer and a nucleation layer between the AlxGa1?xN buffer layer and the substrate.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: A semiconductor light detecting device has a light absorbing layer; and a pn junction, carriers generated by the light absorbing layer absorbing the light in a light detecting region being detected as a photoelectric current through a depletion layer provided by applying a backward voltage to the pn junction, wherein the light detecting region in the light absorbing layer is all depleted in a slate where an operating voltage is applied.

Abstract: A unipolar photodiode and methods of making and using employ a Schottky contact as a cathode contact. The Schottky cathode contact is created directly on a carrier traveling or collector layer of the unipolar photodiode resulting in a simpler overall structure to use and make. The unipolar photodiode comprises a light absorption layer, the collector layer adjacent to the light absorption layer, the Schottky cathode contact in direct contact with the collector layer, and an anode contact either directly or indirectly interfaced to the light absorption layer. The light absorption layer has a doping concentration that is greater than a doping concentration of the collector layer. The light absorption layer has a band gap energy that is less than that of the collector layer. The light absorption layer and the collector layer may be of the same or opposite conduction type.

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract: A light-emitting thyristor having an improved luminous efficiency is provided. According to the light-emitting thyristor, a p-type AlGaAs layer and an n-type AlGaAs layer are alternately stacked to form a pnpn structure on a GaAs buffer layer formed on a GaAs substrate, and Al composition of the AlGaAs layer just above the GaAs buffer layer is increased in steps or continuously.

Abstract: In a distributed feedback type semiconductor layer diode including a semiconductor substrate, an optical guide layer formed on the semiconductor substrate, a diffraction grating having a phase shift region being formed between the semiconductor substrate and the optical guide layer, and an active layer formed on the optical guide layer, &kgr;L+A·&Dgr;&lgr;≧B where &kgr; is a coupling coefficient of the diffraction grating, L is a cavity length of the diode, &Dgr;&lgr; is a detuning amount denoted by &Dgr;&lgr;=&lgr;g−&lgr; where &lgr;g is a gain peak wavelength of the diode and &lgr; is an oscillation wavelength of the diode, A is a constant from 0.04 nm−1 to 0.06 nm−1, and B is a constant from 3.0 to 5.0.

Abstract: A semiconductor structure is provided having a III-V substrate, a buffer layer over the substrate, such buffer layer having a compositional graded quaternary lower portion and a compositional graded ternary upper portion. In one embodiment, the lower portion of the buffer layer is compositional graded AlGaInAs and the upper portion is compositional graded AlInAs.

Abstract: InP heterojunction bipolar transistors having a base layer of InGaAs which are compositionally graded to engineer the bandgap of the base layer to be larger at the emitter/base junction than at the collector/base junction. The graded bandgap can increase DC current gain and speed of the device. A metalorganic chemical vapor deposition method of preparing InP heterojunction bipolar transistors having a base layer with a relatively high concentration of carbon dopant. The high carbon dopant concentration lowers the base sheet resistivity and turn-on voltage of the device.

Abstract: A bipolar heterojunction transistor (HBT) includes a collector layer, a base layer formed on the collector layer, a first transition layer formed on the base layer, an emitter layer formed on the first transition layer, a second transition layer formed on the emitter layer, and an emitter cap layer formed on the second transition layer. Each of the first and second transition layers is formed of a composition that contains an element, the mole fraction of which is graded in such a manner that the conduction band of the HBT is continuous through the base layer, the first and second transition layers, the emitter layer and the emitter cap layer.

Abstract: There is provided a compound semiconductor device that comprises a substrate formed of a first compound semiconductor, a graded channel layer formed on the substrate and formed of a second compound semiconductor layer, that lowers mostly an energy band gap in its inside by continuously changing a mixed-crystal ratio in a thickness direction such that a peak of the mixed-crystal ratio of one constituent element is positioned in its inside, and containing an impurity, a barrier layer formed on the graded channel layer, a gate electrode formed on the barrier layer, and source/drain electrodes for flowing a current into the graded channel layer. Accordingly, the compound semiconductor device having MESFET, that has the maximum mutual conductance and can make the change in the mutual conductance gentle in response to the gate voltage, can be obtained.

Abstract: The heterojunction transistor comprises III-V semiconductor materials with a broad forbidden band material and a narrow forbidden band material. The narrow forbidden band material is an III-V compound containing gallium as one of its III elements and both arsenic and nitrogen as V elements, the nitrogen content being less than about 5%, and the narrow forbidden band material includes at least a fourth III or V element. Adding this fourth element makes it possible to adjust the width of the forbidden band, the conduction band discontinuity &Dgr;Ec, and the valance band discontinuity &Dgr;Ev of the heterojunction. The invention is applicable to making field effect transistors of the HEMT type having a very small forbidden band, and thus having high drain current. It also applies to making heterojunction bipolar transistors of small VBE, and thus capable of operating with power supply voltages that are very low.

Abstract: This invention provides a double hetero-junction bipolar transistor (DHBT) in which a probability of the impact ionization at the interface between the base and the collector is reduced, thereby enhancing the break down voltage. In the present DHBT, a plurality of transition layers is inserted between the base layer and the collector layer. Each transition layers has an energy band gap gradually increasing from the base to the collector, and comprises a doped layer close to the base and an un-doped layer. Transition layers thus configured may bring both characteristics of the high break down voltage by the reduction of the average doping concentration and the capability of the high-speed operation by the reduction of the junction capacitance.

Abstract: A silicon-germanium bipolar transistor includes a silicon substrate in which a first n-doped emitter region, a second p-doped base region adjoining the latter and a third n-doped collector region adjoining the latter, are formed. A first space charge zone is formed between the emitter region and the base region and a second space charge zone is formed between the base region and the collector region. The base region and an edge zone of the adjoining emitter region are alloyed with germanium. The germanium concentration in the emitter region rises toward the base region. The germanium concentration in a junction region containing the first space charge zone rises less sharply than in the emitter region or decreases and, in the base region, it initially again rises more sharply than in the junction region.

Abstract: The present invention provides a highly doped semiconductor layer. More specifically, the present invention provides a semiconductor layer that includes at least two impurities. Each impurity is introduced at a level below its respective degradation concentration. In this manner, the two or more impurities provide an additive conductivity to the semiconductor layer at a level above the conductivity possible with any one of the impurities alone, due to the detrimental effects that would be created by increasing the concentration of any one impurity beyond its degradation concentration.

Abstract: A high performance SiGe HBT that has a SiGe layer with a peak Ge concentration of at least approximately 20% and a boron-doped base region formed therein having a thickness. The base region includes diffusion-limiting impurities substantially throughout its thickness, at a peak concentration below that of boron in the base region. Both the base region and the diffusion-limiting impurities are positioned relative to a peak concentration of Ge in the SiGe layer so as to optimize both performance and yield.

Abstract: There is provided a MQB layer as a multi-quantum barrier portion composed of well layers and barrier layers that are formed of extremely thin films having different compositions and alternately stacked. This enhances an effective barrier height by using the phenomenon that holes likely to flow from a SiGe base layer to a Si emitter layer are reflected by the MQB layer and thereby suppresses the reverse injection of the holes from the SiGe base layer into the Si emitter layer. As a result, the reverse injection of carriers is suppressed by the MQB layer even when the base doping concentration is increased, which provides a satisfactory current amplification factor and increases a maximum oscillation frequency. What results is a bipolar transistor having excellent RF characteristics such as current amplification factor, current gain cutoff frequency, and maximum oscillation frequency in a microwave band or the like.

Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

Abstract: A SiGe-HBT is provided with a SiGe film and a Si film grown in succession by epitaxial growth. The SiGe film is made up of a SiGe buffer layer, a SiGe graded composition layer, and a SiGe upper layer, in which the Ge content is substantially constant or changes not more than that of the SiGe graded composition layer. Even if there are fluctuations in the position of the EB junction, the EB junction is positioned in a portion of the SiGe upper layer, so fluctuations in the Ge content in the EB junction can be inhibited, and a stable high current amplification factor can be obtained. It is also possible to provide a SiGeC film instead of the SiGe film.

Abstract: A light emitting device employing gallium nitride type compound semiconductor which generates no crystal defect, dislocation and can be separated easily to chips by cleavage and a method for producing the same are provided. As a substrate on which gallium nitride type compound semiconductor, layers are stacked, a gallium nitride type compound semiconductor substrate, a single-crystal silicon, a group II-VI compound semiconductor substrate, or a group III-V compound semiconductur substrate is employed.

Abstract: The present invention provides a varactor diode for frequency multipliers at submillimeter wave frequencies and above. Functionally the new diode replaces the conventional heterostructure barrier varactor diode. Two important features of the antimony-based quantum well heterostructure barrier varactor are; first: an aluminum antimnide/aluminum-arsenic-antimnide heterostructure barrier and second: a bandgap-engineered, triangular quantum well cathode and anode.

Abstract: A Double Heterojunction Bipolar Transistor (DHBT) is disclosed employing a collector of InP, an emitter of InP or other material such as InAlAs, and a base of either a selected InxGa1−xAsySb1−y compound, which preferably is lattice-matched to InP or may be somewhat compressively strained thereto, or of a superlattice which mimics the selected InGaAsSb compound. When an emitter having a conduction band non-aligned with that of the base is used, such as InAlAs, the base-emitter junction is preferably graded using either continuous or stepped changes in bulk material, or using a chirped superlattice. Doping of the junction may include one or more delta doping layer to improve the shift of conduction band discontinuities provided by a grading layer, or to permit a wider depletion region.

Abstract: A silicon germanium heterojunction bipolar transistor device having a semiconductor region, and a diffusion region in the semiconductor region, wherein the diffusion region is boron-doped, wherein the semiconductor region comprises a carbon dopant therein to minimize boron diffusion, and wherein a combination of an amount of the dopant, an amount of the boron, and a size of the semiconductor region are such that the diffusion region has a sheet resistance of less than approximately 4 Kohms/cm2. Also, the diffusion region is boron-doped at a concentration of 1×1020/cm3 to 1×1021/cm3. Additionally, the semiconductor region comprises 5-25% germanium and 0-3% carbon. By adding carbon to the semiconductor region, the device achieves an electrostatic discharge robustness, which further causes a tighter distribution of a power-to-failure of the device, and increases a critical thickness and reduces the thermal strain of the semiconductor region.

Abstract: A semiconductor layer is co-doped with two dopants. The first dopant is to generate charge carriers in the semiconductor material, and the second dopant is to promote atomic disorder within the material. When the semiconductor material is annealed, the second dopant becomes mobile and moves through the lattice so as to promote atomic disorder. This eliminates unwanted effects such as, for example, a reduction in the forbidden bandgap that can otherwise arise as a result of atomic ordering. The amount of diffusion of the second dopant during the annealing can be increased by making the initial concentration of the second dopant non-uniform over the volume of the semiconductor material.