Abstract: A highly reflecting back illuminated diode structure allows light that has not been absorbed by a semiconductor absorbing region to be back reflected for at least a second pass into the absorbing region. The diode structure in a preferred embodiment provides a highly reflecting layer of gold to be supported in part by a conducting alloyed electrode ring contact and in part by a passivation layer of SixNy. Conveniently this structure provides a window within the contact which allows light to pass between the absorbing region and the reflecting layer of gold.

Abstract: The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, among others.

Abstract: Conventional CMOS devices suffer from imbalance because the mobility of holes in the PMOS transistor is less than the mobility of electrons in the NMOS transistor. The use of strained silicon in the channels of CMOS devices further exacerbates the difference in electron and hole mobility, as strained silicon provides a greater increase in electron mobility than hole mobility. However, hole mobility is increased in the SiGe layer underlying the strained silicon layer. Therefore, a more evenly-balanced, high-speed CMOS device is formed by including strained silicon in the NMOS transistor and not in the PMOS transistor of a CMOS device.

Abstract: A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collector voltage. It also has less variation than conventional bipolar transistors for the collector current while ensuring high speed properties and high gain. In one example, the band gap in the base region is smaller than the band gap in the emitter and collector regions. The band gap is constant near the junction with the emitter region and decreases toward the junction with the collector region. A single crystal silicon/germanium is a typically used for the base region.

Abstract: In a distributed feedback type semiconductor layer diode including a semiconductor substrate, an optical guide layer formed on the semiconductor substrate, a diffraction grating having a phase shift region being formed between the semiconductor substrate and the optical guide layer, and an active layer formed on the optical guide layer,

Abstract: A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supply can be ion implanted in either the SiGe cap layer or the relaxed SiGe layer. In another embodiment, there is provided a method of fabricating a circuit including providing at least one strained channel, enhancement mode FET, and at least one strained channel, depletion mode FET on a substrate, and ion implanting a dopant supply in the depletion mode FET.

Abstract: A method of manufacturing a semiconductor device which includes forming a first SiGe layer having a low content of Ge, forming an oxide layer by implanting oxygen ions into the first SiGe layer, and then annealing the first SiGe layer. The method also includes forming, on the first SiGe layer, a second SiGe layer which has a higher content of Ge than the first SiGe layer, forming a strained Si layer on the second SiGe layer, and forming a field effect transistor in which the strained Si layer is used a channel region. Further, a field effect transistor may be formed on a semiconductor substrate having an indefectible, high-quality, buried oxide layer and a largely strained Si layer, and hence a high-speed, low-power-consumption semiconductor device can be realized.

Abstract: A quantum well optoelectronic device exploiting the multistability of the light-current characteristic of a multiple quantum well structure to achieve complex manipulation of the optical output of a light-emitting channel. Intraband tunneling of each of two distinct carrier types gives rise to a nonlinear dependence of optical gain on injected current.

Abstract: In the manufacture of a semiconductor laser device, sequentially grown on a sapphire substrate in the following order are a buffer layer, a first undoped GaN layer, a first super lattice defect reducing layer, a second undoped GaN layer, a second super lattice defect reducing layer, a third undoped GaN layer, a third super lattice defect reducing layer and a fourth undoped GaN layer. A device structure is then formed thereon. The first to third super lattice defect reducing layers each include five pairs of InGaN and AlGaN films alternately placed on one another in this order.

Abstract: An n-GaN layer is provided as an emitter layer for supplying electrons. A non-doped (intrinsic) AlxGa1−xN layer (0≦x≦1) having a compositionally graded Al content ratio x is provided as an electron transfer layer for transferring electrons toward the surface. A non-doped AlN layer having a negative electron affinity (NEA) is provided as a surface layer. Above the AlN layer, a control electrode and a collecting electrode are provided. An insulating layer formed of a material having a larger electron affinity than that of the AlN layer is interposed between the control electrode and the collecting electrode. This provides a junction transistor which allows electrons injected from the AlN layer to conduct through the conduction band of the insulating layer and then reach the collecting electrode.

Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis. The quantum dot layer is preferably comprised of AlxByInzGa1-x-y-zN, InGaN1-a-bPaAsb, or AlxByInzGa1-x-y-zN1-a-bPaAsb.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) with

Abstract: A Group-III nitride semiconductor light-emitting diode having an electrically conducting silicon (Si) single crystal substrate having on an upper surface thereof at least a light-emitting part having a pn-heterojunction structure composed of a Group-III nitride semiconductor, which light-emitting part is stacked via an intermediate layer composed of a metal or a semiconductor, the single crystal substrate having a back surface electrode on a back surface thereof, a surface electrode on an upper surface of the light-emitting part and a perforated part formed by eliminating the Si single crystal substrate in a region exclusive of the back surface electrode on the back surface of the single crystal substrate and a method of manufacturing thereof are disclosed.

Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein surfaces of the buffer layer are c facets of Ga atoms; a separating layer including (InXAl1-X)YGa1-YN (where 0≦X≦1, 0≦Y≦1) formed on the buffer layer, wherein surfaces of the separating layer are c facets of In, Al, or Ga atoms; a channel layer including GaN, InGaN, or a combination of GaN and InGaN formed on the separating layer, wherein surfaces of the channel layer are c facets of Ga or In atoms; and an electron supply layer including AlGaN formed on the channel layer, wherein surfaces of the electron supply layer are c facets of Al or Ga atoms, wherein the AlN composition ratio in the separating layer is smaller than the AlN composition ratio in the electron supply layer.

Abstract: A semiconductor power component has a MOS structure in which the source region is formed of a material whose band gap is smaller than the band gap of the material of the channel region. This measure reduces the gain of a parasitic bipolar transistor.

Abstract: A semiconductor substrate, a field effect transistor, a method of forming a SiGe layer and a method of forming a strained Si layer using the same, and a method of manufacturing a field effect transistor are provided, which enable the threading dislocation density of the SiGe layer to be reduced and the surface roughness to be minimized. On top of a Si substrate 1 is provided a SiGe buffer layer 2, 12 constructed of a plurality of laminated layers comprising alternating layers of a SiGe gradient composition layer 2a, 12a in which the Ge composition ratio increases gradually from the Ge composition ratio of the base material, and a SiGe constant composition layer 2b, 12b which is provided on top of the gradient composition layer and in which the Ge composition ratio is equal to that of the upper surface of the gradient composition layer.

Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.

Abstract: InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.

Abstract: According to this invention, a group III nitride inverted high electron mobility transistor, and a power amplifier using the same are provided. A transistor and power amplifier according to this invention are characterized in that the lattice constant of a bulk of a donor layer is larger than that of an underlayer containing a group III nitride compound semiconductor material, or the donor layer is made of impurity-doped AlyGa(1−y)N, the underlayer is made of undoped AlxGa(1−x)N, and x and y satisfy an inequality 0≦y<x≦1.

Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.

Abstract: A semiconductor device is constituted by a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. The second layer B has wider band gap than the first layer W. Each thickness of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of wavelength of quantum-wave of carriers in each of the first layer W and the second layer B existing around the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. The quantum-wave interference layer functions as a reflecting layer of carriers for higher reflectivity.

Abstract: A semiconductor layer is co-doped with two dopants. The first dopant is to generate charge carriers in the semiconductor material, and the second dopant is to promote atomic disorder within the material. When the semiconductor material is annealed, the second dopant becomes mobile and moves through the lattice so as to promote atomic disorder. This eliminates unwanted effects such as, for example, a reduction in the forbidden bandgap that can otherwise arise as a result of atomic ordering. The amount of diffusion of the second dopant during the annealing can be increased by making the initial concentration of the second dopant non-uniform over the volume of the semiconductor material.

Abstract: Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography. In accordance with one embodiment of the invention, there is provided a semiconductor structure including a planarized relaxed Si1−xGex layer on a substrate; and a device heterostructure deposited on said planarized relaxed Si1−xGex layer including at least one strained layer.

Abstract: A semiconductor layer is co-doped with two dopants. The first dopant is to generate charge carriers in the semiconductor material, and the second dopant is to promote atomic disorder within the material. When the semiconductor material is annealed, the second dopant becomes mobile and moves through the lattice so as to promote atomic disorder. This eliminates unwanted effects such as, for example, a reduction in the forbidden bandgap that can otherwise arise as a result of atomic ordering. The amount of diffusion of the second dopant during the annealing can be increased by making the initial concentration of the second dopant non-uniform over the volume of the semiconductor material.

Abstract: The field effect device consisting of a substrate, a conducting backplane formed in the substrate, a source and a drain disposed above the conductive backplane, a gate insultatively disposed above the substrate between the source and drain, and a backgate contact electrically coupled to the conducting backplane.

Abstract: A heterojunction bipolar transistor having a ballast resistance layer between an AlGaAs emitter layer and an emitter electrode, wherein the ballast resistance layer comprises n-AlxGa1−XAs, wherein 0<X<1, and a GaAs selective etching layer is provided between the emitter layer and the ballast resistance layer.

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer bandedge is at least kBT higher than the Fermi level of the semiconductor layer, which allows only selected, “hot” electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Abstract: There is provided a semiconductor light emitting device having improved adhesion of an electrode by reducing defects in a crystal surface. An n-type AlGaInP lower clad layer 12, an AlGaInP active layer 13, a p-type AlGaInP upper clad layer 14, a p-type AlGaInP intermediate layer 15 whose lattice matching rate &Dgr;a/a with GaAs is −3.3%, a p-type AlGaInP current diffusion layer 16 and a p-type electrode 17 are laminated on an n-type GaAs substrate 11 and an n-type electrode 18 is provided on the n-type GaAs substrate 11. Thus, the number of crystal defects in the crystal surface can be reduced to 20 or less per one LED by setting the value of the lattice matching rate &Dgr;a/a of the intermediate layer 15 to be −3.3%, which is lower than −2.5%. As a result, adhesion of the p-type electrode 17 formed on the current diffusion layer 16 is improved and thereby the yield of LED can be enhanced.

Abstract: A hetero junction bipolar transistor has an emitter region, a base region, a collector region and a subcollector region which are serially arranged. The collector region includes a plurality of sub-regions. An energy bandgap in each of the sub-regions is constant or linearly changes, and an energy band edge where mobile charge carriers run in the collector region is continuous at each boundary between the sub-regions. Two-dimensional or quasi-two-dimensional charge layer is formed at the boundary of the sub-regions so as to compensate quasi-electric field caused by differences in electron affinity and energy bandgap between the sub-regions. The mobile charge carriers pass through the collector region from the base region without encountering barriers and thereby this heterojunction bipolar transistor achieves a high operating efficiency.

Abstract: The light emitting diode includes an intermediate layer made of non-single crystalline material between single crystalline layers. By the intermediate layer, the boundary characteristic between the single crystalline layers may be improved and the defect caused by the lattice mismatch can be decreased, so that the brightness and forward voltage characteristics can be improved.

Abstract: A solid-state wavelength demultiplexer comprising a plurality of photosensitive elements wherein each element has certain energy gap defined by the material composition. All photosensitive elements are grown on a common substrate where the first grown buffer layer, adjacent and near lattice matched to the first bottom photosensitive element, is heavily doped. A composition of photosensitive elements varies from the first bottom photosensitive element up to a first top photosensitive layer in such a way that corresponding energy gap has a minimum value in the lowermost element while the maximum value in the uppermost element. A wide gap doped “window” layer is grown on top of the uppermost element. Each individual photosensitive element consists of at least three sublayers comprising a first doped sublayer, a second heavily doped sublayer, and a photosensitive undoped sublayer sandwiched between them.

Abstract: An integrated optoelectronic circuit chip for optical data communication systems includes a silicon substrate, at least one MOS field effect transistor (MOSFET) formed on a portion of the silicon substrate, and an avalanche photodetector operatively responsive to an incident optical signal and formed on another portion of the substrate. The avalanche photodetector includes a light absorbing region extending from a top surface of the silicon substrate to a depth h and doped to a first conductivity type. The light absorbing region is ionizable by the incident optical signal to form freed charge carriers in the light absorbing region. A light responsive region is formed in the light absorbing region and extends from the top surface of the silicon substrate to a depth of less than h. The light responsive region is doped to a second conductivity type of opposite polarity to the first conductivity type.

Abstract: In an electron-emitting device, an electron supplying layer for supplying electrons is composed of an n-GaN layer. An electron transferring layer for moving electrons toward the surface is composed of non-doped (intrinsic) AlxGa1−xN (0≦x≦1) having a graded composition for the Al concentration x. A surface layer is composed of non-doped AlN having a negative electron affinity (NEA). The electron transferring layer composed of AlxGa1−xN has a band gap which is enlarged nearly continuously from the electron supplying layer to the surface layer and a negative electron affinity or a positive electron affinity close to zero. If such a voltage V as to render the surface electrode side positive is applied, the band of AlxGa1−xN is bent, whereby a current derived mainly from a diffused current flows from the electron supplying layer to the surface layer through the electron transferring layer. Thereby excellent electron emitting characteristic is obtained.

Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

Abstract: A semiconductor photodetection device includes a photodetection layer formed of an alternate and repetitive stacking of an optical absorption layer accumulating therein a compressive strain and a stress-compensating layer accumulating therein a compensating tensile strain, wherein the optical absorption layer has a thickness larger than a thickness of the stress-compensating layer.

Abstract: Semiconductor structures and a method of forming semiconductor structures The avalanche breakdown characteristics, such as breakdown voltage and impact ionisation coefficient, of a semiconductor structure can be controlled by controlling the Brillouin-zone-averaged energy bandgap (<Ec>) of the material forming the structure. Consequently, the avalanche breakdown characteristics of a device may be tailored independently of the bandgap Eg. The Brillouin-zone-averaged energy bandgap (<Ec>) may be controlled by controlling the composition of the semiconductor used or by straining its lattice.

Abstract: A heterostructure thermionic cooler and a method for making thermionic coolers, employing a barrier layer of varying conduction bandedge for n-type material, or varying valence bandedge for p-type material, that is placed between two layers of material. The barrier layer has a high enough barrier for the cold side to only allow “hot” electrons, or electrons of high enough energy, across the barrier. The barrier layer is constructed to have an internal electric field such that the electrons that make it over the initial barrier are assisted in travel to the anode. Once electrons drop to the energy level of the anode, they lose energy to the lattice, thus heating the lattice at the anode. The barrier height of the barrier layer is high enough to prevent the electrons from traveling in the reverse direction.

Abstract: InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.

Abstract: A field effect transistor such as a flash EEPROM device has channel region between a source region and a drain region with the channel region including a silicon germanium alloy layer epitaxially grown on a silicon substrate and a silicon cap layer epitaxially grown on the alloy layer. A floating gate is provided over and insulated from the channel region, and a control gate is provided over and insulated from the floating gate. The silicon germanium alloy layer and cap silicon layer provide for enhanced secondary impact ionization when injecting electrons from the channel region into the floating gate in programming the device. In a preferred embodiment the SiGe alloy layer is graded with the germanium mole fraction increasing from zero to some maximum value in the growth direction and with the germanium layer thickness being below a critical thickness for maintaining pseudomorphic strain.

Abstract: A vertical channel flash memory cell with a silicon germanium layer in the channel region provides enhanced secondary electron injection when programming the device. The device includes a silicon substrate, a silicon germanium alloy layer epitaxially grown on the substrate, and a silicon layer epitaxially grown on the silicon germanium layer. A sidewall through the stacked structure is formed by etching thereby exposing edges of the silicon layer and the silicon germanium layer and a portion of the substrate. A floating gate is formed overlying the sidewall and insulated therefrom with a control gate overlying the floating gate and insulated therefrom. A source region is formed in the silicon layer and a drain region is formed in the substrate with a channel therebetween along the sidewall and including the silicon germanium layer. The silicon germanium layer is preferably compressively strained and can have a uniform mole fraction or a graded mole fraction.

Abstract: In the manufacture of a semiconductor laser device, sequentially grown on a sapphire substrate in the following order are a buffer layer, a first undoped GaN layer, a first super lattice defect reducing layer, a second undoped GaN layer, a second super lattice defect reducing layer, a third undoped GaN layer, a third super lattice defect reducing layer and a fourth undoped GaN layer. A device structure is then formed thereon. The first to third super lattice defect reducing layers each include five pairs of InGaN and AlGaN films alternately placed on one another in this order.

Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.

Abstract: A low-bandgap, double-heterostructure PV device is provided, including in optical alignment a first InP1−yAsy n-layer formed with an n-type dopant, an GaxIn1−xAs absorber layer, the absorber layer having an n-region formed with an n-type dopant and an p-region formed with a p-type dopant to form a single pn-junction, and a second InP1−yAsy p-layer formed with a p-type dopant, wherein the first and second layers are used for passivation and minority carrier confinement of the absorber layers.

Abstract: The or each strained quantum well layer of a quantum confined Stark effect modulator is provided with a substructure of substructure layers not all having the same lattice constant. The thickness and composition of these substructure layers may be arranged to produce a differential strain that is asymmetric with respect to the mid-plane of the quantum well and so skews the hole wavefunctions for heavy-holes, HH1, and light-holes, LH1, in opposite directions. This enables the choice of composition designed to provide substantial matching of the E1-HH1 and E1-LH1 Stark shifts for one particular polarity of applied field, thereby providing a modulation facility that is substantially polarisation insensitive. Alternatively, the thickness and composition of the layers may be chosen to produce a symmetrical strain profile in which the same effect is provided, but for both polarities of applied field.

Abstract: This invention is a novel silicon carbide and silicon (SiC/Si) heterostructure N-shaped negative-differential-resistance semiconductor switch having low power dissipation and large on/off current ratio. The structure of the semiconductor switch includes Al electrode/p-type single crystal silicon carbide layer/graded-composition layer/n-type single crystal silicon substrate/Al electrode (Al/p-SiC/GCL/n-Si/Al), wherein the graded-composition layer is a buffer layer between the p-SiC and n-Si layers.

Abstract: The present invention provides an epitaxial wafer having compound semiconductor epitaxial layer provided on a substrate, a total thickness of a portion of the compound semiconductor epitaxial layers comprises Ga, As and P as constituent elements being not less than 80 &mgr;m and in the epitaxial layer a low carrier concentration region with a carrier concentration of from 0.5 to 9×1015 cm−3 doped with nitrogen being formed.

Abstract: A Group III-V semiconductor optoelectronic device provides for visible wavelength light output having a more laterally uniform, high power beam profile, albeit still quasi-Gaussian. A number of factors contribute to the enhanced profile including an improvement in reducing band offset of the Group III-V deposited layers improving carrier density through a decrease in the voltage drop require to generate carrier flow; reduction of contaminants in the growth of Group III-V AlGaInP-containing layers with compositional Al, providing for quality material necessary to achieve operation at the desired visible wavelengths; the formation of an optical resonator cavity that provides, in part, weak waveguiding of the propagating light; and the utilization of a mechanism to provide for beam spreading and filing in a beam diverging gain section prior to actively aggressive gain pumping of the propagating light in the device.

Abstract: A reduced 1/f low frequency noise high electron mobility transistor is obned based on the realization that in modulation-doped heterostructure transistors the inherent bandbending in the high bandgap material spacer layer allows certain trap energy levels to cross or approach the Fermi level at or near the 2DEG interface. For the case of AlGaAs/GaAs HEMTs or AlGaAs/InGaAs/GaAs pseudomorphic HEMTs the composition of the spacer layer is graded to provide for the conduction band energy to have a negative slope near the spacer layer/2DEG interface. This bandbending pulls interface trap energy levels away from the Fermi level and significantly reduces f.sub.t (1-f.sub.t) and the spectral density of the 1/f low frequency noise.

Abstract: A family of lasers is provided which can be readily grown upon silicon wafer platforms, each laser having a highly doped stably strained SiGe or Ge collector layer formed upon a SiGe graded relaxed buffer layer in turn grown on the Si wafer, and an intrinsic strain-symmetric Ge--Si superlattice covered by a heavily doped stably strained SiGe emitter. The superlattice has numerous thin 8-15 atomic monolayers of interleaved Ge and Si atoms, enabling high stack heights.

Abstract: Disclosed is an electroabsorption-type optical modulator, which includes a semiconductor substrate; and a semiconductor buffer layer, a semiconductor optical absorption layer and a semiconductor cladding layer which are layered in order on the semiconductor substrate. The absorption of a light wave supplied to an end of the semiconductor optical absorption layer is controlled by changing the intensity of an electric field applied to the semiconductor optical absorption layer. The semiconductor optical absorption layer has a first region with an absorption-edge wave length shorter than that of a second region of the semiconductor optical absorption layer.