Bipolar Transistor Patents (Class 257/197)
  • Patent number: 10923470
    Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 16, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Kazuhito Nakai, Yusuke Tanaka
  • Patent number: 10916642
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 9, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Steven M. Shank, John J. Pekarik
  • Patent number: 10868155
    Abstract: A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara, Shigeki Koya
  • Patent number: 10840236
    Abstract: A semiconductor device includes a sub-collector layer disposed on a substrate, a bipolar transistor including a collector layer formed of a semiconductor having a lower carrier concentration than the sub-collector layer, a base layer, and an emitter layer, and a protection diode including a Schottky electrode. The Schottky electrode forms, in a partial region of an upper surface of the collector layer, a Schottky junction to the collector layer and is connected to one of the base layer and the emitter layer. In the collector layer, a part that forms a junction to the base layer and a part that forms a junction to the Schottky electrode are electrically connected to each other via the collector layer.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 17, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Isao Obu
  • Patent number: 10825812
    Abstract: A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Kanno, Masaharu Yamaji, Hitoshi Sumida
  • Patent number: 10825922
    Abstract: A semiconductor device comprises: an extrinsic base region; a first dielectric spacer on at least a part of a sidewall of the extrinsic base region adjacent to an emitter window region; an intrinsic base region; a base link region coupling the intrinsic base region and the extrinsic base region; a collector region underlying the intrinsic base region and having a periphery underlying the base link region; and a second dielectric spacer, separating the base link region from at least the periphery of the collector region; wherein said second dielectric spacer extends laterally beyond said first dielectric spacer to underlie said emitter window region.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: November 3, 2020
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, James Kirchgessner
  • Patent number: 10818781
    Abstract: Provided is a heterojunction bipolar transistor (HBT) structure with a bandgap graded hole barrier layer, including: a sub-collector layer including an N-type group III-V semiconductor on a substrate, a collector layer on the sub-collector layer and including a group III-V semiconductor, a hole barrier layer on the collector layer, a base layer on the hole barrier layer and including a P-type group III-V semiconductor, an emitter layer on the base layer and including an N-type group III-V semiconductor, an emitter cap layer on the emitter layer and including an N-type group III-V semiconductor, and an ohmic contact layer on the emitter cap layer and including an N-type group III-V semiconductor. Bandgaps of the hole barrier layer at least include a gradually increasing bandgap from the base layer towards the collector layer and a largest bandgap of the hole barrier layer is greater than bandgap of the base layer.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: October 27, 2020
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Chao-Hsing Huang, Yu-Chung Chin, Min-Nan Tseng, Kai-Yu Chen
  • Patent number: 10818772
    Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Pernell Dongmo, Cameron Luce, James W. Adkisson, Qizhi Liu
  • Patent number: 10818782
    Abstract: At a portion at which a gate trench is branched, the trench is formed at a deeper position than at portions of the gate trench having a linear shape. A semiconductor device is provided, including: a first conductivity-type semiconductor substrate; a second conductivity-type base region provided at a front surface side of the semiconductor substrate; a first trench portion provided extending from a front surface of the semiconductor substrate and penetrating the base region; and a second conductivity-type contact region which is provided in a part of the base region at a front surface side of the semiconductor substrate and has a higher impurity concentration than the base region, wherein the first trench portion has a branch portion on the front surface of the semiconductor substrate, and the branch portion is provided being surrounded by the contact region on the front surface of the semiconductor substrate.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 27, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10811452
    Abstract: An image sensing device including a noise blocking structure is disclosed. The image sensing device includes a semiconductor substrate structured to support a plurality of image pixels producing signals upon a detection of an incident light and a logic circuit configured to process signals produced by the image pixels are formed, and a noise blocking structure disposed at the semiconductor substrate and formed to surround the logic circuit is formed. The noise blocking structure includes a first blocking structure and a second blocking structure. The first blocking structure includes multiple portions spaced from one another, each of the multiple portions extending in a line without any bending portion. The second blocking structure are disposed between the multiple portions of the first blocking structure and include portions partially overlapping with the first blocking structure.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 20, 2020
    Assignee: SK hynix Inc.
    Inventors: Ho Young Kwak, Jong Eun Kim
  • Patent number: 10804429
    Abstract: A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: October 13, 2020
    Assignee: Lumileds LLC
    Inventors: Isaac Harshman Wildeson, Parijat Pramil Deb, Robert Armitage
  • Patent number: 10797180
    Abstract: The semiconductor device includes a first insulating layer; a first oxide insulating layer over the first insulating layer; an oxide semiconductor layer over the first oxide insulating layer; a source electrode layer and a drain electrode layer over the oxide semiconductor layer; a second oxide insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer; a gate insulating layer over the second oxide insulating layer; a gate electrode layer over the gate insulating layer; a second insulating layer over the first insulating layer the source electrode layer, the drain electrode layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer, and a third insulating layer over the first insulating layer, the source electrode layer, the drain electrode layer, and the second insulating layer.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: October 6, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Takahisa Ishiyama, Katsuaki Tochibayashi, Kazuya Hanaoka
  • Patent number: 10777648
    Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Seyoung Kim, Injo Ok, Soon-Cheon Seo
  • Patent number: 10741680
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 11, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Patent number: 10706153
    Abstract: An information handling system (IHS) may implement techniques to detect a power-on event, to determine whether an authorized cryptographic erase operation of a storage device that implements cryptographic erasure is pending and, during an initialization sequence, to send to the device in response to determining that no such operation is pending, a command to disable cryptographic erasure on the device. The command may set an indicator on the device that, when set, disables cryptographic erasure. In response to determining that an authorized cryptographic erase operation is pending, the IHS may refrain from sending the command to disable cryptographic erasure on the device, and may send a command to cause the pending operation to be performed. In response to receiving an indication of completion of the pending operation, the IHS may clear an indicator that an authorized cryptographic erase operation is pending and initiate a power-on or reboot event.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 7, 2020
    Assignee: Dell Products L.P.
    Inventors: Mukund Khatri, David Michael Pereira, Chandrashekar Nelogal
  • Patent number: 10707179
    Abstract: A semiconductor structure including a MIM capacitor includes a substrate, a MIM capacitor disposed over the substrate, a first insulating layer disposed over the MIM capacitor, an ONON stack disposed over the first insulating layer, a connecting via disposed in the first insulating layer, and a connecting pad disposed in the ONON stack and in contact with the connecting via. The ONON stack covers sidewalls of the connecting pad and a portion of a top surface of the connecting pad.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Jiun Wu, Yinlung Lu, Mingni Chang, Ming-Yih Wang
  • Patent number: 10707141
    Abstract: First and second electrodes (12,13) are provided on an upper surface of the semiconductor chip (9) and spaced apart from each other. A wiring member (15) includes a first joint (15a) bonded to the first electrode (12) and a second joint (15b) bonded to the second electrode (13). Resin (2) seals the semiconductor chip (9), the first and second electrodes (12,13) and the wiring member (15). A hole (18) extending through the wiring member (15) up and down is provided between the first joint (15a) and the second joint (15b).
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: July 7, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Yoshimatsu, Osamu Usui, Yuji Imoto
  • Patent number: 10707336
    Abstract: High-performance lateral bipolar junction transistors (BJTs) are provided in which a lightly doped upper intrinsic base region is formed between a lower intrinsic base region and an extrinsic base region. The lightly doped upper intrinsic base region provides two electron paths which contribute to the collector current, IC. The presence of the lightly doped upper intrinsic base region increases the total IC and leads to higher current gain, ?, if there is no increase of the base current, IB.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 10665609
    Abstract: The present invention is notably directed to an electro-optical device. The latter comprises a layer structure with: a silicon substrate; a buried oxide layer over the silicon substrate; a tapered silicon waveguide core over the buried oxide layer, the silicon waveguide core cladded by a first cladding structure; a bonding layer over the first cladding structure; and a stack of III-V semiconductor gain materials on the bonding layer, the stack of III-V semiconductor gain materials cladded by a second cladding structure. The layer structure is configured to optically couple radiation between the stack of III-V semiconductor gain materials and the tapered silicon waveguide core. The first cladding structure comprises a material having: a refractive index that is larger than 1.54 for said radiation; and a bandgap, which, in energy units, is larger than an average energy of said radiation.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Utz Herwig Hahn, Marc Seifried
  • Patent number: 10658495
    Abstract: A method of forming a silicon-germanium heterojunction bipolar transistor (hbt) device is provided. The method includes forming a stack of four doped semiconductor layers on a semiconductor substrate. The method further includes forming a dummy emitter contact and contact spacers on a fourth doped semiconductor layer of the stack of four doped semiconductor layers, and removing portions of the second, third, and fourth semiconductor layers to form a vertical fin. The method further includes recessing the second and fourth doped semiconductor layers, and depositing a condensation layer on the second, third, and fourth doped semiconductor layers. The method further includes reacting the condensation layer with the third doped semiconductor layer to form a protective segment on a condensed protruding portion.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: May 19, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Choonghyun Lee, Soon-Cheon Seo, Sungjae Lee
  • Patent number: 10651298
    Abstract: The disclosure provides an HBT structure with bandgap graded hole barrier layer, comprising: a sub-collector layer, a collector layer, a hole barrier layer, a base layer, an emitter layer, an emitter cap layer, and an ohmic contact layer, all stacked sequentially on a substrate; with the hole barrier layer formed of at least one of AlGaAs, AlGaAsN, AlGaAsP, AlGaAsSb, and InAlGaAs, Aluminum composition being less than 22%, and In, N, P, and Sb compositions being respectively less than or equal to 10%; wherein bandgaps of the hole barrier layer at least comprise a gradually increasing bandgap from the base layer towards the collector layer and the largest bandgap of the hole barrier layer is greater than bandgaps of the base layer and the collector layer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: May 12, 2020
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng, Kai-Yu Chen
  • Patent number: 10651269
    Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 12, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Masayuki Miyazaki, Hidenao Kuribayashi
  • Patent number: 10636897
    Abstract: In a bipolar transistor, a collector layer includes three semiconductor layers: an n-type GaAs layer (Si concentration: about 5×1015 cm?3, thickness: about 350 nm), a p-type GaAs layer (C concentration: about 4.5×1015 cm?3, thickness: about 100 nm, sheet concentration: 4.5×1010 cm?2), and an n-type GaAs layer Si concentration: about 5×1015 cm?3, thickness: about 500 nm. The sheet concentration of the p-type GaAs layer is set to less than 1×1011 cm?2.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 28, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Atsushi Kurokawa, Tsunekazu Saimei
  • Patent number: 10636660
    Abstract: To manufacture a super-junction (SJ) layer of a SJ device, an epitaxial (epi) layer having a first conductivity type may be formed on an underlying layer, which may be formed from a wide-bandgap material. A first mask may then be formed onto a first portion of the epi layer, and a first set of SJ pillars may be selectively implanted into a second portion of the epi layer exposed by the first mask. Then, a second mask may be formed on the second portion of the epi layer that is self-aligned relative to the first mask. After removing the first mask, a second set of SJ pillars may be selectively implanted into the first portion of the epi layer. Removing the second mask may then yield the SJ layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 28, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Reza Ghandi, Alexander Viktorovich Bolotnikov, Peter Almern Losee, David Alan Lilienfeld
  • Patent number: 10629591
    Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: April 21, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Kazuhito Nakai, Yusuke Tanaka
  • Patent number: 10622465
    Abstract: A heterojunction bipolar transistor (HBT) may include a base contact and emitter mesas on a collector mesa. The HBT may include emitter contacts on the emitter mesas. The HBT may include a first dielectric layer on the collector mesa, sidewalls of the emitter mesas, and the base contact. The HBT may further include a second dielectric layer on the first dielectric layer and on sidewalls of the emitter contacts. The HBT may further include a secondary conductive layer on the first dielectric layer, the second dielectric layer, and the emitter contacts.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Xia Li, Bin Yang
  • Patent number: 10607913
    Abstract: The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 31, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: HuiLi Fu, Shujie Cai, Feiyu Luo
  • Patent number: 10588097
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine declared antenna gain-related information that corresponds to an estimated actual antenna gain for an antenna, and adjust a parameter of a wireless subsystem based on the declared antenna gain-related information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Ilan Sutskover, Wilfrid D'Angelo, Eran Friedlander, Nadav Kahana, Noam Kogos, Baruch Navon, Leor Rom
  • Patent number: 10580748
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 3, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui
  • Patent number: 10573730
    Abstract: A bipolar transistor is described. In accordance with one aspect of the present invention the bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Claus Dahl, Dmitri Alex Tschumakow
  • Patent number: 10566421
    Abstract: A method for manufacturing a fin-type bipolar semiconductor device includes providing a substrate comprising a first region of a first conductivity type and a second region of a second conductivity type adjacent the first region, etching the substrate to form a third region in the first region, a first set of fins on the third region, a fourth region in the second region, and a second set of fins on the fourth region, performing a first implantation into a first portion of the second set of fins and a corresponding portion of the fourth region to form an emitter region of the first conductivity type, a remaining portion of the fourth region not being doped forming a base region adjacent the emitter region and forming a junction in the fourth region, and performing a second implantation into a second portion of the second set of fins different from the first portion.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: February 18, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10559749
    Abstract: A magnetoresistive effect element, which includes: a first ferromagnetic layer as a magnetization fixed layer; a second ferromagnetic layer as a magnetization free layer; and a nonmagnetic spacer layer provided between the first ferromagnetic layer and the second ferromagnetic layer. The nonmagnetic spacer layer includes an Ag alloy represented by General Formula (1), and thereby lattice mismatch between the nonmagnetic spacer layer, and the first ferromagnetic layer and/or the second ferromagnetic layer is reduced, compared to lattice mismatch when the nonmagnetic spacer layer is formed of Ag, Ag?X1-???(1) where X indicates one element selected from the group made of Al, Cu, Ga, Ge, As, Y, La, Sm, Yb, and Pt, and 0<?<1.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 11, 2020
    Assignee: TDK CORPORATION
    Inventors: Kazuumi Inubushi, Katsuyuki Nakada
  • Patent number: 10552049
    Abstract: A method and apparatus for managing data access comprises: receiving a write request for writing data into one or more storage blocks; in response to determining that a storage block is unavailable, writing a part of the data into a virtual storage block corresponding to the storage block, the part of the data being required to be written into the storage block; and in response to determining that the storage block becomes available, copying the part of the data from the virtual storage block to the storage block. The embodiments of the present disclosure further disclose a corresponding apparatus. By introducing the virtual storage blocks in the data access, the embodiments of the present disclosure can realize the parallel data transfers of a plurality of writes and thus greatly improve the data writing performance of the system.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: February 4, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Ruiyong Jia, Jian Gao, Lifeng Yang, Xu Xinlei, Jibing Dong
  • Patent number: 10541320
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: January 21, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Patent number: 10529715
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 10522418
    Abstract: A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Sheng Yun, You-Ru Lin, Shao-Ming Yu
  • Patent number: 10515872
    Abstract: A transistor having an emitter, a base, and a collector, the transistor includes a substrate, a collector contact, a metallic sub-collector coupled to the collector contact, and the metallic sub-collector electrically and thermally coupled to the collector, and an adhesive layer between the substrate and the metallic sub-collector, the adhesive layer bonded to the substrate and in direct contact with the substrate and bonded to the metallic sub-collector and in direct contact with the metallic sub-collector, wherein the adhesive layer comprises an electrically conductive material.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: December 24, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Yakov Royter, Pamela R. Patterson, Donald A. Hitko
  • Patent number: 10504991
    Abstract: In one example, a sensor includes a heterojunction bipolar transistor and component sensing surface coupled to the heterojunction bipolar transistor via an extended base component. In another example, a biosensor for detecting a target analyte includes a heterojunction bipolar transistor and a sensing surface. The heterojunction bipolar transistor includes a semiconductor emitter including an emitter electrode for connecting to an emitter voltage, a semiconductor collector including a collector electrode for connecting to a collector voltage, and a semiconductor base positioned between the semiconductor emitter and the semiconductor collector. The sensing surface is coupled to the semiconductor base of the heterojunction bipolar transistor via an extended base component and includes a conducting film and a reference electrode.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tak Ning, Sufi Zafar
  • Patent number: 10497817
    Abstract: P-N diodes that include p-type doped diamond and devices, such as p-n-p heterojunction bipolar transistors, that incorporate the p-n diodes are provided. In the p-n diodes, the diamond at the p-n junction has a positive electron affinity and is passivated by a thin layer of inorganic material that provides a tunneling layer that passivates the bonding interface states, without hindering carrier transport across the interface.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: December 3, 2019
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventor: Zhenqiang Ma
  • Patent number: 10497866
    Abstract: A non-volatile memory device is described herein. The non-volatile memory device includes a diffusive memristor electrically coupled to a redox transistor. The redox transistor includes a gate, a source, and a drain, wherein the gate comprises a first storage element that acts as an ion reservoir, and a channel between the source and the drain comprises a second storage element, wherein a state of the memory device is represented by conductance of the second storage element.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 3, 2019
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: Elliot James Fuller, Sapan Agarwal, Albert Alec Talin
  • Patent number: 10490639
    Abstract: In certain aspects, a heterojunction bipolar transistor (HBT) comprises a collector mesa, a base mesa on the collector mesa, and an emitter mesa on the base mesa. The base mesa has a tapered sidewall tapering from a wide bottom to a narrow top. The HBT further comprises a collector contact on a portion of the collector mesa and extending to a portion of the tapered sidewall of the base mesa.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li
  • Patent number: 10468508
    Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • Patent number: 10445008
    Abstract: A data management method for memory and a memory apparatus are provided. The memory includes a number of memory pages. Each of the memory pages includes multiple memory cells. Each of the memory cells includes a first bit and a second bit. Each of the memory cells has a first logical state, a second logical state, a third logical state, and a fourth logical state. The data management method for memory includes the following steps. A data update command corresponding to a logical address is received. The logical address corresponds to a physical address before receiving the data update command. A sanitizing voltage is applied to a first target memory cell of the memory cells in a target memory page of the memory pages located at the physical address. The logical state of the first target memory cell is changed.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yung-Chun Li, Ping-Hsien Lin, Yu-Ming Chang
  • Patent number: 10439053
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Patent number: 10431674
    Abstract: A bipolar junction transistor preferably includes: an emitter region; a base region; and a collector region, in which an edge of the emitter region is aligned with an edge of the base region. Preferably, an edge of the base region is aligned with an edge of the collector region, the edge of the emitter region is aligned with the edges of the base region and the collector region, and the widths of the emitter region, the base region, and the collector region are equivalent. According to a top view of the bipolar junction transistor, each of the base region and the collector region includes a rectangle.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Cho, Chen-Wei Pan
  • Patent number: 10424653
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10418328
    Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Kawamura
  • Patent number: 10396188
    Abstract: A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter may be smaller than 100 nanometers, which is suitable for high speed applications.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Gengming Tao, Xia Li
  • Patent number: 10389353
    Abstract: An optical switch includes: a photothyristor that is switched from an off state to an on state by incident light; a light-emitting element that emits outgoing light when the photothyristor is in the on state; and a tunnel junction layer or a III-V compound layer having metallic conductivity. The tunnel junction layer or the III-V compound layer is disposed between the photothyristor and the light-emitting element.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Takashi Kondo
  • Patent number: 10367084
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu