Abstract: Structures including a vertical heterojunction bipolar transistor and methods of forming a structure including a vertical heterojunction bipolar transistor. The structure comprises a semiconductor substrate including a trench, a first semiconductor layer including a portion adjacent to the trench, a dielectric layer between the first semiconductor layer and the semiconductor substrate, and a second semiconductor layer in the trench. The dielectric layer has an interface with the first semiconductor layer, and the second semiconductor layer includes a portion that is recessed relative to the interface. The structure further comprises a vertical heterojunction bipolar transistor including a collector in the portion of the second semiconductor layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.

Abstract: The invention relates to a curable resin composition containing (A) a multifunctional benzoxazine compound having two or more benzoxazine rings, (B) an epoxy compound having at least one norbornane structure and at least two epoxy groups, (C) a trisphenolmethane type epoxy compound, and (D) a curing agent, and optionally (E) an inorganic filler and (F) a curing accelerator; a cured product thereof; methods of producing the curable resin composition and the cured product; and a semiconductor device in which a semiconductor element is disposed in a cured product obtained by curing a curable resin composition containing components (A) to (D), and optionally components (E) and (F).

Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.

Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

Abstract: A semiconductor device includes a semiconductor substrate, first and second trench electrodes formed on the semiconductor substrate, a floating layer of a first conductivity type formed around the first and second trench electrodes, a floating separation layer of a second conductivity type formed between the first and second trench electrodes and contacted with the floating layer of the first conductivity type and a floating layer control gate disposed on the floating separation layer of the second conductivity type.

Abstract: A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.

Abstract: A hetero-junction phototransistor with a first layer comprising an InP N buffer and substrate, a second layer comprising an InGaAs N collector on the InP N buffer and substrate, a plurality of InGaAs P bases on the InGaAs N collector layer, and a plurality of InAIAs N emitters is described. Each emitter of the plurality of InAIAs N emitters is on a different base of the plurality of InGaAs P bases. The hetero-junction phototransistor comprises a plurality of InGaAs N+ caps, wherein each cap of the plurality of InGaAs N+ caps is on a different emitter of the plurality of InAIAs N emitters. The hetero-junction phototransistor comprises one or more electrical contacts. Each of the one or more electrical contacts is on a different cap of the plurality of InGaAs N+ caps.

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

Abstract: A method of manipulating deposition rates of poly-silicon and a method of manufacturing a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device are provided. The method of manipulating deposition rates of poly-silicon includes: providing a substrate, where a first surface of the substrate includes at least two of an oxide material region, a silicon nitride material region and a silicon material region; performing a first treatment on the first surface of the substrate, so as to manipulate the deposition rates of poly-silicon on different regions of the first surface to be closer; and forming a poly-silicon layer on the first surface of the substrate.

Abstract: The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N+-type diffusion region, an N-type diffusion region, a P+-type diffusion region, a P-type diffusion region, an N+-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N+-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N+-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N+-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N+-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.

Abstract: Methods of manufacturing a heterojunction bipolar transistor are described herein. An exemplary method can include providing a base/emitter stack, the base/emitter stack comprising a substrate, an etch stop layer over the substrate, an emitter contact layer over the etch stop layer, an emitter over the emitter contact layer, and/or a base over the emitter. The exemplary method further can include forming a collector. The exemplary method also can include wafer bonding the base to the collector. Other embodiments are also disclosed herein.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

Abstract: A semiconductor device, including a parallel pn layer formed on a semiconductor substrate, and an insulated gate structure provided on the parallel pn layer. The parallel pn layer includes a plurality of first regions and a plurality of second regions disposed repeatedly alternating one another along a first direction that is parallel to an upper surface of the semiconductor substrate. Each of the first regions and second regions has, along the first direction, an impurity concentration that has a maximum value thereof at a peak position and that decreases gradually from the peak position. Each of the first regions and second regions has, along a depth direction thereof, a first part and a second part, a gradient of the impurity concentration along the first direction being respectively symmetrical and asymmetrical in the first part and in the second part, with respect to the peak position.

Abstract: Disclosed is a transistor having a base, a substrate, and a collector between the substrate and the base. The collector has a first region of a first thickness under the base and is made up of a first dopant type having a substantially constant doping concentration across the first thickness. A second region with a second thickness under the first region is made up of a second dopant type that is different from the first dopant type and has a substantially constant doping concentration across the second thickness. A third region with a third thickness under the second region is made up of the second dopant type with a graded doping concentration that is a function of increasing distance from the second region through the third thickness. An emitter is located over the base opposite the collector.

Abstract: Embodiments of the present invention provide a multiple fin field effect transistor (finFET) with low-resistance gate structure. A metallization line is formed in parallel with the gate, and multiple contacts are formed over the fins which connect the metallization line to the gate. The metallization line provides reduced gate resistance, which allows fewer transistors to be used for providing In-Out (IO) functionality, thereby providing space savings that enable an increase in circuit density.

Abstract: A phototransistor includes an emitter, a collector, and a base between the emitter and the collector. The base has a thickness greater than 500 nanometers and the base absorbs photons passing through the collector to the base.

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

Abstract: The present disclosure discloses a distributed system and a message processing method. The distributed system includes a client and a plurality of nodes. The client includes processing circuitry that is configured to send a message including a digital signature of the client. The distributed system is in a first consensus mode for reaching a consensus on the message. The processing circuitry obtains results from a subset of the nodes that receive the message. The results have respective digital signatures of the subset of the nodes. After verifying the digital signatures of the subset of the nodes, the processing circuitry of the client determines, based on the results, whether one or more of the nodes in the distributed system is malfunctioned.

Abstract: A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.

Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.

Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

Abstract: A NiPt layer with a Pt atom concentration equal to 15% plus or minus 1% is deposited on a semiconductor region (which may, for example, be a source/drain region of a MOS transistor). An anneal is then performed at a temperature of 260° C. plus or minus 20° C., for a duration in the range from 20 to 60 seconds, in order to produce, from the Nickle-Platinum (NiPt) layer and the semiconductor material of said semiconductor region, an intermetallic layer. Advantageously, the intermetallic layer possesses a structure of heteroepitaxy with the semiconductor material, and includes free Pt atoms.

Abstract: Provided is a common-emitter and common-base heterojunction bipolar transistor disposed on a packaging substrate with a heat sink, including a common-base heterojunction bipolar transistor having a first base, a first emitter and a first collector, a common-emitter heterojunction bipolar transistor having a second base, a second emitter and a second collector, a heat shunt bridge for connecting the first emitter with the second collector, a first pad for being connected with the first base and a first copper pillar, a second pad for being connected with the first collector and a second copper pillar, a third pad for being connected with the second base and a third copper pillar, and a fourth copper pillar disposed above the second emitter; the common-emitter and common-base heterojunction bipolar transistor is flip-chip mounted on the packaging substrate, and the fourth copper pillar is soldered on the heat sink.

Abstract: Vertical bipolar junction transistors (VBJTs), each with one or more resistors connected in a circuit in different circuit configurations, are disclosed. The VBJT has an emitter substructure that includes an emitter layer, a collector, an intrinsic base, one or more doped epitaxy regions, and one or more resistors. The intrinsic base, the doped epitaxy region(s), and the resistor(s) are stacked upon one another in a channel between the emitter layer and the collector. Various circuit configurations and structures are described including a common-collector circuit, a common-emitter circuit, and an emitter-degenerate circuit. Methods of making these configuration/structures are disclosed.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a first semiconductor layer including a device region; a second semiconductor layer under the first semiconductor layer; a layer of conductive material between the first semiconductor layer and the second semiconductor layer; at least one contact extending to and contacting the layer of conductive material; and a device in the device region above the layer of conductive material.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region above the sub-collector region; an intrinsic base region composed of intrinsic base material located above the collector region; an emitter located above and separated from the intrinsic base material; and a raised extrinsic base having a stepped configuration and separated from and self-aligned to the emitter.

Abstract: A bipolar transistor includes an upper sub-collector layer, a collector layer, a base layer, an emitter layer, and a collector electrode. The collector layer is disposed on the upper sub-collector layer. The base layer is disposed on the collector layer. An emitter layer is disposed on the base layer. The collector electrode is disposed directly on a sidewall of the upper sub-collector layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with an oxygen lattice structure and methods of manufacture. The structure includes: a sub-collector region in a substrate; a collector region above the substrate; at least one oxygen film separating the sub-collector region and the collector region; an emitter region adjacent to the collector region; and a base region adjacent to the emitter region.

Abstract: A bipolar junction transistor includes a collector having a first surface on a first level and a second surface on a second level. A base is formed on the second level of the collector, and an emitter is formed on the base. A dielectric liner is formed on vertical sidewalls of the collector, the base and the emitter and over the first surface. A conductive region is formed adjacent to the base in the dielectric liner. A base contact is formed along one of the vertical sidewalls to connect to the base through the conductive region.

Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: A bipolar transistor includes a collector layer, a base layer on the collector layer, and a first elongated emitter mesa on the base layer having a long side and a short side, wherein the long side is parallel with a first direction, and n separate first emitter-contact structures disposed along the first direction on the first elongated emitter mesa, where n is an integer greater than one.

Abstract: In one aspect, a gate driver circuit includes a gate driver having a first input connected to a first node and a second input connected to a second node. The gate driver circuit also includes a current source circuit that includes a first transistor and a capacitor having a top plate connected to the source of the first transistor and a bottom plate connected to ground. The gate driver circuit further includes a switch that includes a second transistor. A gate of the second transistor is connected to a drain of the first transistor and a source of the second transistor is connected to the first node.

Abstract: The present application teaches, among other innovations, power semiconductor devices in which breakdown initiation regions, on BOTH sides of a die, are located inside the emitter/collector regions, but laterally spaced away from insulated trenches which surround the emitter/collector regions. Preferably this is part of a symmetrically-bidirectional power device of the “B-TRAN” type. In one advantageous group of embodiments (but not all), the breakdown initiation regions are defined by dopant introduction through the bottom of trench portions which lie within the emitter/collector region. In one group of embodiments (but not all), these can advantageously be separated trench portions which are not continuous with the trench(es) surrounding the emitter/collector region(s).

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A collector layer includes an inclined side surface, and a dielectric layer is positioned in a lateral direction adjacent to the inclined side surface of the collector layer. An intrinsic base is disposed over the collector layer, and an emitter is disposed over the intrinsic base. An airgap is positioned between the dielectric layer and the inclined side surface of the collector layer in the lateral direction, and an extrinsic base is positioned in the lateral direction adjacent to the intrinsic base. The extrinsic base is positioned over the airgap.

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS

Abstract: An optoelectronic device with a semiconductor body that includes: a bottom cathode structure, formed by a bottom semiconductor material, and having a first type of conductivity; and a buffer region, arranged on the bottom cathode structure and formed by a buffer semiconductor material different from the bottom semiconductor material. The optoelectronic device further includes: a receiver comprising a receiver anode region, which is formed by the bottom semiconductor material, has a second type of conductivity, and extends in the bottom cathode structure; and an emitter, which is arranged on the buffer region and includes a semiconductor junction formed at least in part by a top semiconductor material, different from the bottom semiconductor material.

Abstract: The disclosure provides a high ruggedness HBT structure, including: a sub-collector layer on a substrate and formed of an N-type III-V semiconductor material; a collector layer on the sub-collector layer and formed of a III-V semiconductor material; a base layer on the collector layer and formed of a P-type III-V semiconductor material; an emitter layer on the base layer and formed of one of N-type semiconductor materials of InGaP, InGaAsP and InAlGaP; a first emitter cap layer on the emitter layer and formed of one of undoped or N-type semiconductor materials of AlxGa1-xAs, AlxGa1-xAs1-yNy, AlxGa1-xAs1-zPz, AlxGa1-xAs1-wSbw, and InrAlxGa1-x-rAs, x having a highest value between 0.05?x?0.4, and y, z, r, w?0.1; a second emitter cap layer on the first emitter cap layer and formed of an N-type III-V semiconductor material; and an ohmic contact layer on the second emitter cap layer and formed of an N-type III-V semiconductor material.

Abstract: Photonic devices monolithically integrated with CMOS are disclosed, including sub-100 nm CMOS, with active layers comprising acceleration regions, light emission and absorption layers, and optional energy filtering regions. Light emission or absorption is controlled by an applied voltage to deposited films on a pre-defined CMOS active area of a substrate, such as bulk Si, bulk Ge, Thick-Film SOI, Thin-Film SOI, Thin-Film GOI.

Abstract: A lateral bipolar junction transistor including an emitter region, base region and collector region laterally orientated over a type IV semiconductor substrate, each of the emitter region, the base region and the collector region being composed of a type III-V semiconductor material. A buried oxide layer is present between the type IV semiconductor substrate and the emitter region, the base region and the collector region. The buried oxide layer having a pedestal aligned with the base region.

Abstract: A method of manufacturing a semiconductor device includes forming a field plate on an insulating film covering a transistor, the field plate being electrically coupled to a gate of the transistor via the insulating film, and the transistor being located on a substrate, forming a silicon nitride protective film covering the insulating film and the field plate, forming a silicon oxide base film on the silicon nitride protective film, and forming a MIM capacitor on the silicon oxide base film. The MIM capacitor includes a first electrode, a dielectric film and a second electrode which are stacked in an order. Forming the MIM capacitor includes performing wet etching on the silicon oxide base film on the field plate after forming the dielectric film.

Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.

Abstract: An opto-electronic High Electron Mobility Transistor (HEMT) may include a current channel including a two-dimensional electron gas (2DEG). The opto-electronic HEMT may further include a photoelectric bipolar transistor embedded within at least one of a source and a drain of the HEMT, the photoelectric bipolar transistor being in series with the current channel of the HEMT.

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.

Abstract: A channel stopper region extending from a first main surface into a component layer of a first conductivity type is formed in an edge region of a component region, the edge region being adjacent to a sawing track region. Afterward, a doped region extending from the first main surface into the component layer is formed in the component region. The channel stopper region is formed by a photolithographic method that is carried out before a first photolithographic method for introducing dopants into a section of the component region outside the channel stopper region.