Bipolar Transistor Patents (Class 257/197)
  • Patent number: 10439053
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Patent number: 10431674
    Abstract: A bipolar junction transistor preferably includes: an emitter region; a base region; and a collector region, in which an edge of the emitter region is aligned with an edge of the base region. Preferably, an edge of the base region is aligned with an edge of the collector region, the edge of the emitter region is aligned with the edges of the base region and the collector region, and the widths of the emitter region, the base region, and the collector region are equivalent. According to a top view of the bipolar junction transistor, each of the base region and the collector region includes a rectangle.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng Cho, Chen-Wei Pan
  • Patent number: 10424653
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10418328
    Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Kawamura
  • Patent number: 10396188
    Abstract: A semiconductor device comprises a heterojunction bipolar transistor (HBT). The HBT comprises an emitter, a collector, and a base between the emitter and the collector. A width of the emitter may be smaller than 100 nanometers, which is suitable for high speed applications.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Gengming Tao, Xia Li
  • Patent number: 10389353
    Abstract: An optical switch includes: a photothyristor that is switched from an off state to an on state by incident light; a light-emitting element that emits outgoing light when the photothyristor is in the on state; and a tunnel junction layer or a III-V compound layer having metallic conductivity. The tunnel junction layer or the III-V compound layer is disposed between the photothyristor and the light-emitting element.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Takashi Kondo
  • Patent number: 10367084
    Abstract: Fabrication methods and device structures for heterojunction bipolar transistors. A first emitter of a first heterojunction bipolar transistor and a second collector of a second heterojunction bipolar transistor are formed in a device layer of a silicon-on-insulator substrate. A first base layer of a first heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the first emitter. A first collector of the first heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the first base layer. A second base layer of the second heterojunction bipolar transistor is epitaxially grown on the device layer with an intrinsic base portion arranged on the second collector. A second emitter of the second heterojunction bipolar transistor is epitaxially grown on the intrinsic base portion of the second base layer. A connection is formed between the first emitter and the second collector.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Alvin J. Joseph, Qizhi Liu
  • Patent number: 10355079
    Abstract: Hydrogen atoms and crystal defects are introduced into an n-semiconductor substrate by proton implantation. The crystal defects are generated in the n-semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Masayuki Miyazaki, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 10355090
    Abstract: In an edge termination region, first to third electric field mitigating layers are provided in a concentric shape surrounding an active region. Between adjacent first to third electric field mitigating layers, p-type first to third space-modulated regions are provided each of which is closer to a chip edge than is the third electric field mitigating layer. Each of the space-modulated regions is formed by, from an inner side, a low-concentration sub-region and a high-concentration sub-region arranged to alternately repeat in a concentric shape surrounding the electric field mitigating layer on the inner side. Preferable, lengths (Lb1, Lb2, Lb3) of the first to third space-modulated regions are set to satisfy Lb1?Lb2<Lb3 and preferably lengths (La1, La2, La3) of the first to third electric field mitigating layers are set to satisfy La1<La2<La3. A rate of increase of the lengths of the first to third electric field mitigating layers may be constant.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shoji Yamada
  • Patent number: 10340292
    Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zuoguang Liu, Xin Miao
  • Patent number: 10319830
    Abstract: A heterojunction bipolar transistor may include an emitter, a base contacting the emitter, a collector contacting the base, a sub-collector contacting the collector, and an electrical isolation layer contacting the sub-collector. The heterojunction bipolar transistor may also include a backside heatsink thermally coupled to the sub-collector and the collector. The backside heatsink may be aligned with a central axis of the emitter and the base.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 11, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Bin Yang, Gengming Tao, Xia Li
  • Patent number: 10297680
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 21, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Patent number: 10263125
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device, such as a varactor diode. The IC device includes a composite collector and heterostructure. A layer of wider band gap material is included as part of the collector at the collector/base interface. The presence of the wide band gap material may increase breakdown voltage and allow for increased hyperabrupt doping profiles in the narrower band gap portion of the collector. This may allow for increased tuning range and improved intermodulation (IMD) performance without the decreased breakdown performance associated with homojunction devices. Other embodiments may also be described and/or claimed.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: April 16, 2019
    Assignee: Qorvo US, Inc.
    Inventor: Nick Gengming Tao
  • Patent number: 10236366
    Abstract: After forming a trench extending through an insulator layer and an underlying top semiconductor portion that is comprised of a first semiconductor material and a dopant of a first conductivity type to define an emitter and a collector on opposite sides of the trench in the top semiconductor portion, an intrinsic base comprising a second semiconductor material having a bandgap less than a bandgap of the first semiconductor material and a dopant of a second conductivity type opposite the first conductivity type is formed in a lower portion the trench by selective epitaxial growth. The intrinsic base protrudes above the top semiconductor portion and is laterally surrounded by entire top semiconductor portion and a portion of the insulator layer. An extrinsic base is then formed on top of the intrinsic base to fill a remaining volume of the trench by a deposition process.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Jeng-Bang Yau
  • Patent number: 10229856
    Abstract: Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • Patent number: 10217857
    Abstract: A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd
    Inventors: Young Seok Kim, Bum Seok Kim
  • Patent number: 10211090
    Abstract: Disclosed are embodiments of a transistor, which incorporates an airgap for low base-emitter capacitance (Cbe). Each embodiment of the transistor has a monocrystalline base and, within the monocrystalline base, an intrinsic base region and an extrinsic base region positioned laterally adjacent to the intrinsic base region, wherein the intrinsic and extrinsic base regions have co-planar top surfaces. An essentially T-shaped emitter in cross-section has a lower emitter region on the intrinsic base region and an upper emitter region above the lower emitter region. Each embodiment of the transistor further has an airgap, which is positioned laterally adjacent to the lower emitter region so as to be between the extrinsic base region and the upper emitter region. Thus, the entire airgap is above the co-planar top surfaces of the intrinsic base region and the extrinsic base region. Also disclosed herein are methods of forming the transistor embodiments.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Vibhor Jain, Renata A. Camillo-Castillo
  • Patent number: 10193010
    Abstract: A light emitting element includes: a light emitting part that is formed on a front surface side of a semi-insulating substrate; and a light receiving part that is formed on the front surface side, that shares a semiconductor layer with the light emitting part, and that receives light propagating in a lateral direction through the semiconductor layer from the light emitting part, wherein anode electrodes and cathode electrodes of the light emitting part and the light receiving part are formed on the front surface side in a state in which the anode electrodes are separated from each other and the cathode electrodes are separated from each other.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: January 29, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Naoki Jogan, Jun Sakurai, Akemi Murakami, Takashi Kondo, Junichiro Hayakawa
  • Patent number: 10177228
    Abstract: The present techniques relate to a semiconductor device having resistance which has a positive temperature coefficient and a suitable value, and to a method for manufacturing a semiconductor device having resistance which has a positive temperature coefficient and a suitable value. The semiconductor device related to the present techniques is a bipolar device in which a current flows through a pn junction. The semiconductor device includes an n-type silicon carbide drift layer, a p-type first silicon carbide layer formed on the silicon carbide drift layer, and a p-type second silicon carbide layer formed on the first silicon carbide layer. Then, the second silicon carbide layer has a positive temperature coefficient of resistance.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: January 8, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroshi Watanabe
  • Patent number: 10164048
    Abstract: A method includes providing a structure that includes a substrate, a gate structure over the substrate, and a source/drain (S/D) feature including silicon germanium (SiGe) adjacent to the gate structure. The method further includes implanting gallium (Ga) into the S/D feature; performing a first annealing process at a first temperature to recrystallize the SiGe; depositing a conductive material including a metal over the S/D feature after the first annealing process; performing a second annealing process at a second temperature to cause reaction between the metal and the S/D feature; and performing a third annealing process at a third temperature to activate dopants including Ga in the S/D feature.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
  • Patent number: 10153361
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Qizhi Liu, Anthony K. Stamper
  • Patent number: 10114743
    Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: October 30, 2018
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Tal Heller, Asaf Garfunkel, Hadas Oshinsky, Yacov Duzly, Amir Shaharabany, Judah Gamliel Hahn
  • Patent number: 10109724
    Abstract: A heterojunction bipolar transistor unit cell may include a compound semiconductor substrate. The heterojunction bipolar transistor unity may also include a base mesa on the compound semiconductor substrate. The base mesa may include a collector region on the compound semiconductor substrate and a base region on the collector region. The heterojunction bipolar transistor unity may further include a single emitter mesa on the base mesa.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: October 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Gengming Tao, Bin Yang, Xia Li, Miguel Miranda Corbalan
  • Patent number: 10090380
    Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 2, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Ana Villamor, Piet Vanmeerbeek, Jaume Roig-Guitart, Filip Bogman
  • Patent number: 10070529
    Abstract: A surface-mount component (10A) having a pair of connection terminals (12a, 12b) with an inter-terminal pitch L2 therebetween is mounted on a circuit substrate (20A) having a pair of electrode pads (22a, 22b) with an inter-electrode pitch L1 therebetween (L2>L1). Standard position indication marks (23) are formed on the circuit substrate (20A). When heating is performed under a state in which solder non-wetting of the left electrode pad (22a) occurs, the solder applied to the right electrode pad (22b) solder connects the right electrode pad (22b) and the connection terminal (12b), and the surface-mount component (10A) is attracted to the left and is offset or displaced from the standard position indication marks (23) by an offset dimension ?7. If the solder is applied to the left and right electrode pads (22a, 22b), there is no offset dimension.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Eitaro Fukuzumi, Mitsunori Nishida, Muneyuki Ooshima
  • Patent number: 10068992
    Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung Lo, Tzu-Hsiang Hsu, Chia-Jung Hsu, Feng-Cheng Yang, Teng-Chun Tsai, Ying-Ho Chen
  • Patent number: 10056449
    Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: August 21, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Masayuki Miyazaki, Hidenao Kuribayashi
  • Patent number: 10056390
    Abstract: An IC chip includes a logic circuit cells array and a static random access memory (SRAM) cells array. The logic circuit cells array includes a plurality of logic circuit cells abutted to one another in a first direction. The logic circuit cells array includes one or more continuous first fin lines that each extends across at least three of the abutted logic circuit cells in the first direction. The static random access memory (SRAM) cells array includes a plurality of SRAM cells abutted to one another in the first direction. The SRAM cells array includes discontinuous second fin lines.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10050647
    Abstract: A power amplification module includes a first amplification transistor that receives a first signal outputs an amplified second signal from the collector thereof; and a bias circuit that supplies a bias current to the base of the first amplification transistor. The first bias circuit includes a first transistor that is diode connected and is supplied with a bias control current; a second transistor that is diode connected, the collector thereof being connected to the emitter of the first transistor; a third transistor, the base thereof being connected to the base of the first transistor, and the bias current being output from the emitter thereof; a fourth transistor, the collector thereof being connected to the emitter of the third transistor and the base thereof being connected to the base of the second transistor; and a first capacitor between the base and the emitter of the third transistor.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 14, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Masatoshi Hase
  • Patent number: 10032912
    Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 24, 2018
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pierre Morin, Kangguo Cheng, Jody Fronheiser, Xiuyu Cai, Juntao Li, Shogo Mochizuki, Ruilong Xie, Hong He, Nicolas Loubet
  • Patent number: 10032893
    Abstract: A bipolar transistor comprises a semiconductor body including a collector region and a base region arranged on top of the collector region. The base region has a first crystalline structure and is at least partly doped with dopants of a first doping type. The collector region is laterally enclosed by a trench isolation and is doped with dopants of a second doping type. The transistor further comprises a conductive base contact layer laterally enclosing the base region which is doped with dopants of the first doping type. The base contact layer comprises a part with the first crystalline structure and a part with a second crystalline structure, wherein the part with the second crystalline structure laterally encloses the part with the first crystalline structure. The transistor further comprises an emitter region arranged on the base region.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: July 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Armin Tilke, Claus Dahl, Dmitri A. Tschumakow
  • Patent number: 10020322
    Abstract: A highly reliable semiconductor device which includes an oxide semiconductor is provided. Alternatively, a transistor having normally-off characteristics which includes an oxide semiconductor is provided. The transistor includes a first conductor, a first insulator, a second insulator, a third insulator, a first oxide, an oxide semiconductor, a second conductor, a second oxide, a fourth insulator, a third conductor, a fourth conductor, a fifth insulator, and a sixth insulator. The second conductor is separated from the sixth insulator by the second oxide. The third conductor and the fourth conductor are separated from the sixth insulator by the fifth insulator. The second oxide has a function of suppressing permeation of oxygen as long as oxygen contained in the sixth insulator is sufficiently supplied to the oxide semiconductor through the second oxide. The fifth insulator has a barrier property against oxygen.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: July 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Takahisa Ishiyama, Katsuaki Tochibayashi, Yoshinori Ando, Yasutaka Suzuki, Mitsuhiro Ichijo, Toshiya Endo, Shunpei Yamazaki
  • Patent number: 9997516
    Abstract: A semiconductor device includes a semiconductor substrate and first and second bipolar transistors. The semiconductor substrate includes first and second main surfaces opposing each other. The first bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a first emitter layer. The second bipolar transistor is formed on the first main surface of the semiconductor substrate and includes a second emitter layer and a resistor layer. The resistor layer is stacked on the second emitter layer in a direction normal to the first main surface.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: June 12, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Shigeru Yoshida, Kaoru Ideno
  • Patent number: 9991249
    Abstract: A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Min Ryu, Hyo-Sig Won
  • Patent number: 9991417
    Abstract: An optoelectronic device that includes a germanium containing buffer layer atop a silicon containing substrate, and a first distributed Bragg reflector stack of III-V semiconductor material layers on the buffer layer. The optoelectronic device further includes an active layer of III-V semiconductor material present on the first distributed Bragg reflector stack, wherein a difference in lattice dimension between the active layer and the first distributed brag reflector stack induces a strain in the active layer. A second distributed Bragg reflector stack of III-V semiconductor material layers having a may be present on the active layer.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jeehwan Kim, Ning Li, Devendra K. Sadana
  • Patent number: 9991217
    Abstract: A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: June 5, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Daisuke Tokuda, Tsunekazu Saimei, Hiroaki Tokuya
  • Patent number: 9972675
    Abstract: An RC-IGBT according to the invention includes a high electric field cell formed in a region surrounded by an IGBT cell or in a region surrounded by a diode cell, and an n+ diffusion layer formed at a position opposed to the high electric field cell, the position being on a second main surface of an n? type drift layer. The high electric field cell has a higher maximum electric field intensity generated when a voltage is applied between main terminals than maximum electric field intensities of the IGBT cell, the diode cell, and a withstand voltage holding structure. Additionally, a p+ type collector layer and the high electric field cell fail to overlap with each other in a direction vertical to a first main surface of the n? type drift layer in a plane view.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: May 15, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shinya Soneda
  • Patent number: 9905678
    Abstract: The present disclosure relates to a semiconductor device with multiple heterojunction bipolar transistors (HBTs) that have different emitter ballast resistances. The disclosed semiconductor device includes a substrate, a first HBT and a second HBT formed over the substrate. The first HBT includes a first collector, a first base over the first collector, a first emitter over the first base, and a first cap structure over the first emitter. The second HBT includes a second collector, a second base over the second collector, a second emitter over the second base, and a second cap structure over the second emitter. Herein, the first cap structure is different from the second cap structure, such that a first emitter ballast resistance from the first cap structure is at least 1.5 times greater than a second emitter ballast resistance from the second cap structure.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 27, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Peter J. Zampardi, Brian G. Moser, Thomas James Rogers
  • Patent number: 9882551
    Abstract: A frequency includes an input terminal, an output terminal, a transistor having a gate terminal which receives input of a signal including a first frequency from the input terminal, a source terminal and a drain terminal connected to the output terminal by a main line, an output matching circuit provided in the main line, the output matching circuit shutting off the first frequency while allowing an output frequency multiplied from the first frequency to pass therethrough, a branch line including a power supply terminal for connection to a power supply, the branch line branching off from a branch point in the main line, and a first diode provided in the branch line, the first diode having an anode connected to the power supply terminal and a cathode connected on the branch point side.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 30, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hitoshi Kurusu, Takumi Sugitani
  • Patent number: 9871125
    Abstract: A bipolar transistor and a method for fabricating a bipolar transistor are disclosed. In one embodiment the bipolar transistor includes a semiconductor body including a collector region and a base region arranged on top of the collector region, the collector region being doped with dopants of a second doping type and the base region being at least partly doped with dopants of a first doping type and an insulating spacers arranged on top of the base region. The semiconductor body further includes a semiconductor layer including an emitter region arranged on the base region and laterally enclosed by the spacers, the emitter region being doped with dopants of the second doping type forming a pn-junction with the base region, wherein the emitter region is fully located above a horizontal plane through a bottom side of the spacers.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 16, 2018
    Assignee: Infineon Technologies AG
    Inventors: Josef Boeck, Wolfgang Liebl
  • Patent number: 9865715
    Abstract: An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that are capable of further reducing a turn-on voltage are provided. An epitaxial wafer for a heterojunction bipolar transistor includes a collector layer made of GaAs, a base layer formed on the collector layer and made of InGaAs, and an emitter layer formed on the base layer and made of InGaP, and the base layer has an In composition that decreases from the emitter layer side toward the collector layer side.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: January 9, 2018
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Shinjiro Fujio, Takeshi Meguro
  • Patent number: 9831329
    Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 28, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
  • Patent number: 9831348
    Abstract: A thin film transistor is provided, and includes a gate electrode, a first gate dielectric layer, a second gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed on a substrate. The first gate dielectric layer is disposed on the gate electrode and the substrate, and has a radio of the number of silicon-hydrogen bonds to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.2 and 1.0. The second gate dielectric layer is disposed on the first gate dielectric layer, and has a radio of the number of silicon-hydrogen bond to the number of nitrogen-hydrogen bonds, in which the ratio is between 0.01 and 0.2. The channel layer is disposed on the second gate dielectric layer. The source electrode and drain electrode are disposed on the channel layer and located at two opposite sides of the channel layer.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: November 28, 2017
    Assignees: HannStar Display (Nanjing) Corporation, HannStar Display Corporation
    Inventor: Yung-Ching Wang
  • Patent number: 9824986
    Abstract: A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 21, 2017
    Assignee: SONY CORPORATION
    Inventor: Kazumasa Kohama
  • Patent number: 9825156
    Abstract: A compound semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors. The plurality of unit transistors are arranged in a first direction. The bump is disposed above the emitters of the plurality of unit transistors while extending in the first direction. The emitter of at least one of the plurality of unit transistors is displaced from a center line of the bump in the first direction toward a first side of a second direction which is perpendicular to the first direction. The emitter of at least another one of the plurality of unit transistors is displaced from the center line of the bump in the first direction toward a second side of the second direction.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: November 21, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara
  • Patent number: 9786770
    Abstract: A semiconductor device that includes a semiconductor structure having a side wall that is non planar and that extends farther outward at an upper portion than at a lower portion of the side wall. The semiconductor structure extends underneath a semiconductor layer wherein a top portion of the structure contacts the semiconductor layer.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: October 10, 2017
    Assignee: NXP USA, INC.
    Inventors: Jay Paul John, Vishal Trivedi, James Albert Kirchgessner
  • Patent number: 9761598
    Abstract: To provide a semiconductor device with excellent charge retention characteristics, a transistor including a thick gate insulating film to achieve low leakage current is additionally provided such that its gate is connected to a node for holding charge. The node is composed of this additional transistor and a transistor using an oxide semiconductor in its semiconductor layer including a channel formation region. Charge corresponding to data is held at the node.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 9741790
    Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: August 22, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 9711630
    Abstract: A semiconductor device, includes a semiconductor chip which includes: first and second terminals; a first conductive film pattern for the first terminal, formed over an interlayer insulation film; an insulation film formed over the interlayer insulation film so as to cover the first conductive film pattern; a first opening for the first terminal formed in the insulation film, and for exposing a part of the first conductive film pattern; and a nickel film formed over the first conductive film pattern at a portion thereof exposed from the first opening, wherein a semiconductor element controls a conduction between the first terminal and the second terminal, wherein the first terminal is formed of the first conductive film pattern and the nickel film, wherein the first conductive film pattern is formed of a lamination film having a first conductor film containing aluminum, and a second conductor film.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: July 18, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuyuki Yoshinaga, Kenta Sadakata
  • Patent number: 9691885
    Abstract: A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least partially arranged between the semiconductor substrate and the sacrificial layer. A recess is formed within the stack. The recess extends through the stack to the semiconductor substrate so that the recess at least partially overlaps with a surface of the collector region of the semiconductor substrate. The collector region extends from a main surface of the semiconductor substrate into the substrate material. The method further comprises generating a base structure at the collector region and in the recess. The base structure contacts and covers the collector region within the recess of the sacrificial layer. The method further comprises generating an emitter structure at the base structure. The emitter structure contacts and at least partially covers the base structure within the recess of the sacrificial layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: June 27, 2017
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Claus Dahl, Dmitri Alex Tschumakow