Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Abstract: A method of making a graphene base transistor with reduced collector area comprising forming a graphene material layer, forming a collector material, depositing a dielectric, planarizing the dielectric, cleaning and removing the native oxide, transferring a base graphene material layer to the top surface of the graphene material layer, bonding the base graphene material layer, and photostepping and defining a second graphene material layer. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region. A graphene base transistor with reduced collector area comprising an electron emitter region, an electron collection region, and a base region.

Abstract: Device structures for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.

Abstract: A SiGe HBT has an inverted heterojunction structure, where the emitter layer is formed prior to the base layer and the collector layer. The frequency performance of the SiGe HBT is significantly improved through a better thermal process budget for the base profile, essential for higher cut-off frequency (fT) and a minimal collector-base area for a reduced parasitic capacitance, essential for higher maximum oscillation frequency (fmax). This inverted heterojunction structure can be fabricated by using ALE processes to form an emitter on a preformed epitaxial silicide, a base over the emitter and a collector over the base.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: Methods of forming bipolar device structures and bipolar device structures. An opening may be formed in a device layer of a silicon-on-insulator substrate that extends to a buried insulator layer of the silicon-on-insulator substrate. An intrinsic base layer may be grown within the device layer opening by lateral growth on opposite first and second sidewalls of the device layer bordering the opening. A first collector of a first bipolar junction transistor of the device structure may be formed at a first spacing from the first sidewall. A second collector of a second bipolar junction transistor of the device structure may be formed at a second spacing from the second sidewall. An emitter, which is shared by the first bipolar junction transistor and the second bipolar transistor, is formed inside the opening. Portions of the intrinsic base layer may supply respective intrinsic bases for the first and second bipolar junction transistors.

Abstract: One aspect of this disclosure is a power amplifier module that includes a first die including a power amplifier and a passive component, the power amplifier including a bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm?3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and a second die including a bias circuit configured to generate a bias signal based at least partly on an indication of an electrical property of the passive component of the first die and to provide the bias signal to the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: The present disclosure relates to heterojunction bipolar transistors for improved radio frequency (RF) performance. In this regard, a heterojunction bipolar transistor includes a base, an emitter, and a collector. The base is formed over the collector such that a base-collector junction is formed between the base and the collector. The base-collector junction is configured to become forward-biased at a first turn-on voltage. The emitter is formed over the base such that a base-emitter junction is formed between the base and the emitter. The base-emitter junction is configured to become forward-biased at a second turn-on voltage, as opposed to the first turn-on voltage. Notably, the second turn-on voltage is lower than the first turn-on voltage.

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. An intrinsic base layer is formed on a semiconductor substrate, an etch stop layer is formed on the intrinsic base layer, and an extrinsic base layer is formed on the etch stop layer. A trench is formed that penetrates through the extrinsic base layer to the etch stop layer. The trench is formed by etching the extrinsic base layer selective to the etch stop layer. The first trench is extended through the etch stop layer to the intrinsic base layer by etching the etch stop layer selective to the intrinsic base layer. After the trench is extended through the etch stop layer, an emitter is formed using the trench.

Abstract: One aspect of this disclosure is a power amplifier module that includes a first die including a power amplifier and a passive component, the power amplifier including a bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm?3 at an interface with the base, the collector also having a grading in which doping concentration increases away from the base; and a second die including a bias circuit configured to generate a bias signal based at least partly on an indication of an electrical property of the passive component of the first die and to provide the bias signal to the power amplifier. Other embodiments of the module are provided along with related methods and components thereof.

Abstract: A method for fabricating a semiconductor device using a high-temperature ion implantation process includes providing a substrate including a plurality of fins. In some examples, a mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. By way of example, a first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. In various examples, an interstitial cluster is formed within the group of fins and within the test structure. In some embodiments, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.

Abstract: An improvement is achieved in the performance of a semiconductor device. Over the main surface of a semiconductor substrate for the n-type base of an IGBT, an insulating layer is formed. In a trench of the insulating layer, an n-type semiconductor layer is formed over the semiconductor substrate and, on both sides of the semiconductor layer, gate electrodes are formed via gate insulating films. In an upper portion of the semiconductor layer, a p-type semiconductor region for a p-type base and an n+-type semiconductor region for an n-type emitter are formed. Under the gate electrodes, parts of the insulating layer are present. The side surfaces of the gate electrodes opposite to the side surfaces thereof facing the semiconductor layer via the gate insulating films are adjacent to the insulating layer.

Abstract: A high-frequency device having a switching circuit including a semiconductor substrate; a first high-frequency input/output terminal; a second high-frequency input/output terminal; a control signal input terminal; a power terminal; a ground terminal; an insulating portion disposed on a main surface of the semiconductor substrate; and a voltage-applying electrode for applying a predetermined positive voltage from the power electrode to the semiconductor substrate, wherein the switching circuit includes a field-effect transistor disposed in an active region of the semiconductor substrate.

Abstract: A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate.

Abstract: A fin field effect transistor includes a first fin structure and a second fin structures both protruding from a substrate, first and second gate electrodes on the first and second fin structures, respectively, and a gate dielectric layer between each of the first and second fin structures and the first and second gate electrodes, respectively. Each of the first and second fin structures includes a buffer pattern on the substrate, a channel pattern on the buffer pattern, and an etch stop pattern provided between the channel pattern and the substrate. The etch stop pattern includes a material having an etch resistivity greater than that of the buffer pattern.

Abstract: Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier mobility of a channel layer and a reduced influence from interface states. A semiconductor wafer includes a base wafer, a first crystalline layer, and an insulating layer. The base wafer, the first crystalline layer, and the insulating layer are stacked in the order of the base wafer, the first crystalline layer, and the insulating layer. The first crystalline layer is made of InxGa1-xAs (0.35?x?0.43) that can pseudo-lattice-match with GaAs or AlGaAs. The first crystalline layer is usable as a channel layer of a field effect transistor, and the insulating layer is usable as a gate insulating layer of the field effect transistor.

Abstract: A bipolar junction transistor (BJT) formed using a fin field-effect transistor (FinFET) complimentary metal-oxide-semiconductor (CMOS) process flow is provided. The BJT includes an emitter fin, a base fin, and a collector fin formed on a substrate. The base fin encloses the emitter fin and collector fin encloses the emitter fin. In some embodiments, the emitter fin, base fin, and collector fin have a square shape when viewed from above and are concentric with each other.

Abstract: An image sensor device includes a silicon-based substrate, a silicon-germanium epitaxy layer, an isolation feature, an active pixel cell and a logic circuit. The silicon-germanium epitaxy layer is on the silicon-based substrate, in which the silicon-germanium epitaxy layer has a composition of Si1-xGex, where 0<x<1. The isolation feature is disposed in the silicon-germanium epitaxy layer to define a pixel region and a periphery region of the silicon-germanium epitaxy layer. The active pixel cell is disposed in the pixel region of the silicon-germanium epitaxy layer. The logic circuit is disposed in the periphery region.

Abstract: Systems and methods are disclosed for performing data sanitization at a data storage device (DSD). In an embodiment, a controller may direct a memory device to sanitize data by securely erasing the data, generate an attestation confirming that the data was successfully sanitized, and sign the attestation using an authentication key to create a signed attestation. In another embodiment, a circuit may direct a memory device to sanitize data based on the data sanitization instruction, generate a sanitization confirmation indicating that the data was successfully sanitized, and provide the sanitization confirmation including a first thumbprint and a second thumbprint to another device. Generating the sanitization confirmation may include processing a first storage encryption key to produce the first thumbprint, directing the memory device to obliterate the first storage encryption key, and processing a second storage encryption key to produce the second thumbprint.

Abstract: A bipolar junction transistor includes a common base region, a plurality of emitter regions disposed in the common base region and arrayed to be spaced apart from each other in a first diagonal direction, and a plurality of collector regions disposed in the common base region and arrayed to be spaced apart from each other in the first diagonal direction. The plurality of emitter regions and the plurality of collector regions are alternately arrayed in a second diagonal direction.

Abstract: P-type second semiconductor layers each interposed between a corresponding pair of n-type first semiconductor layers reduce the apparent doping concentration in the entire collector layer without reducing the doping concentrations in the first semiconductor layers. This improves the linearity of capacitance characteristics and enables sufficient mass productivity to be achieved. Interposing each of the second semiconductor layers between the corresponding pair of the first semiconductor layers reduce the average carrier concentration over the entire collector layer, which allows a wide depletion layer to be formed inside the collector layer and, as a result, reduces base-collector capacitance.

Abstract: A circuit arrangement with at least a source contact (7), a gate contact (6), and a Schottky-Reverse contact (2), which is embodied as a Schottky-contact above a transistor channel and connected to the source contact such that in a return operation electrons can flow from a drain contact (5, 5.1, 5.2) via the Schottky-Reverse contact to the source contact. The circuit arrangement includes at least two transistor sections (A, A?, B, B?), with a first of the transistor sections (A, A?) including the Schottky-Reverse contact and a second of the transistor section (B, B?) being embodied without the Schottky-Reverse contact. The two transistor sections (A, A?, B, B?) are arranged alternating and embodied such that at least in a forward operation electrons can flow in a transistor channel from a source contact (7) to the drain contact (5, 5.1, 5.2), circumventing an area of influence (12) of the Schottky-Reverse contact.

Abstract: The present disclosure relates to integrated circuit (IC) structures and methods of forming the same. An IC structure according to the present disclosure can include: a doped substrate region adjacent to an insulating region; a crystalline base structure including: an intrinsic base region located on and contacting the doped substrate region, the intrinsic base region having a first thickness; an extrinsic base region adjacent to the insulating region, wherein the extrinsic base region has a second thickness greater than the first thickness; a semiconductor layer located on the intrinsic base region of the crystalline base structure; and a doped semiconductor layer located on the semiconductor layer.

Abstract: Novel N-structured In As/Al Sb(Al Ga Sb)/Ga Sb based type-II SL pin detector with p on n and n on p configurations are given to detect light in the Mid Wavelength Infrared Range—MWIR with a cut-off wavelength of 5 ?m. Better carrier confinements are performed by placing AlSb layers switching from InAs layers to Ga Sb layers successively in the growth direction throughout the SL pin diode where zero bias detectivity is improved as 6×1013 A/Hz1/2 at a wavelength of 4.2 ?m at 79K. RoA value is measured as 1.8×106 ?cm2 which is better than nBn devices. Dark current density is also obtained in the range of 4-7×10?7 A/cm at zero bias and Vb=0.3V respectively at 79K.

Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.

Abstract: A pixel 10 includes a photodiode PD which is provided between a first barrier region 21 forming a first potential barrier B1 and a second barrier region 27 forming a second potential barrier B2, a first floating diffusion region F1 which is provided adjacent to the first barrier region 21, and to which a first electric charge generated in the photodiode PD is transferred, and a second floating diffusion region F2 which is provided adjacent to the second barrier region 27, and into which a second electric charge generated in the photoelectric conversion region PD flows, and in which a part of the flowing-in second electric charge is accumulated. The second potential barrier B2 is lower than the first potential barrier B1.

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Abstract: A device includes a semiconductor die. The semiconductor die includes a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap. The semiconductor die further includes a contact layer disposed epitaxially upon the first semiconductor layer. The contact layer has a thickness that is less than a critical thickness. The second semiconductor layer is epitaxially disposed upon the contact layer. The contact layer has a third band-gap that is less than the first band-gap and the second band-gap. The semiconductor die further includes a conductive layer disposed upon the contact layer to form an ohmic contact. The conductive layer comprises one or more metal layers compatible with silicon processing techniques.

Abstract: The reliability of a semiconductor device is improved. The semiconductor device includes a wire which is a conductive film pattern for a terminal formed over a first insulation film over a semiconductor substrate, a second insulation film formed over the first insulation film in such a manner as to cover the wire, and a nickel layer formed over the wire at a portion thereof exposed from an opening in the second insulation film. The wire is formed of a lamination film having a main conductor film containing aluminum as a main component, and a conductor film formed over the entire top surface of the main conductor film. The conductor film is formed of a titanium film, a tungsten film, or a titanium tungsten film. The nickel layer is formed over the conductor film at a portion thereof exposed from the opening.

Abstract: The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a semiconductor column having a first portion comprising a first material, a second portion comprising a second material, and a third portion comprising a third material, where the second material is different than the first material and the third material. The first portion, the second portion, and the third portion have substantially equal widths. A first abrupt interface exists between a top surface of the first portion and a bottom surface of the second portion, and a second abrupt interface exists between a top surface of the second portion and a bottom surface of the third portion, in an embodiment. In an embodiment, the column forms part of a transistor where the first portions functions as a source or drain, the second portion functions as a channel, and the third portion functions as a drain or source.

Abstract: A semiconductor device, that has a transistor region and a surge-protector region, includes: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer in the transistor region; and a surge-protector first electrode, a surge-protector second electrode, and a surge-protector third electrode formed on the second semiconductor layer in the surge-protector region, wherein the source electrode and the surge-protector second electrode are connected to each other, wherein the drain electrode and the surge-protector third electrode are connected to each other, wherein the surge-protector first electrode is formed between the surge-protector second electrode and the surge-protector third electrode, and wherein a distance between the surge-protector first electrode and the surge-protector third electrode is smaller than a distance between the g

Abstract: A graphene base transistor with reduced collector area comprising an electron injection region, an electron collection region, and a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith. A method of making a graphene base transistor with reduced collector area comprising forming an electron injection region, forming an electron collection region, and forming a base region wherein the base region comprises one or more sheets of graphene and wherein the base region is intermediate the electron injection region and the electron collection region and forms electrical interfaces therewith.

Abstract: Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.

Abstract: A device includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. The device further includes a first node and a second node, and an Electro-Static Discharge (ESD) device coupled between the first node and the second node. The ESD device includes a semiconductor fin adjacent to and over a top surface of the insulation region. The ESD device is configured to, in response to an ESD transient on the first node, conduct a current from the first node to the second node.

Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

Abstract: A housing for an optoelectronic semiconductor component includes a housing body having a mounting plane and a leadframe with a first connection conductor and a second connection conductor. The housing body deforms the leadframe in some regions. The leadframe has a main extension plane which extends obliquely or perpendicularly with respect to the mounting plane. A semiconductor component having such a housing and a semiconductor chip and a method for producing a housing are also disclosed.

Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

Abstract: The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC.

Abstract: According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a light transmitting layer and a first semiconductor layer. The light transmitting layer is transmittable with respect to light emitted from the light emitting layer. The first semiconductor layer contacts the light transmitting layer between the light emitting layer and the light transmitting layer. The light transmitting layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the light transmitting layer, has a lattice constant smaller than a lattice constant of the active layer, and has a tensile stress in an in-plane direction.

Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.

Abstract: According to a bipolar transistor structure having a transistor top and a transistor bottom herein, a silicon substrate located at the transistor bottom has a collector region of a first conductivity type. An epitaxial base layer of a second conductivity type overlies, relative to the transistor top and bottom, a portion of the collector region. The epitaxial base layer has a bottom surface on the silicon substrate and a top surface opposite the bottom surface. A top region, relative to the transistor top and bottom, of the epitaxial base layer comprises a concentration of germanium having atomic compositions sufficient to avoid impacting transistor parameters, and sufficient to be resistant to selective chemical etching. A silicon emitter layer of the first conductivity type overlies, relative to the transistor top and bottom, a portion of the epitaxial base layer adjacent to the top surface of the epitaxial base layer.

Abstract: A cascode gain stage apparatus includes a common-emitter connected transistor having a first base metal contact, first emitter metal contact, a first collector metal contact and a u-shaped first collector interface metal; and a common-base connected transistor having a second emitter metal contact, a second base metal contact, and a second collector metal contact, the second emitter metal contact in communication with the first collector metal contact through a transistor interconnect metallic strap, the second emitter metal contact disposed between the first collector metal contact and the second base metal contact. With this configuration, the first collector metal contact and second emitter metal contact are connected by the transistor interconnect metallic strap without high-aspect ratio traces to reduce crossover coupling.

Abstract: A higher breakdown voltage transistor has separated emitter, base contact, and collector contact. Underlying the emitter and the base contact are, respectively, first and second base portions of a first conductivity type. Underlying and coupled to the collector contact is a collector region of a second, opposite, conductivity type, having a central portion extending laterally toward, underneath, or beyond the base contact and separated therefrom by the second base portion. A floating collector region of the same conductivity type as the collector region underlies and is separated from the emitter by the first base portion. The collector and floating collector regions are separated by a part of the semiconductor (SC) region in which the base is formed. A further part of the SC region in which the base is formed, laterally bounds or encloses the collector region.

Abstract: Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.

Abstract: Embodiments generally relate to optoelectronic semiconductor devices such as photovoltaic cells. In one aspect, a method for forming a device includes forming an absorber layer made of gallium arsenide (GaAs) and having one type of doping, and forming an emitter layer made of a different material and having a higher bandgap than the absorber layer. An intermediate layer can be formed between emitter and absorber layers. A heterojunction and p-n junction are formed between the emitter layer and the absorber layer, where the p-n junction is formed at least partially within the different material at a location offset from the heterojunction. A majority of the absorber layer can be outside of a depletion region formed by the p-n junction. The p-n junction causes a voltage to be generated in the cell in response to the cell being exposed to light at a front side.

Abstract: A semiconductor device includes a first semiconductor region including a first semiconductor material. The semiconductor device further includes a second semiconductor region adjoining the first semiconductor region. The second semiconductor region includes a second semiconductor material different from the first semiconductor material. The semiconductor device further includes a drift or base zone in the first semiconductor region. The semiconductor device further includes an emitter region in the second semiconductor region. The second semiconductor region includes at least one type of deep-level dopant. A solubility of the at least one type of deep-level dopant is higher in the second semiconductor region than in the first semiconductor region.

Abstract: The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.