Heterojunction Formed Between Semiconductor Materials Which Differ In That They Belong To Different Periodic Table Groups (e.g., Ge (group Iv) - Gaas (group Iii-v) Or Inp (group Iii-v) - Cdte (group Ii-vi)) Patents (Class 257/200)
  • Patent number: 11308853
    Abstract: There are provided in the present disclosure a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register of the present disclosure includes: a forward scanning input sub-circuit for pre-charging a potential of a pull-up node by an operation level signal under control of a forward input signal and a forward scanning signal upon scanning forwards; a backward scanning input sub-circuit for pre-charging the potential of the pull-up node by an operation level signal under control of a backward input signal and a backward scanning signal upon scanning backwards; an output sub-circuit for outputting a clock signal through a signal output terminal under control of the potential of the pull-up node; wherein the pull-up node is a connection node of the forward scanning input sub-circuit, the backward scanning input sub-circuit and the output sub-circuit.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: April 19, 2022
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wang Guo, Yanchen Li, Yue Li, Jinyu Li, Dawei Feng, Yu Zhao, Shaojun Hou, Dong Wang, Mingyang Lv
  • Patent number: 11302807
    Abstract: A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: April 12, 2022
    Assignee: Nuvoton Technology Corporation
    Inventors: Chih-Hao Chen, Wen-Ying Wen
  • Patent number: 11302277
    Abstract: A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register unit comprises: an input circuit, a transmission circuit and an output control circuit; wherein the transmission circuit is coupled to a first node, a second node, a clock signal terminal and a first power source terminal, respectively, and is configured to control an electric potential of the second node under the control of the first node, the clock signal terminal and the first power source terminal, and the output control circuit is configured to control an electric potential of the output signal terminal under the control of the second node. The electric potential of the output signal from the output signal terminal in the shift register unit can be controlled by adopting one clock signal terminal, which effectively reduces the power consumption of the shift register unit.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: April 12, 2022
    Assignees: Ordos YuanSheng Optoelectronics Co., LTD., BOE Technology Group Co., LTD.
    Inventor: Fei Huang
  • Patent number: 11281320
    Abstract: An electronic device may include an edge touch screen including a main display region and an edge display region extending from the main display region each including one or more of red pixels, near infrared ray pixels, and sensor pixels for detecting light with different wavelengths; and a controller configured to, drive the edge touch screen in response to a touch input for the edge display region being maintained for a set time by instructing at least one selected red pixel of the red pixels and at least one selected near infrared ray pixel of the near infrared ray pixels corresponding to a position of the touch input to emit light, and measure biometrics based on light amounts of light of different wavelengths received from at least one selected sensor pixel of the sensor pixels corresponding to the position of the touch input.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Joon Heo, Kyung Bae Park, Yong Wan Jin
  • Patent number: 11282974
    Abstract: A photosensitive element includes a first film layer, a second film layer and a third film layer. The first film layer, the second film layer and the third film layer are in a sequentially stacked structure, the first film layer is a p-type copper indium gallium selenide (CIGS) layer, the second film layer is an i-type CIGS layer, and the third film layer is an n-type film layer, and the first film layer, the second film layer and the third film layer form a PIN junction structure.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 22, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingrong Ren, Jianming Sun, Yingwei Liu
  • Patent number: 11276723
    Abstract: A semiconductor device comprising: a substrate; a semiconductor layer; and a wiring structure section between the substrate and the semiconductor layer, the wiring structure section including a plurality of stacked wiring layers and a plurality of stacked insulating films, the wiring structure section including an electrode, wherein an opening for connecting a member to the electrode is formed in the semiconductor layer and the wiring structure section; the semiconductor layer has an isolation region in which an insulating film is embedded and which surrounds the opening; the wiring structure section has a ring which is formed of the plurality of wiring layers and surround the opening; and a distance between the opening and the ring closest to the opening is larger than a distance between the opening and the isolation region closest to the opening.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: March 15, 2022
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takumi Ogino, Hideaki Ishino, Akihiro Shimizu, Katsunori Hirota, Tsutomu Tange
  • Patent number: 11264303
    Abstract: A power semiconductor device includes a frame, a semiconductor element, a substrate, and a sealing resin. The semiconductor element is disposed on the frame. The substrate is disposed on a side of the frame opposite to a side on which the semiconductor element is disposed. The sealing resin seals the semiconductor element and the substrate. The substrate includes a metal sheet, a first insulating sheet on one main surface side of the metal sheet, and a second insulating sheet on the other main surface side of the metal sheet. The metal sheet has flexibility at a normal temperature.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 1, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinya Nakagawa, Takuya Shiraishi
  • Patent number: 11264285
    Abstract: Three-dimensional integration can overcome scaling limitations by increasing transistor density in volume rather than area. To provided gate-all-around field-effect-transistor devices with different threshold voltages and doping types on the same substrate, methods are provided for growing adjacent nanosheet stacks having channels with different doping profiles. In one example, a first nanosheet stack is formed having channels with first doping characteristics. Then the first nanosheet stack is etched, and a second nanosheet stack is formed in plane with the first nanosheet stack. The second nanosheet stack has channels with different doping characteristics. This process can be repeated for additional nanosheet stacks. In another example, the formation of the nanosheet stacks with channels having different doping characteristics is performed by restricting layer formation to predefined locations using a patterned layer (e.g.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: March 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mark Gardner, Jim Fulford
  • Patent number: 11245091
    Abstract: The present disclosure provides an OLED panel, an OLED packaging method, and a display panel. The OLED panel includes a substrate; an OLED element on a surface of the substrate; an inorganic cover layer on the substrate and the OLED element, the inorganic cover layer being configured to cover a peripheral portion of the surface of the substrate; a bonding layer on the inorganic cover layer; and a barrier layer on the bonding layer, wherein a portion of the bonding layer on the peripheral portion includes at least one rib configured to form an airtight space for isolating the OLED element from the external.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: February 8, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Ang Xiao, Xiaodong Yang, Guowei Li, Quanqin Sun, Yangyang Zhang, Hongjian Wu, Chao Ma, Guanyu Lu
  • Patent number: 11239327
    Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen
  • Patent number: 11240943
    Abstract: The disclosed concept relates to electrical isolation between power electronic and cooling and/or mounting components and, in particular, a ceramic layer disposed on one or more portions of the cooling and/or mounting components to provide electrical isolation, as well as, a thermally conductive path to remove heat produced by the power electronic component.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: February 1, 2022
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: David Glenn Woolard, Paul Thomas Murray
  • Patent number: 11227645
    Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: January 18, 2022
    Assignee: IMEC VZW
    Inventors: Sushil Sakhare, Manu Komalan Perumkunnil, Johan Swerts, Gouri Sankar Kar, Trong Huynh Bao
  • Patent number: 11211270
    Abstract: A method according to an embodiment includes: mounting a reference-specimen of a same material as that of a specimen on a support member and creating a map indicating a distortion in a gravity direction of the reference-specimen; mounting the specimen on the support member and irradiating light to the specimen; correcting a linear component of a distortion in a gravity direction of the specimen between a first point on the specimen and a second point located in the first scanning direction on the specimen on a basis of a first difference in the gravity direction between the first and second points in the map, and correcting a secondary component of the distortion in the gravity direction of the specimen using a feedback circuit, when the pattern is imaged; and performing a defect inspection using an image of the pattern.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: December 28, 2021
    Assignee: NUFLARE TECHNOLOGY, INC.
    Inventor: Masaya Takeda
  • Patent number: 11211485
    Abstract: Provided is a trench-type power transistor. The trench-type power transistor includes a source, a drain, a first gate, a second gate, a body diode and a body region contact diode. The body diode and the body region contact diode are connected in series. The first gate controls turn-on and turn-off of a first current channel through a gate voltage, the second gate is connected to the source and controls turn-on and turn-off of a second current channel through a source voltage.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: December 28, 2021
    Assignee: SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.
    Inventors: Zhendong Mao, Yuanlin Yuan, Lei Liu, Wei Liu, Rui Wang, Yi Gong
  • Patent number: 11171202
    Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 9, 2021
    Assignee: Infineon Technologies AG
    Inventors: Anton Mauder, Franz-Josef Niedernostheide, Christian Philipp Sandow
  • Patent number: 11162662
    Abstract: An LED lighting module and a display having the LED module are disclosed. The LED lighting module includes a plurality of micro LED arrays and a phosphor film. The micro LED arrays are respectively composed of at least one micro LED. The phosphor film is disposed on one side of the micro LED arrays; and the phosphor film has a transparent substrate and is provided with a plurality of light emitting regions. The plurality of light emitting regions are arranged adjacent to each other and into a matrix form, and are set corresponding to the micro LED arrays collimation respectively. A part or the whole of the surface of the plurality of light emitting regions is provided with at least one type of phosphor powder.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 2, 2021
    Assignee: UNITY OPTO TECHNOLOGY CO., LTD.
    Inventor: Ching-Huei Wu
  • Patent number: 11162189
    Abstract: There is provided a semiconductor substrate including: a sapphire substrate; an intermediate layer formed of gallium nitride with random crystal directions and provided on the sapphire substrate; and at least one or more semiconductor layers each of which is formed of a gallium nitride single crystal and that are provided on the intermediate layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: November 2, 2021
    Assignee: DEXERIALS CORPORATION
    Inventors: Kazuhiro Yagihashi, Shinya Akiyama
  • Patent number: 11145839
    Abstract: An organic EL display device includes an element substrate including a substrate, plurality of organic EL elements supported by the substrate and respectively located in the plurality of pixels, and bank layer defining each of the plurality of pixels; and thin film encapsulation structure covering the plurality of pixels. The bank layer has an inclining surface enclosing each of the plurality of pixels. The thin film encapsulation structure includes a first inorganic barrier layer, organic barrier layer including a plurality of solid portions in contact with a top surface of the first inorganic barrier layer, and second inorganic barrier layer in contact with the top surface of the first inorganic barrier layer and top surfaces of the plurality of solid portions. The plurality of solid portions include pixel periphery solid portions each extending from a portion on the inclining surface to a peripheral area in the corresponding pixel.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: October 12, 2021
    Assignee: Sakai Display Products Corporation
    Inventor: Katsuhiko Kishimoto
  • Patent number: 11140465
    Abstract: Concepts and technologies directed to optical networking with hybrid optical vortices are disclosed herein. Embodiments can include a system that is configured to perform operations for optical networking with hybrid optical vortices. The system can include a hybrid optical switch that can communicatively couple with another network device via one or more nanofiber communication paths. The operations can include receiving, from a first nanofiber communication path, a hybrid optical vortex that carries an internet protocol packet. The operations also can include decoupling the hybrid optical vortex to extract an optical vortex that encapsulates the internet protocol packet. The operations also can include switching the internet protocol packet to a subsequent communication path based on the optical vortex that encapsulates the internet protocol packet.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: October 5, 2021
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Timothy Innes, Oliver Elliott, Samuel Scruggs
  • Patent number: 11114037
    Abstract: Embodiments of the application provide a gate driver on array (GOA) circuit and a display apparatus, which is capable of outputting signals of negative pulse waveforms using a simplified circuit design and improving output capability of the GOA circuit by changing a high voltage level of a clock signal to a voltage level of a first high level signal. Thus, the GOA circuit is improved by the first capacitor and the second capacitor, which make the GOA circuit more stable.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 7, 2021
    Inventor: Liuqi Zhang
  • Patent number: 11094754
    Abstract: An organic light emitting display device and a method of fabricating thereof are discussed. The organic light emitting display device according to an example includes a plurality of first bank layers arranged along a first direction and a second direction on a substrate to define a plurality of pixels; a plurality of second bank layers disposed along the first direction on the first bank layers to divide the columns of pixels having different colors; an organic light emitting layer in each pixel; at least one first pocket pixel unit at both sides of the pixel having the smallest area; and a first dummy organic light emitting layer in the first pocket pixel unit.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 17, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyuk-Chan Gee, Jeong-Gyun Shin, Young-Tae Son, Sang-Bin Lee
  • Patent number: 11062764
    Abstract: A semiconductor device includes a control signal generation circuit and an input/output control circuit. The control signal generation circuit enters a copy operation based on a combination of logic levels of first and second operation control signals and generates a transfer control signal according to a detection result of logic levels of bits included in first internal data during the copy operation. The input/output control circuit generates first data and second data by inverting or non-inverting the logic levels of the first internal data based on the transfer control signal.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventor: Kwang Hun Lee
  • Patent number: 11042518
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based hierarchical data storage. One of the methods includes: determining, based on a blockchain stored in a database that includes multiple levels of storage, a block number interval that includes one or more block numbers associated with data nodes to be migrated to a lower level of storage in response to the data nodes meeting a data migration condition, wherein each of the data nodes is included in a state Merkle tree and is associated with a block number of a block of the blockchain where the corresponding data node was last updated, and the lower level of storage corresponds to a storage media with lower storage cost.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 22, 2021
    Assignee: Advanced New Technologies Co., Ltd.
    Inventors: Zhonghao Lu, Benquan Yu, Haizhen Zhuo
  • Patent number: 11004798
    Abstract: Embodiments of the disclosure are drawn to arrangements of one or more “cuts” or pattern of cuts in conductive structures. Wiring layers may each include a cut pattern including a set of cuts through conductive structures of the wiring layers where each of the cuts is offset from the other in a direction orthogonal to the cut. The cut pattern in a wiring layer may be orthogonal to the cut pattern in another wiring layer. In some examples, the cut pattern may be a stair-step pattern. In some examples, the cut pattern may be interrupted by other conductive structures.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hirokazu Matsumoto, Ryota Suzuki, Mitsuki Koda, Makoto Sato
  • Patent number: 10985270
    Abstract: A nitride power transistor comprises: a silicon substrate comprising a differently doped semiconductor composite structure for forming a space charge depletion region; and a nitride epitaxial layer located on the silicon substrate. With introduction of a differently doped semiconductor composite structure for forming a space charge depletion region inside a silicon substrate of a nitride power transistor, the nitride power transistor is capable of withstanding a relatively high external voltage, and thus a breakdown voltage of the device is improved.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 20, 2021
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventor: Kai Cheng
  • Patent number: 10978529
    Abstract: An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulat
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 13, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Junichi Morinaga, Hikaru Yoshino
  • Patent number: 10978518
    Abstract: A display panel includes an upper display substrate including a display area and a non-display area adjacent to the display area, the display area including first to third pixel areas and a light shielding area adjacent to the first to third pixel areas, a lower display substrate including first to third light emitting elements configured to emit light of a first color and overlapping the first to third pixel areas, respectively, and a plurality of spacers overlapping the display area and arranged between the upper display substrate and the lower display substrate.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 13, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jeaheon Ahn, YeoGeon Yoon, Jeongki Kim, Seok-Joon Hong
  • Patent number: 10937873
    Abstract: A high electron mobility transistor includes a channel layer, a barrier layer on the channel layer, source and drain contacts on the barrier layer, a gate contact between the source and drain contacts, and a multi-layer passivation structure on the upper surface of the barrier layer between the source contact and the drain contact. The multi-layer passivation structure includes a first passivation layer that comprises a charge dissipation material directly contacts the upper surface of the barrier layer and a second passivation layer comprising a different material than the first passivation layer that also directly contacts the upper surface of the barrier layer. In some embodiments, at least one recess may be formed in the upper surface of the barrier layer and the second passivation layer may be formed within the recesses.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Cree, Inc.
    Inventors: Kyoung-Keun Lee, Fabian Radulescu, Scott Sheppard
  • Patent number: 10879391
    Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mickey Hsieh, Chun-Yang Tsai, Kuo-Ching Huang, Kuo-Chi Tu, Pili Huang, Cheng-Jun Wu, Chao-Yang Chen
  • Patent number: 10879312
    Abstract: There are provided a memory device and a memory unit that make it possible to improve retention property of a resistance value in low-current writing. The memory device of the technology includes a first electrode, a memory layer, and a second electrode in order, in which the memory layer includes an ion source layer containing one or more transition metal elements selected from group 4, group 5, and group 6 in periodic table, one or more chalcogen elements selected from tellurium (Te), sulfur (S), and selenium (Se), and one or both of boron (B) and carbon (C), and a resistance change layer having resistance that is varied by voltage application to the first electrode and the second electrode.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: December 29, 2020
    Assignee: SONY CORPORATION
    Inventors: Hiroaki Sei, Kazuhiro Ohba, Seiji Nonoguchi
  • Patent number: 10873049
    Abstract: An organic light-emitting device and preparation method thereof, and a display apparatus are provided. The organic light-emitting device includes: a base substrate, an organic light-emitting element provided on the base substrate and an encapsulation structure for encapsulating the organic light-emitting element. The encapsulation structure includes a fluorescent material, and the organic light-emitting element emits a first light, and the fluorescent material is excited by the first light to generate a second light.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: December 22, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Wang
  • Patent number: 10867831
    Abstract: A method and apparatus for bonding semiconductor devices are disclosed. In an embodiment, the method may include attaching a first die to a flip head of a flip module, flipping the first die with the flip module, removing the first die from the flip module after flipping the first die, inspecting the flip head of the flip module for contamination after removing the first die, cleaning the flip head with an in situ cleaning module after inspecting the flip head, and attaching a second die to the flip head after cleaning the flip head.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Zuo Tsai, Yang-Chih Hsueh, Chia-Yin Chen, Fu-Kang Tien, Ebin Liao, Wen-Chih Chiou
  • Patent number: 10861703
    Abstract: To provide dummy openings having at least one of arrangement and shape determined depending on the shape of a non-effective region.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 8, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Hirohisa Fujita, Kenji Fujii, Satoshi Ibe, Makoto Watanabe, Shuhei Oya, Yusuke Hashimoto
  • Patent number: 10854731
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Andrew W. Yeoh, Joseph Steigerwald, Jinhong Shin, Vinay Chikarmane, Christopher P. Auth
  • Patent number: 10825892
    Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Wen-Tung Chen, Yu-Cheng Liu, Horng-Huei Tseng
  • Patent number: 10820072
    Abstract: Concepts and technologies directed to optical networking with hybrid optical vortices are disclosed herein. Embodiments can include a system that is configured to perform operations for optical networking with hybrid optical vortices. The system can include a hybrid optical switch that can communicatively couple with another network device via one or more nanofiber communication paths. The operations can include receiving, from a first nanofiber communication path, a hybrid optical vortex that carries an internet protocol packet. The operations also can include decoupling the hybrid optical vortex to extract an optical vortex that encapsulates the internet protocol packet. The operations also can include switching the internet protocol packet to a subsequent communication path based on the optical vortex that encapsulates the internet protocol packet.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: October 27, 2020
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Timothy Innes, Oliver Elliott, Samuel Scruggs
  • Patent number: 10789222
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based hierarchical data storage. One of the methods includes: determining, based on a blockchain stored in a database that includes multiple levels of storage, a block number interval that includes one or more block numbers associated with data nodes to be migrated to a lower level of storage in response to the data nodes meeting a data migration condition, wherein each of the data nodes is included in a state Merkle tree and is associated with a block number of a block of the blockchain where the corresponding data node was last updated, and the lower level of storage corresponds to a storage media with lower storage cost.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: September 29, 2020
    Assignee: Alibaba Group Holding Limited
    Inventors: Zhonghao Lu, Benquan Yu, Haizhen Zhuo
  • Patent number: 10790030
    Abstract: A non-volatile memory device and a method thereof that are capable of improving programming speed are introduced. The non-volatile memory device includes a memory array, a charge-pump circuit, a bias detection circuit and a memory controller is introduced. The memory array includes a plurality of memory cells; and a charge-pump circuit is configured to generate a charge-pump voltage. The bias detection circuit is coupled to the charge-pump circuit and is configured to determine whether a level of the charge-pump voltage is less than a first pre-determined threshold value. The memory controller is coupled to the bias detection circuit and is configured to pause a programming operation being performed on at least one of the plurality of memory cells when the bias detection circuit determines that the level of the charge-pump voltage is less than the first pre-determined threshold value.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: September 29, 2020
    Assignee: Windbond Electronics Corp.
    Inventor: Koying Huang
  • Patent number: 10770522
    Abstract: An EL device includes a display panel and an imaging element, and the display panel includes a panel substrate and an EL layer, and an imaging hole for guiding light from a subject to the imaging element is formed in the display area to straddle a plurality of scanning signal lines and a plurality of data signal lines when viewed from a direction perpendicular to a display area.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: September 8, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Tetsuya Ueno
  • Patent number: 10770540
    Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Andrew Vladimir Claude Cervin, Marina Zelner
  • Patent number: 10755925
    Abstract: A method for reducing crystalline defects in a semiconductor structure is presented. The method includes epitaxially growing a first crystalline material over a crystalline substrate, epitaxially growing a second crystalline material over the first crystalline material, and patterning and removing portions of the second crystalline material to form openings. The method further includes converting the first crystalline material into a non-crystalline material, depositing a thermally stable material in the openings, depositing a capping layer over the second crystalline material and the thermally stable material to form a substantially enclosed semiconductor structure, and annealing the substantially enclosed semiconductor structure.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Kunal Mukherjee, John A. Ott, Devendra K. Sadana, Brent A. Wacaser
  • Patent number: 10741478
    Abstract: A power module includes a first power semiconductor device including a first electrode, a resin frame including first receiving portions, and a first leadframe. The first leadframe has a first main surface facing the first electrode and is electrically and mechanically connected to the first electrode. The first receiving portions face the first main surface of the first leadframe and receive part of the first leadframe. Thus, the power module has high reliability and can be miniaturized.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: August 11, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shinnosuke Soda, Hiroshi Kobayashi
  • Patent number: 10734342
    Abstract: A semiconductor package includes: a connection member having a first surface and a second surface opposing each other in a stacking direction of the semiconductor package and including an insulating member and a redistribution layer formed on the insulating member and having a redistribution via; a semiconductor chip disposed on the first surface of the connection member and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection member and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection member; UBM pads disposed on the passivation layer and overlapping the redistribution vias in the stacking direction; and UBM vias connecting the UBM pads to the redistribution layer through the passivation layer, not overlapping the redistribution vias with respect to the stacking direction, and having a non-circular cross section.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seok Hwan Kim, Han Kim, Kyung Ho Lee, Kyung Moon Jung
  • Patent number: 10712851
    Abstract: An electronic device may include an edge touch screen including a main display region and an edge display region extending from the main display region each including one or more of red pixels, near infrared ray pixels, and sensor pixels for detecting light with different wavelengths; and a controller configured to, drive the edge touch screen in response to a touch input for the edge display region being maintained for a set time by instructing at least one selected red pixel of the red pixels and at least one selected near infrared ray pixel of the near infrared ray pixels corresponding to a position of the touch input to emit light, and measure biometrics based on light amounts of light of different wavelengths received from at least one selected sensor pixel of the sensor pixels corresponding to the position of the touch input.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Joon Heo, Kyung Bae Park, Yong Wan Jin
  • Patent number: 10705303
    Abstract: An optical connector assembly (OCA) includes a connector housing to maintain alignment between optical components housed within the OCA and photoelectric converters on an optoelectronic substrate (OES) assembly. The optical components include a ferrule and an optical cable. The ferrule is optically coupled to the optical cable. The OCA includes a ferrule holder to hold the ferrule within the OCA, and a spring located between the connector housing and the ferrule holder. The spring is to apply a separating force between the ferrule holder and the connector housing. The OCA includes a gasket coupled to the connector housing. The coupling of the connector housing to a socket compresses the gasket to provide a seal between the connector housing and the socket.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 7, 2020
    Inventors: Paul Kessler Rosenberg, George Panotopoulos, Kent Devenport, Darrell R. Childers, Cecil D. Hastings, Jr., Daniel D. Kurtz
  • Patent number: 10682958
    Abstract: Vehicle display device (10) including a display unit (50), installed in a cabin of a vehicle and having a display face oriented in a different direction from a direction of a driver (DR), configured to display an image depicting a surrounding area of the vehicle, and a mirror unit (55) installed in the cabin of the vehicle and configured to reflect some or all of an image area displayed on the display unit (50). A visible range of the surrounding area visible to the driver through an image of the display unit (50) reflected in the mirror unit (55) changes according to movement of a viewing position of the driver (DR) with respect to the mirror unit (55).
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 16, 2020
    Assignee: SONY CORPORATION
    Inventor: Eiji Oba
  • Patent number: 10679552
    Abstract: A pixel circuit includes a first control sub-circuit, a second control sub-circuit, a current detection sub-circuit, a driving sub-circuit, and an energy storage sub-circuit. The first control sub-circuit is configured to transmit a voltage on a data voltage terminal to a first node under control of a voltage on a first scan signal terminal. The second control sub-circuit is configured to transmit the voltage on the first node to a control terminal of the driving sub-circuit under control of a voltage on a second scan signal terminal. The current detection sub-circuit is configured to output a detection current under control of the voltage on the first node and detect a current value of the detection current. The driving sub-circuit is configured to output a driving current under control of the voltage on the control terminal of the driving sub-circuit. The energy storage sub-circuit is configured to store electrical energy.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: June 9, 2020
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xianrui Qian
  • Patent number: 10651306
    Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 12, 2020
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, Yu Cao
  • Patent number: 10629777
    Abstract: An optoelectronic semiconductor chip includes a semiconductor body including an n-conducting region, a p-conducting region and an active region between the n-conducting region and the p-conducting region; a first mirror containing a first metallic layer, and a p-metallization containing a second metallic layer, wherein during operation of the semiconductor chip, the first mirror is not at the same electrical potential as the p-conducting region, during operation of the semiconductor chip, the p-metallization is at the same electrical potential as the p-conducting region, and the first mirror has at least one opening through which the p-metallization is electrically conductively connected to the p-conducting region.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: April 21, 2020
    Assignee: OSRAM OLED GmbH
    Inventor: Alexander F. Pfeuffer
  • Patent number: 10621120
    Abstract: An integrated-circuit buffer component includes a control-side data interface configurably coupled to first and second memory-side data interfaces via internal conductors, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Rambus Inc.
    Inventors: Ian P. Shaeffer, Arun Vaidyanath, Sanku Mukherjee