Abstract: A memory apparatus includes an address decoding circuit configured to output a test redundancy address based on an address that is transmitted from a memory controller; and a redundancy address check circuit configured to determine whether the test redundancy address is replacing a failed address, in order to perform an ECC test operation by using the test redundancy address.

Abstract: An optoelectronic device includes a first semiconductor layer, a second semiconductor layer and an active layer between the first semiconductor layer and the second semiconductor layer; a first insulating layer on the second semiconductor layer and including a plurality of first openings exposing the first semiconductor layer, wherein the first openings include a first group and a second group; a third electrode on the first insulating layer and including a first extended portion and a second extended portion, wherein the first extended portion and the second extended portion are respectively electrically connected to the first semiconductor layer through the first group of the first openings and the second group of the first openings, and wherein the number of the first group of the first openings is different from the number of the second group of the first openings; and a plurality of fourth electrodes on the second insulating layer and electrically connected to the second semiconductor layer, wherein in a

Abstract: Provided is a semiconductor light-emitting element having improved light emission output. The semiconductor light-emitting element includes a light-emitting layer having a layered structure in which a first III-V compound semiconductor layer and a second III-V compound semiconductor layer having different composition ratios are repeatedly stacked. The first and second III-V compound semiconductor layers each contain three or more types of elements that are selected from Al, Ga, and In and from As, Sb, and P. The composition wavelength difference between the composition wavelength of the first III-V compound semiconductor layer and the composition wavelength of the second III-V compound semiconductor layer is 50 nm or less. The ratio of the lattice constant difference between the lattice constant of the first III-V compound semiconductor layer and the lattice constant of the second III-V compound semiconductor layer is not less than 0.05% and not more than 0.60%.

Abstract: A display panel and a display device. The display panel includes a test circuit located in a non-display region. The test circuit includes a plurality of switching transistors and at least one data switching line extending in a first direction. In each switching transistor, a first end of the switching transistor is electrically connected to a data line in the display panel, and a second end of the switching transistor is configured to receive a test data signal. The data switching line is disposed in the same layer as a source-drain layer of the switching transistor. The data switching line is configured to control the switching transistor to be turned on or off.

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

Abstract: An apparatus for treating a substrate includes a process chamber having a treatment space defined therein, a support unit for supporting the substrate in the treatment space, a liquid supply unit for supplying treating liquid to the substrate supported on the support unit, and a heating unit disposed in the support unit for heating the substrate supported on the support unit, wherein the heating unit includes a plurality of lamps to heat the substrate, and a window disposed above the lamps to transmit light emitted from the lamps, wherein the window includes a base in a form of a plate, and light adjustment means formed on the base to spread or converge light emitted from the lamps.

Abstract: Radar sensor, having an antenna assembly and a monolithic microwave integrated circuit that is arranged on a circuit board of the radar sensor and comprises at least one antenna connection that is to be connected to the antenna assembly, in particular is implemented in a ball grid, provides radar signals to be emitted, which can be generated by the microwave circuit, or accepts received radar signals from the antenna assembly, the connection of the antenna connection to the antenna assembly being formed at least in part by a waveguide, wherein, for connecting the at least one antenna connection to the waveguide designed as a wave duct, the circuit board comprises, at the position of the antenna connection, a through-opening leading to the side of the circuit board opposite the microwave circuit, through which the antenna connection is connected to a radiation element projecting into the waveguide arranged on the opposite side of the circuit board at the position of the antenna connection.

Abstract: A display device includes a carrier, a substrate unit, a plurality of light emitting elements and a circuit unit. The carrier has a top surface and a bottom surface opposite to each other, and a peripheral surface interconnecting the top and bottom surfaces. The substrate unit is disposed on one side of the peripheral surface of the carrier. The light emitting elements are spacedly disposed on the top surface of the carrier. The circuit unit includes a plurality of circuit modules that are disposed on the substrate unit and that are electrically connected to the light emitting elements. Each of the circuit modules includes a switch control circuit and a driving circuit that are configured to control the light emitting elements.

Abstract: According to an aspect, a detection device includes: a substrate; a plurality of photoelectric conversion elements provided to the substrate; a plurality of transistors provided corresponding to each of the photoelectric conversion elements; and a plurality of scan lines that extend in a first direction. A plurality of detection elements each include the photoelectric conversion element and the transistors provided so as to overlap the photoelectric conversion element. The detection elements include a first detection element and a second detection element adjacent in a second direction intersecting the first direction, and one of the scan lines is provided between the first detection element and the second detection element and is coupled to the first detection element and the second detection element.

Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.

Abstract: A system and method for detecting a single-molecule using an integrated circuit which includes at least one membrane having a nanopore located between first and second reservoirs and a low-noise preamplifier having an electrode formed on the surface thereof is provided. The method includes passing a target molecule through the nanopore, and measuring a current through the nanopore to detect the presence of a biomolecular entity, if any.

Abstract: An optical member that has excellent antireflection properties and that can maintain antifogging properties over a long term, and a method for manufacturing an optical member are provided. The optical member includes, in sequence, a substrate, a porous layer, and a multilayered antireflection layer. The ratio n/n0 is 0.85 or more and 0.95 or less, where n represents a refractive index of a layer having the highest refractive index among layers included in the antireflection layer and n0 represents a refractive index of a compound constituting the layer having the highest refractive index at a theoretical density.

Abstract: The present disclosure discloses a dimming mirror and a manufacturing method thereof, and a dimming apparatus. The dimming mirror includes a dimming layer including a plurality of dimming units. Each of the dimming units includes a first driving structure and a second driving structure opposite to each other, and an elastic supporting structure disposed between the first driving structure and the second driving structure. The first and second driving structures and the elastic supporting structure enclose a dimming chamber. The first and second driving structures are configured to adjust a dimming angle of the dimming unit by adjusting a gap width of the dimming chamber, such that a response wavelength of the dimming mirror is adjusted. The present disclosure facilitates the improvement of the flexibility of the dimming mirror.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

Abstract: A semiconductor device includes a support body including a mount region, a semiconductor chip disposed on the mount region with a predetermined distance therebetween, a bump disposed between the support body and the semiconductor chip, a wall portion disposed between the support body and the semiconductor chip along a part of an outer edge of the semiconductor chip, and an underfill resin layer disposed between the support body and the semiconductor chip. The underfill resin layer covers an outer side surface of the wall portion.

Abstract: A flash memory including a NAND memory cell array, a current detection unit, an offset voltage determining unit, and a reading voltage generating unit. The NAND memory cell array forms at least one monitoring NAND string in each block, which are used to monitor the cycle frequency of programing and erasing. The current detection unit detects the current that flows through the monitoring NAND string. The offset voltage determining unit determines the first offset voltage and the second offset voltage that are respectively added to the read-pass voltage and the reading voltage, according to the current detected. The reading voltage generating unit generates the read-pass voltage with the first offset voltage added. The reading voltage generating unit also generates the reading voltage with the second offset voltage added.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a logic region; forming a stack structure on the memory region and a gate structure on the logic region; forming a first cap layer on the stack structure and the gate structure; performing an oxidation process to form an oxide layer on the first cap layer; forming a second cap layer on the oxide layer; and removing part of the second cap layer, part of the oxide layer, and part of the first cap layer on the logic region to form a spacer adjacent to the gate structure.

Abstract: An LED lighting module with micro led arrays and phosphor film is disclosed. The LED lighting module includes a plurality of micro LED arrays and a phosphor film. The micro LED arrays are respectively composed of at least one micro LED. The phosphor film is disposed on one side of the micro LED arrays; and the phosphor film has a transparent substrate and is provided with a plurality of light emitting regions. The plurality of light emitting regions are arranged adjacent to each other and into a matrix form, and are set corresponding to the micro LED arrays collimation respectively. A part or the whole of the surface of the plurality of light emitting regions is provided with at least one type of phosphor powder.

Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based hierarchical data storage. One of the methods includes: determining, based on a blockchain stored in a database that includes multiple levels of storage, a block number interval that includes one or more block numbers associated with data nodes to be migrated to a lower level of storage in response to the data nodes meeting a data migration condition, wherein each of the data nodes is included in a state Merkle tree and is associated with a block number of a block of the blockchain where the corresponding data node was last updated, and the lower level of storage corresponds to a storage media with lower storage cost.

Abstract: A method is presented for improved linearity of a phase change memory (PCM) cell structure. The method includes forming a bottom electrode over a substrate, constructing a PCM stack including a plurality of PCM layers each having a different crystallization temperature over the bottom electrode, and forming a top electrode over the PCM stack. The crystallization temperature varies in an ascending order from the bottom electrode to the top electrode.

Abstract: A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.

Abstract: There are provided in the present disclosure a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register of the present disclosure includes: a forward scanning input sub-circuit for pre-charging a potential of a pull-up node by an operation level signal under control of a forward input signal and a forward scanning signal upon scanning forwards; a backward scanning input sub-circuit for pre-charging the potential of the pull-up node by an operation level signal under control of a backward input signal and a backward scanning signal upon scanning backwards; an output sub-circuit for outputting a clock signal through a signal output terminal under control of the potential of the pull-up node; wherein the pull-up node is a connection node of the forward scanning input sub-circuit, the backward scanning input sub-circuit and the output sub-circuit.

Abstract: A high electron mobility transistor (HEMT) device including a substrate, a first channel layer, a second channel layer, a cap layer, a first metal nitride layer, a gate, a source, and a drain is provided. The first channel layer is disposed on the substrate. The second channel layer is disposed on the first channel layer. The cap layer is disposed on the second channel layer and exposes a portion of the second channel layer. The first metal nitride layer is disposed on the cap layer. The gate is disposed on the first metal nitride layer. The width of the first metal nitride layer is greater than or equal to the width of the gate. The source and the drain are disposed on the second channel layer at two sides of the gate.

Abstract: A shift register unit and a driving method thereof, a gate driving circuit and a display apparatus are provided. The shift register unit comprises: an input circuit, a transmission circuit and an output control circuit; wherein the transmission circuit is coupled to a first node, a second node, a clock signal terminal and a first power source terminal, respectively, and is configured to control an electric potential of the second node under the control of the first node, the clock signal terminal and the first power source terminal, and the output control circuit is configured to control an electric potential of the output signal terminal under the control of the second node. The electric potential of the output signal from the output signal terminal in the shift register unit can be controlled by adopting one clock signal terminal, which effectively reduces the power consumption of the shift register unit.

Abstract: An electronic device may include an edge touch screen including a main display region and an edge display region extending from the main display region each including one or more of red pixels, near infrared ray pixels, and sensor pixels for detecting light with different wavelengths; and a controller configured to, drive the edge touch screen in response to a touch input for the edge display region being maintained for a set time by instructing at least one selected red pixel of the red pixels and at least one selected near infrared ray pixel of the near infrared ray pixels corresponding to a position of the touch input to emit light, and measure biometrics based on light amounts of light of different wavelengths received from at least one selected sensor pixel of the sensor pixels corresponding to the position of the touch input.

Abstract: A photosensitive element includes a first film layer, a second film layer and a third film layer. The first film layer, the second film layer and the third film layer are in a sequentially stacked structure, the first film layer is a p-type copper indium gallium selenide (CIGS) layer, the second film layer is an i-type CIGS layer, and the third film layer is an n-type film layer, and the first film layer, the second film layer and the third film layer form a PIN junction structure.

Abstract: A semiconductor device comprising: a substrate; a semiconductor layer; and a wiring structure section between the substrate and the semiconductor layer, the wiring structure section including a plurality of stacked wiring layers and a plurality of stacked insulating films, the wiring structure section including an electrode, wherein an opening for connecting a member to the electrode is formed in the semiconductor layer and the wiring structure section; the semiconductor layer has an isolation region in which an insulating film is embedded and which surrounds the opening; the wiring structure section has a ring which is formed of the plurality of wiring layers and surround the opening; and a distance between the opening and the ring closest to the opening is larger than a distance between the opening and the isolation region closest to the opening.

Abstract: A power semiconductor device includes a frame, a semiconductor element, a substrate, and a sealing resin. The semiconductor element is disposed on the frame. The substrate is disposed on a side of the frame opposite to a side on which the semiconductor element is disposed. The sealing resin seals the semiconductor element and the substrate. The substrate includes a metal sheet, a first insulating sheet on one main surface side of the metal sheet, and a second insulating sheet on the other main surface side of the metal sheet. The metal sheet has flexibility at a normal temperature.

Abstract: Three-dimensional integration can overcome scaling limitations by increasing transistor density in volume rather than area. To provided gate-all-around field-effect-transistor devices with different threshold voltages and doping types on the same substrate, methods are provided for growing adjacent nanosheet stacks having channels with different doping profiles. In one example, a first nanosheet stack is formed having channels with first doping characteristics. Then the first nanosheet stack is etched, and a second nanosheet stack is formed in plane with the first nanosheet stack. The second nanosheet stack has channels with different doping characteristics. This process can be repeated for additional nanosheet stacks. In another example, the formation of the nanosheet stacks with channels having different doping characteristics is performed by restricting layer formation to predefined locations using a patterned layer (e.g.

Abstract: The present disclosure provides an OLED panel, an OLED packaging method, and a display panel. The OLED panel includes a substrate; an OLED element on a surface of the substrate; an inorganic cover layer on the substrate and the OLED element, the inorganic cover layer being configured to cover a peripheral portion of the surface of the substrate; a bonding layer on the inorganic cover layer; and a barrier layer on the bonding layer, wherein a portion of the bonding layer on the peripheral portion includes at least one rib configured to form an airtight space for isolating the OLED element from the external.

Abstract: The disclosed concept relates to electrical isolation between power electronic and cooling and/or mounting components and, in particular, a ceramic layer disposed on one or more portions of the cooling and/or mounting components to provide electrical isolation, as well as, a thermally conductive path to remove heat produced by the power electronic component.

Abstract: A high electron mobility transistor (HEMT) includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer, wherein the aluminum gallium nitride layer comprises a tensile stress. A source electrode and a drain electrode are disposed on the aluminum gallium nitride layer. A gate electrode is disposed on the aluminum gallium nitride layer between the source electrode and the drain electrode. At least one silicon oxide layer is embedded in the aluminum gallium nitride layer, wherein the silicon oxide layer is formed by a flowable chemical vapor deposition, and the silicon oxide layer increases the tensile stress in the aluminum gallium nitride layer.

Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

Abstract: A method according to an embodiment includes: mounting a reference-specimen of a same material as that of a specimen on a support member and creating a map indicating a distortion in a gravity direction of the reference-specimen; mounting the specimen on the support member and irradiating light to the specimen; correcting a linear component of a distortion in a gravity direction of the specimen between a first point on the specimen and a second point located in the first scanning direction on the specimen on a basis of a first difference in the gravity direction between the first and second points in the map, and correcting a secondary component of the distortion in the gravity direction of the specimen using a feedback circuit, when the pattern is imaged; and performing a defect inspection using an image of the pattern.

Abstract: Provided is a trench-type power transistor. The trench-type power transistor includes a source, a drain, a first gate, a second gate, a body diode and a body region contact diode. The body diode and the body region contact diode are connected in series. The first gate controls turn-on and turn-off of a first current channel through a gate voltage, the second gate is connected to the source and controls turn-on and turn-off of a second current channel through a source voltage.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Abstract: An LED lighting module and a display having the LED module are disclosed. The LED lighting module includes a plurality of micro LED arrays and a phosphor film. The micro LED arrays are respectively composed of at least one micro LED. The phosphor film is disposed on one side of the micro LED arrays; and the phosphor film has a transparent substrate and is provided with a plurality of light emitting regions. The plurality of light emitting regions are arranged adjacent to each other and into a matrix form, and are set corresponding to the micro LED arrays collimation respectively. A part or the whole of the surface of the plurality of light emitting regions is provided with at least one type of phosphor powder.

Abstract: There is provided a semiconductor substrate including: a sapphire substrate; an intermediate layer formed of gallium nitride with random crystal directions and provided on the sapphire substrate; and at least one or more semiconductor layers each of which is formed of a gallium nitride single crystal and that are provided on the intermediate layer.

Abstract: An organic EL display device includes an element substrate including a substrate, plurality of organic EL elements supported by the substrate and respectively located in the plurality of pixels, and bank layer defining each of the plurality of pixels; and thin film encapsulation structure covering the plurality of pixels. The bank layer has an inclining surface enclosing each of the plurality of pixels. The thin film encapsulation structure includes a first inorganic barrier layer, organic barrier layer including a plurality of solid portions in contact with a top surface of the first inorganic barrier layer, and second inorganic barrier layer in contact with the top surface of the first inorganic barrier layer and top surfaces of the plurality of solid portions. The plurality of solid portions include pixel periphery solid portions each extending from a portion on the inclining surface to a peripheral area in the corresponding pixel.

Abstract: Concepts and technologies directed to optical networking with hybrid optical vortices are disclosed herein. Embodiments can include a system that is configured to perform operations for optical networking with hybrid optical vortices. The system can include a hybrid optical switch that can communicatively couple with another network device via one or more nanofiber communication paths. The operations can include receiving, from a first nanofiber communication path, a hybrid optical vortex that carries an internet protocol packet. The operations also can include decoupling the hybrid optical vortex to extract an optical vortex that encapsulates the internet protocol packet. The operations also can include switching the internet protocol packet to a subsequent communication path based on the optical vortex that encapsulates the internet protocol packet.

Abstract: Embodiments of the application provide a gate driver on array (GOA) circuit and a display apparatus, which is capable of outputting signals of negative pulse waveforms using a simplified circuit design and improving output capability of the GOA circuit by changing a high voltage level of a clock signal to a voltage level of a first high level signal. Thus, the GOA circuit is improved by the first capacitor and the second capacitor, which make the GOA circuit more stable.

Abstract: An organic light emitting display device and a method of fabricating thereof are discussed. The organic light emitting display device according to an example includes a plurality of first bank layers arranged along a first direction and a second direction on a substrate to define a plurality of pixels; a plurality of second bank layers disposed along the first direction on the first bank layers to divide the columns of pixels having different colors; an organic light emitting layer in each pixel; at least one first pocket pixel unit at both sides of the pixel having the smallest area; and a first dummy organic light emitting layer in the first pocket pixel unit.

Abstract: A semiconductor device includes a control signal generation circuit and an input/output control circuit. The control signal generation circuit enters a copy operation based on a combination of logic levels of first and second operation control signals and generates a transfer control signal according to a detection result of logic levels of bits included in first internal data during the copy operation. The input/output control circuit generates first data and second data by inverting or non-inverting the logic levels of the first internal data based on the transfer control signal.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for blockchain-based hierarchical data storage. One of the methods includes: determining, based on a blockchain stored in a database that includes multiple levels of storage, a block number interval that includes one or more block numbers associated with data nodes to be migrated to a lower level of storage in response to the data nodes meeting a data migration condition, wherein each of the data nodes is included in a state Merkle tree and is associated with a block number of a block of the blockchain where the corresponding data node was last updated, and the lower level of storage corresponds to a storage media with lower storage cost.

Abstract: Embodiments of the disclosure are drawn to arrangements of one or more “cuts” or pattern of cuts in conductive structures. Wiring layers may each include a cut pattern including a set of cuts through conductive structures of the wiring layers where each of the cuts is offset from the other in a direction orthogonal to the cut. The cut pattern in a wiring layer may be orthogonal to the cut pattern in another wiring layer. In some examples, the cut pattern may be a stair-step pattern. In some examples, the cut pattern may be interrupted by other conductive structures.

Abstract: A nitride power transistor comprises: a silicon substrate comprising a differently doped semiconductor composite structure for forming a space charge depletion region; and a nitride epitaxial layer located on the silicon substrate. With introduction of a differently doped semiconductor composite structure for forming a space charge depletion region inside a silicon substrate of a nitride power transistor, the nitride power transistor is capable of withstanding a relatively high external voltage, and thus a breakdown voltage of the device is improved.