Abstract: To provide a light-emitting element where electrons are efficiently injected into a Ge light emission layer and light can be efficiently emitted, the light-emitting element has a barrier layer 3 which is formed on an insulating film 2, worked in a size in which quantum confinement effect manifests and made of monocrystalline Si, a p-type diffused layer electrode 5 and an n-type diffused layer electrode 6 respectively provided at both ends of the barrier layer 3, and a monocrystalline Ge light emission part 13 provided on the barrier layer 3 between the electrodes 5, 6. At least a part of current that flows between the electrodes 5, 6 flows in the barrier layer 3 in a horizontal direction with respect to a substrate 1.

Abstract: A semiconductor wafer comprises, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer in this order, wherein both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rates of the first semiconductor crystal layer and the third semiconductor crystal layer by a second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent.

Abstract: A semiconductor device having a p base region and an n+ emitter region that come into contact with an emitter electrode and are selectively provided in a surface layer of an n? drift layer. A gate electrode is provided on a portion of the front surface of the n? drift layer which is interposed between the n+ emitter regions, with a gate insulating film interposed therebetween. In some exemplary embodiments, an n+ buffer layer and a p collector layer which have a higher impurity concentration than the n? drift layer are sequentially provided on a surface of the n? drift layer opposite to the front surface on which the n+ emitter region is provided. The impurity concentration of the n+ buffer layer is equal to or greater than 7×1016 cm?3 and equal to or less than 7×1017 cm?3. Accordingly, it is possible to obtain high field decay resistance.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N) and a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N). The IC device may further include a gate terminal and a gate dielectric layer disposed between the gate terminal and the barrier layer and/or between the gate terminal and the buffer layer. In various embodiments, the gate dielectric layer may include a fluoride- or chloride-based compound, such as calcium fluoride (CaF2).

Abstract: An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.

Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.

Abstract: The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, an N Field-Effect Transistor (NFET), a method for manufacturing an NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer 22.

Abstract: An object of the present invention is to provide a GaN-based light emitting diode element having a great emission efficiency and suitable for an excitation light source for a white LED. The GaN-based light emitting diode element includes an n-type conductive m-plane GaN substrate, a light emitting diode structure which is formed of a GaN-based semiconductor, on a front face of the m-plane GaN substrate, and an n-side ohmic electrode formed on a rear face of the m-plane GaN substrate, wherein a forward voltage is 4.0 V or less when a forward current applied to the light emitting diode element is 20 mA.

Abstract: According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.

Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.

Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.

Abstract: A method for reducing the effects of cracks in an epitaxial film. The method includes; providing a semiconductor wafer with an epitaxial film thereon; inspecting the epitaxial film to determine outer peripheral edge regions of the epitaxial film having cracks therein; and selectively removing the determined outer peripheral edge regions of the epitaxial film while leaving portions of the semiconductor wafer underlying the removed determined outer peripheral regions of the epitaxial film.

Abstract: Nonvolatile memory devices include a vertical stack of nonvolatile memory cells. The vertical stack of nonvolatile memory cells includes a first nonvolatile memory cell having a first gate pattern therein, which is separated from a vertical active region by a first multi-layered dielectric pattern having a first thickness, and a second nonvolatile memory cell having a second gate pattern therein, which is separated from the vertical active region by a second multi-layered dielectric pattern having a second thickness. The second gate pattern is also separated from the first gate pattern by a distance less than a sum of the first and second thicknesses.

Abstract: A semiconductor device may include a p-channel semiconductor active region and an n-channel semiconductor active region. An element isolation insulating layer electrically isolates the p-channel semiconductor active region from the n-channel semiconductor active region. An insulating layer made of a different material, being in contact with both ends, in its channel length direction, of the p-channel semiconductor active region applies a compression stress in the channel length direction to a channel of the p-channel semiconductor active region. The p-channel semiconductor active region is surrounded by the insulating layer, in the channel length direction, of the p-channel semiconductor active region and by the element isolation insulating layer, parallel to the channel length direction, of the p-channel semiconductor active region. The n-channel semiconductor active region is surrounded by the element isolation insulating layer.

Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.

Abstract: The presently claimed invention provides a barium strontium titanate/strontium titanate/gallium arsenide (BST/STO/GaAs) heterostructure comprising a gallium arsenide (GaAs) substrate, at least one strontium titanate (STO) layer, and at least one barium strontium titanate (BST) layer. The BST/STO/GaAs heterostructure of the present invention has a good temperature stability, high dielectric constant and low dielectric loss, which enable to fabricate tunable ferroelectric devices. A method for fabricating the BST/STO/GaAs heterostructure is also disclosed in the present invention, which comprises formation of at least one STO layer on the GaAs substrate by a first laser molecular beam epitaxial system, and formation of at least one BST layer on the STO layer by a second laser molecular beam epitaxial system.

Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract: According to one embodiment of the present invention, a solid state electrolyte memory cell includes a cathode, an anode and a solid state electrolyte. The anode includes an intercalating material and first metal species dispersed in the intercalating material.

Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.

Abstract: A semiconductor device according to an embodiment includes, a first conductivity type semiconductor substrate including one of Si and SiC; a second conductivity type semiconductor region at a surface of the semiconductor substrate, a GaN-based semiconductor layer on the semiconductor substrate, and a lateral semiconductor element at the GaN-based semiconductor layer and above the semiconductor region, the lateral semiconductor element having a first electrode and a second electrode electrically connected to the semiconductor region.

Abstract: A semiconductor device includes a first layer and a second layer over the first layer. The first and second layers are configured to form an electron gas layer at an interface of the first and second layers. The semiconductor device also includes an Ohmic contact and multiple conductive vias through the second layer. The conductive vias are configured to electrically couple the Ohmic contact to the electron gas layer. The conductive vias could have substantially vertical sidewalls or substantially sloped sidewalls, or the conductive vias could form a nano-textured surface on the Ohmic contact. The first layer could include Group III-nitride nucleation, buffer, and channel layers, and the second layer could include a Group III-nitride barrier layer.

Abstract: A semiconductor device includes: a transistor including an oxide semiconductor film; a first insulating film covering the oxide semiconductor film and including a first resin material; and a second insulating film including a second resin material that has polarity different from polarity of the first resin material, the second insulating film being laminated on the first insulating film.

Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: Passivation of group III-nitride heterojunction devices is described herein. The passivation facilitates simultaneous realization of effective/high current collapse suppression and low leakage current without the use of a sophisticated multiple-field plate technique. The passivation can be achieved by growing a charge-polarized AlN thin film on the surface of a group III-nitride based heterojunction device by plasma-enhanced atomic layer deposition such that positive polarization charges are induced at the interface to compensate for a majority of negative charges at the interface.

Abstract: There are disclosed herein various implementations of a monolithically integrated component. In one exemplary implementation, such a monolithically integrated component includes an enhancement mode group IV transistor and two or more depletion mode III-Nitride transistors. The enhancement mode group IV transistor may be implemented as a group IV insulated gate bipolar transistor (group IV IGBT). One or more of the III-Nitride transistor(s) may be situated over a body layer of the group IV IGBT, or the III-Nitride transistor(s) may be situated over a collector layer of the IGBT.

Abstract: An AlGaN/GaN.HEMT includes, a compound semiconductor lamination structure; a p-type semiconductor layer formed on the compound semiconductor lamination structure; and a gate electrode formed on the p-type semiconductor layer, in which Mg being an inert element of p-GaN is introduced into both sides of the gate electrode at the p-type semiconductor layer, and introduced portions of Mg are inactivated.

Abstract: In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.

Abstract: A fine pitch phase change random access memory (“PCRAM”) design and method of fabricating same are disclosed. One embodiment is a phase change memory (“PCM”) cell comprising a spacer defining a rectangular reaction area and a phase change material layer disposed within the reaction area. The PCM cell further comprises a protection layer disposed over the GST film layer and within the area defined by the spacer; and a capping layer disposed over the protection layer and the spacer.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Abstract: An optoelectronic semiconductor chip has a semiconductor layer sequence having an active layer that generates radiation between a layer of a first conductivity type and a layer of a second conductivity type. The layer of the first conductivity type is adjacent to a front side of the semiconductor layer sequence. The semiconductor layer sequence contains at least one cutout extending from a rear side, lying opposite the front side, of the semiconductor layer sequence through the active layer to the layer of the first conductivity type. The layer of the first conductivity type is electrically connected through the cutout by means of a first electrical connection layer which covers the rear side of the semiconductor layer sequence at least in places.

Abstract: One method disclosed herein includes forming a patterned mask layer above a surface of a semiconductor substrate, performing at least one etching process through the patterned mask layer to define a plurality of intersecting ridges that define a ridged surface in the substrate, and forming a Group III-V material on the ridged surface of the substrate. An illustrative device disclosed herein includes a Group IV substrate having a ridged surface comprised of a plurality of intersecting ridges and a Group III-V material layer positioned on the ridged surface of the Group IV substrate.

Abstract: A trench 107 is coated and sealed with a cap film 111 from above an amorphous or polycrystalline InP film 109A buried in the trench 107. Next, a monocrystalline InP film 109B is formed by monocrystallizing the InP film 109A, with a Si (001) plane of the bottom of the trench 107 as a seed crystal plane, by melting InP by heating a Si wafer W at or above a melting point of InP and then solidifying InP by cooling InP.

Abstract: A silicon wafer used in manufacturing GaN for LEDs includes a silicon substrate, a buffer layer of boron aluminum nitride (BxAl1-xN) and an upper layer of GaN, for which 0.35?x?0.45. The BAlN forms a wurtzite-type crystal with a cell unit length about two-thirds of a silicon cell unit length on a Si(111) surface. The C-plane of the BAlN crystal has approximately one atom of boron for each two atoms of aluminum. Across the entire wafer substantially only nitrogen atoms of BAlN form bonds to the Si(111) surface, and substantially no aluminum or boron atoms of the BAlN are present in a bottom-most plane of atoms of the BAlN. A method of making the BAlN buffer layer includes preflowing a first amount of ammonia equaling less than 0.01% by volume of hydrogen flowing through a chamber before flowing trimethylaluminum and triethylboron and then a subsequent amount of ammonia through the chamber.

Abstract: A nitride semiconductor wafer includes a silicon substrate, a first layer, a second layer, a third layer, a fourth layer, a fifth layer, and a sixth layer. The first layer is provided on the silicon substrate. The second layer is provided on the first layer. The third layer is provided on the second layer. The fourth layer is provided on the third layer. The fifth layer is provided on the fourth layer. The sixth layer is provided on the fifth layer. A composition ratio x4 of the fourth layer decreases in a first direction from the third layer toward the fifth layer. A maximum value of the composition ratio x4 is not more than a composition ratio of the third layer. A minimum value of the composition ratio x4 is not less than a composition ratio of the fifth layer.

Abstract: Embodiments of a thin-film heterostructure thermoelectric material and methods of fabrication thereof are disclosed. In general, the thermoelectric material is formed in a Group IIa and IV-VI materials system. The thermoelectric material includes an epitaxial heterostructure and exhibits high heat pumping and figure-of-merit performance in terms of Seebeck coefficient, electrical conductivity, and thermal conductivity over broad temperature ranges through appropriate engineering and judicious optimization of the epitaxial heterostructure.

Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.

Abstract: A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers.

Abstract: Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.

Abstract: A perovskite manganese oxide thin film formed on a substrate that allows a first order phase transition and has A-site ordering. The thin film contains Ba and a rare earth element in the A sites of a perovskite crystal lattice and has an (m10) orientation for which m=2n, and 9?n?1. A method for manufacturing the film includes forming in a controlled atmosphere using laser ablation an atomic layer or thin film that assumes a pyramidal structure having oxygen-deficient sites in a plane containing the rare earth element and oxygen; and filling the oxygen-deficient sites with oxygen. The controlled atmosphere has an oxygen partial pressure controlled to a thermodynamically required value for creating oxygen deficiencies and contains a gas other than oxygen, and has a total pressure that is controlled to a value at which the A sites have a fixed compositional ratio.

Abstract: The present invention provides a silicon-compatible compound junctionless field effect transistor enabled to be compatible to a bulk silicon substrate for substituting an expensive SOI substrate, to form a blocking semiconductor layer between a silicon substrate and an active layer by a semiconductor material having a specific difference of energy bandgap from that of the active layer to substitute a prior buried oxide for blocking a leakage current at an off-operation time and to form the active layer by a semiconductor layer having electron or hole mobility higher than that of silicon, and to operate perfectly as a junctionless device though the dopant concentration of the active layer is much lower than the prior junctionless device.

Abstract: A structure comprises a substrate, a mask, a buffer/nucleation layer, and a group III-V compound semiconductor material. The substrate has a top surface and has a recess from the top surface. The recess includes a sidewall. The first mask is the top surface of the substrate. The buffer/nucleation layer is along the sidewall, and has a different material composition than a material composition of the sidewall. The III-V compound semiconductor material continuously extends from inside the recess on the buffer/nucleation layer to over the first mask.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.