Abstract: A method for fabricating a semiconductor device which protects the ohmic metal contacts and the channel of the device during subsequent high temperature processing steps is explained. An encapsulation layer is used to cover the channel and ohmic metal contacts. The present invention provides a substrate on which a plurality of semiconductor layers are deposited. The semiconductor layers act as the channel of the device. The semiconductor layers are covered with an encapsulation layer. A portion of the encapsulation layer and the plurality of semiconductor layers are removed, wherein ohmic metal contacts are deposited. The ohmic metal contacts are then annealed to help reduce their resistance. The encapsulation layer ensures that the ohmic metal contacts do not migrate during the annealing step and that the channel is not harmed by the high temperatures needed during the annealing step.

Abstract: A novel method for synthesizing device-quality alloys and ordered phases in a Si—Ge—Sn system uses a UHV-CVD process and reactions of SnD4 with SiH3GeH3. Using the method, single-phase SixSnyGe1-x-y semiconductors (x?0.25, y?0.11) are grown on Si via Ge1-xSnx buffer layers The Ge1-xSnx buffer layers facilitate heteroepitaxial growth of the SixSnyGe1-x-y films and act as compliant templates that can conform structurally and absorb the differential strain imposed by the more rigid Si and Si—Ge—Sn materials. The SiH3GeH3 species was prepared using a new and high yield method that provided high purity semiconductor grade material.

Abstract: A nitride semiconductor device includes an n-type layer made of a group III nitride semiconductor and a layer made of a group III nitride semiconductor containing a p-type impurity laminated and formed in contact with the n-type layer, and Al is contained in a portion of the n-type layer in contact with the layer containing the p-type impurity.

Abstract: A semiconductor light emitting device includes: an upper growth layer including a light emitting layer; a transparent substrate through which a radiant light from the light emitting layer passes; and a foundation layer provided between the upper growth layer and the transparent substrate, the foundation layer having a surface-controlling layer and a bonding layer bonded with the transparent substrate. The surface-controlling layer is made of compound semiconductor including at least Ga and As. The upper growth layer is formed on an upper surface of the surface-controlling layer. A lattice constant difference at an interface between the surface-controlling layer and the upper growth layer is smaller than that at an interface between the bonding layer and the transparent substrate.

Abstract: In a process for fabricating a nano-floating gate memory structure, a substrate and a nanocluster source are firstly provided. The nanocluster source is activated for generating a beam of nanoclusters towards the substrate, and at least part of the nanoclusters are received atop the substrate. Thereby, a plurality of nanoclusters of controllable size are formed atop the substrate.

Abstract: A method for fabricating a potential barrier for a nitrogen-face (N-face) nitride-based electronic device, comprising using a thickness and polarization induced electric field of a III-nitride interlayer, positioned between a first III-nitride layer and a second III-nitride layer, to shift, e.g., raise or lower, the first III-nitride layer's energy band with respect to the second III-nitride layer's energy band by a pre-determined amount. The first III-nitride layer and second III-nitride layer each have a higher or lower polarization coefficient than the III-nitride interlayer's polarization coefficient.

Abstract: A nitride semiconductor device includes a first, a second, and a third nitride semiconductor layers that are laminated on a foundation semiconductor layer in stated order, the third nitride semiconductor layer having a wider band gap as compared with the second nitride semiconductor layer, a recess area that is dug from an upper surface of the third nitride semiconductor layer down to a middle of the second nitride semiconductor layer, a first electrode and a second electrode respectively formed on one side and the other side of the recess area so as to be in contact with one of the third nitride semiconductor layer and the second nitride semiconductor layer, a dielectric film formed on the third nitride semiconductor layer and an inner surface of the recess area, and a control electrode formed on the dielectric film in the recess area.

Abstract: An AlN buffer layer, an undoped GaN layer, an undoped AlGaN layer, a first p-AlGaN layer, a second p-AlGaN layer and a high concentration p-GaN layer are formed in this order on a substrate. A gate electrode establishes ohmic contact with the high concentration p-GaN layer. A source electrode and a drain electrode are formed on the undoped AlGaN layer. Two-dimensional electron gas generated at the interface between the undoped AlGaN layer and the undoped GaN layer and the first and second p-AlGaN layers form a pn junction in a gate region. The second p-AlGaN layer covers a SiN film in part.

Abstract: A group-III nitride compound semiconductor device of the present invention comprises a substrate, an intermediate layer provided on the substrate, and a base layer provided on the intermediate layer in which a full width at half maximum in rocking curve of a (0002) plane is 100 arcsec or lower and a full width at half maximum in rocking curve of a (10-10) plane is 300 arcsec or lower. Also, a production method of a group-III nitride compound semiconductor device of the present invention comprises forming the intermediate layer by using a sputtering method.

Abstract: A III-nitride device having a support substrate that may include a first silicon body, a second silicon body, an insulation body interposed between the first and second silicon bodies, and a III-nitride body formed over the second silicon body.

Abstract: Affords Group III nitride semiconductor devices in which the leakage current from the Schottky electrode can be reduced. In a high electron mobility transistor 11, a supporting substrate 13 is composed of AlN, AlGaN, or GaN, specifically. An AlYGa1?YN epitaxial layer 15 has a full-width-at-half maximum of (0002) plane XRD of 150 sec or less. A GaN epitaxial layer 17 is provided between the gallium nitride supporting substrate and the AlYGa1?YN epitaxial layer (O<Y?1). A Schottky electrode 19 is provided on the AlYGa1?YN epitaxial layer 15. The Schottky electrode 19 constitutes a gate electrode of the high electron mobility transistor 11. The source electrode 21 is provided on the gallium nitride epitaxial layer 15. The drain electrode 23 is provided on the gallium nitride epitaxial layer 15.

Abstract: In an electronic device of the present invention a gate Schottky electrode is formed on an active layer constructed of a GaN layer and an AlGaN layer, and a source ohmic electrode and a drain ohmic electrode are further formed on both sides of the gate Schottky electrode on the active layer. A dielectric layer (TiO2 layer) of a stepwise laminate structure is formed on the AlGaN layer so that the electric field distribution between the gate Schottky electrode and the drain ohmic electrode is substantially uniformed. The dielectric constant of TiO2 of the dielectric layer is made higher than the dielectric constant of GaN and AlGaN of the active layer.

Abstract: A method for growing a semi-polar nitride semiconductor thin film via metalorganic chemical vapor deposition (MOCVD) on a substrate, wherein a nitride nucleation or buffer layer is grown on the substrate prior to the growth of the semi-polar nitride semiconductor thin film.

Abstract: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A III-nitride based integrated semiconductor device which includes at least two III-nitride based semiconductor devices formed in a common die.

Abstract: The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device.

Abstract: An object of the present invention is to obtain a group III nitride compound semiconductor stacked structure where a group III nitride compound semiconductor layer having good crystallinity is stably stacked on a dissimilar substrate. The group III nitride compound semiconductor stacked structure of the present invention is a group III nitride compound semiconductor stacked structure comprising a substrate having provided thereon a first layer comprising a group III nitride compound semiconductor and a second layer being in contact with the first layer and comprising a group III nitride compound semiconductor, wherein the first layer contains a columnar crystal with a definite crystal interface and the columnar crystal density is from 1×103 to 1×105 crystals/?m2.

Abstract: An undoped GaN layer, a silicon film, an n type GaN layer, an MQW active layer and a p type GaN layer are stacked sequentially in this order on an AlN buffer layer formed on a sapphire substrate. In this manner, the silicon film is formed in the mid-section of the GaN layers. The AlN buffer layer is crystal-grown at a high temperature. The construction is formed such that a reflectivity of light from a crystal-growing surface is once decreased in a crystal-growing process of the n type GaN layer formed on the silicon film, and the reflectivity of light is increased from the crystal-growing surface in a crystal-growing process of a nitride semiconductor layer to be formed on the n type GaN layer.

Abstract: A forward light monitoring photodiode having a high reflection film with low dark current for detecting forward light emitted from a laser diode and power of the laser diode in spite of the change of temperatures or yearly degradation. The high reflection film is made by depositing an SiON layer upon an InP window layer or an InP substrate by a plasma CVD method. Al2O3/Si reciprocal layers or Al2O3/TiO2 reciprocal layers are produced upon the SiON layer. The high reflection film reflects 80%-90% of a 45 degree inclination incidence beam and allows 20%-10% of the incidence beam to pass the film and arrive at the InP window or substrate.

Abstract: A method for fabricating a bipolar transistor includes forming collector, base, and emitter semiconductor layers on a substrate such that the layers form a vertical sequence with respect to an adjacent surface of the substrate. The method includes etching away a portion of a top one of the semiconductor layers to expose a portion of the base semiconductor layer and then, growing semiconductor on the exposed portion of the base layer. The top one of the semiconductor layers is the layer of the sequence that is located farthest from the substrate. The growing causes grown semiconductor to laterally surround a vertical portion of the top one of the semiconductor layers.

Abstract: Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased.

Abstract: The object of the invention is to reduce the deterioration of crystallinity in the vicinity of an active layer when C, which is a p-type dopant, is doped and to suppress the diffusion of Zn, which is a p-type dopant, into an undoped active layer, thus to realize a sharp doping profile. When a Zn-doped InGaAlAs layer having favorable crystallinity is provided between a C-doped InGaAlAs upper-side guiding layer and an undoped active layer, the influence of the C-doped InGaAlAs layer whose crystallinity is lowered can be reduced in the vicinity of the active layer. Further, the Zn diffusion from a Zn-doped InP cladding layer can be suppressed by the C-doped InGaAlAs layer.

Abstract: A semiconductor optical device comprises a first conductive type III-V compound semiconductor layer, a second conductive type III-V compound semiconductor layer, and an active region. The first conductive type III-V compound semiconductor layer is provided on a substrate. The second conductive type III-V compound semiconductor layer is provided on the substrate. The active region is provided between the first conductive type III-V compound semiconductor layer and the second conductive type III-V compound semiconductor layer. The active region includes a III-V compound semiconductor layer. The III-V compound semiconductor layer contains nitrogen and arsenic as V-group element. The hydrogen concentration of the III-V compound semiconductor layer is greater than 6×1016 cm?3. The III-V compound semiconductor layer of the active region is doped with n-type dopant.

Abstract: A field effect transistor including an i-type first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer and having a band gap energy higher in magnitude than that of the first semiconductor layer. The first semiconductor layer and second semiconductor layer are each made of a gallium nitride-based compound semiconductor layer. A gate electrode is formed on the second semiconductor layer and a second electrode is formed on the first semiconductor layer. Thus, the field effect transistor is constructed in such a manner as the first semiconductor layer and second semiconductor layer are interposed between the gate electrode and the second electrode. Thus field effect transistor is able to discharge the holes that are accumulated in the channel from the elemental structure and to improve the withstand voltage of the field effect transistor.

Abstract: Provides is a compound semiconductor substrate about which the thickness of its nitride semiconductor single crystal layer can be made large while the generation of cracks, crystal defects or the like is restrained in the nitride semiconductor single crystal layer. The substrate has a first intermediate layer 110 formed on a Si single crystal substrate 100 having a crystal plane orientation of {111}. In the layer 110, a first metal compound layer 110a made of any one of TiC, TiN, VC and VN, and a second metal compound layer 110b made of any one of compounds which are different from the compound of the first metal compound layer out of TiC, TiN, VC and VN are laminated in this order alternately each other over the Si single crystal.

Abstract: A manufacturing method and a semiconductor device produced by the method are provided, in which the semiconductor device can easily be manufactured while the hydrogen concentration is decreased. An N-containing InGaAs layer 3 is grown on an InP substrate by the MBE method, and thereafter a heat treatment is provided at a temperature in the range of 600° C. or more and less than 800° C., whereby the average hydrogen concentration of the N-containing InGaAs layer 3 is made equal to or 2×1017/cm3 or less than.

Abstract: A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body.

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).

Abstract: A III-nitride bidirectional switch which includes an AlGaN/GaN interface that obtains a high current currying channel. The bidirectional switch operates with at least one gate that prevents or permits the establishment of a two dimensional electron gas to form the current carrying channel for the bidirectional switch.

Abstract: A method of fabricating a thick gallium nitride (GaN) layer includes forming a porous GaN layer having a thickness of 10-1000 nm by etching a GaN substrate in a reaction chamber in an HCI and NH3 gas atmosphere and forming an in-situ GaN growth layer in the reaction chamber. The method of forming the porous GaN layer and the thick GaN layer in-situ proceeds in a single chamber. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN etching and growth are performed using an HVPE process gas such that costs are greatly reduced.

Abstract: The present invention provides nitride semiconductors having a moderate density of basal plane stacking faults and a reduced density of threading dislocations, various products based on, incorporating or comprising the nitride semiconductors, including without limitation substrates, template films, templates, heterostructures with or without integrated substrates, and devices, and methods for fabrication of templates and substrates comprising the nitride semiconductors.

Abstract: A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

Abstract: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode.

Abstract: A method for fabricating nitrogen-face (N-face) nitride-based electronic devices with low buffer leakage, comprising isolating a buffer from a substrate with an AlGaInN nucleation layer to suppress impurity incorporation from the substrate into the buffer. A method for fabricating N-face nitride-based electronic devices with low parasitic resistance and high breakdown, comprising capping a device structure with a conductive layer to provide extremely low access and/or contact resistances, is also disclosed.

Abstract: High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.

Abstract: A doped semiconductor junction for use in an electronic device and a method for making such junction is disclosed. The junction includes a first polycrystalline semiconductor layer doped with donors or acceptors over a substrate such that the first doped semiconductor layer has a first polarity, the first layer including fused semiconductor nanoparticles; and a second layer in contact with the first semiconductor layer over a substrate to form the semiconductor junction.

Abstract: A laser diode includes a first n-cladding layer disposed on and lattice-matched to an n-semiconductor substrate, wherein the first n-cladding layer is n-AlGaInP or n-GaInP; a second n-cladding layer of n-AlGaAs supported by the first n-cladding layer; and an inserted layer disposed between the first n-cladding layer and the second n-cladding layer, wherein the inserted layer includes the same elements as the first n-cladding layer, the inserted layer has the same composition ratios of Al and Ga (and P) as the first n-cladding layer, and the inserted layer contains a lower composition ratio of In than the first n-cladding layer.

Abstract: A GaN layer is grown on a sapphire substrate, an SiO2 film is formed on the GaN layer, and a GaN semiconductor layer including an MQW active layer is then grown on the GaN layer and the SiO2 film using epitaxial lateral overgrowth. The GaN based semiconductor layer is removed by etching except in a region on the SiO2 film, and a p electrode is then formed on the top surface of the GaN based semiconductor layer on the SiO2 film, to join the p electrode on the GaN based semiconductor layer to an ohmic electrode on a GaAs substrate. An n electrode is formed on the top surface of the GaN based semiconductor layer.

Abstract: The semiconductor laser of this invention includes an active layer formed in a c-axis direction, wherein the active layer is made of a hexagonal-system compound semiconductor, and anisotropic strain is generated in a c plane of the active layer.

Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.

Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.

Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.

Abstract: Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode.

Abstract: A thin film device includes a metal sulfide layer formed on a single crystal silicon substrate by epitaxial growth; and a compound thin film with ionic bonding, which is formed on the metal sulfide layer by epitaxial growth. Alternatively, a thin film device includes a metal sulfide layer formed on a single crystal silicon substrate by epitaxial growth; and at least two compound thin films with ionic bonding, which are formed on the metal sulfide layer by epitaxial growth. For example, (11 20) surface AlN/MnS/Si (100) thin films formed by successively stacking a MnS layer (about 50 nm thick) and an AlN layer (about 1000 nm thick) on a single crystal Si (100) substrate, are used as a substrate, and a (11 20) surface GaN layer (about 100 nm thick) operating as a light emitting layer is formed on the substrate, thereby fabricating a thin film device.

Abstract: A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InGaAsP (including zero As content)guide layer without added dopant impurities, a p-type AlGaInP cladding layer, a p-type band discontinuity reduction layer, and a p-type GaAs contact layer sequentially laminated on an n-type GaAs substrate C or Mg is the dopant impurity in the p-type GaAs contact layer, the p-type band discontinuity reduction layer, and the p-type AlGaInP cladding layer.

Abstract: An electric-field control electrode (5) is formed between a gate electrode (2) and a drain electrode (3). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed below the electric-field control electrode (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered with the SiN film (21).

Abstract: A method for fabricating a non-planar heterostructure field effect transistor using group III-nitride materials with consistent repeatable results is disclosed. The method provides a substrate on which at least one layer of semiconductor material is deposited. An AlN layer is deposited on the at least one layer of semiconductor material. A portion of the AlN layer is removed using a solvent to create a non-planar region with consistent and repeatable results. The at least one layer beneath the AlN layer is insoluble in the solvent and therefore acts as an etch stop, preventing any damage to the at least one layer beneath the AlN layer. Furthermore, should the AlN layer incur any surface damage as a result of the reactive ion etching, the damage will be removed when exposed to the solvent to create the non-planar region.

Abstract: A photodetector is described. The photodetector is comprised of a substrate, a first n-type III-V compound semiconductor layer located on the substrate, an n++-type III-V compound semiconductor layer located on a first portion of the first n-type III-V compound semiconductor layer with a second portion of the first n-type III-V compound semiconductor layer exposed, a p-type III-V compound semiconductor layer located on the n++-type compound semiconductor layer, an undoped III-V compound semiconductor layer located on the p-type III-V compound semiconductor layer, a second n-type III-V compound semiconductor layer located on the undoped III-V compound semiconductor layer, a conductive transparent oxide layer located on the second n-type III-V compound semiconductor layer, a first electrode located on a portion of the conductive transparent oxide layer, and a second electrode located on a portion of the second portion of the first n-type III-V compound semiconductor layer.

Abstract: An optical device with a quantum well is provided. The optical device includes an active layer made of a Group III-V semiconductor compound and having a quantum well of a bandgap grading structure in which conduction band energy and valence band energy change linearly with a slope with the content change of predetermined components while an energy bandgap between the conduction band energy and the valence band energy is maintained at a predetermined value; and two barrier layers, one of which is positioned on an upper surface of the active layer and the other is positioned on a lower surface of the active layer, and which are made of a Group III-V semiconductor compound and have higher conduction band energy and lower valence band energy than the active layer. A driving voltage is decreased and luminous efficiency and reliability are enhanced.