Abstract: There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memory cells sharing a source, and disposed at symmetrical positions, respectively, and two lengths of metal interconnections (the bit lines) are disposed with respect to a width in the direction of a channel width of a region occupied by one of the memory cells. In contrast, respective control gates of the memory cells corresponding to two word are rendered at an identical potential, and respective memory gates thereof are rendered at an identical potential, thereby disposing three lengths of metal interconnections (a control gate control line, memory gate control line, and common source line) with respect to a length of the regions occupied by the two memory cells in the direction of a channel length.

Abstract: High resistance elements of 5 K? or more are connected near first and second control terminals between the first and second control terminals and respective crossing portion of first and second connectings. Even when a high frequency analog signal transmitted in a pad wire leaks to the first and second connectings, the high frequency analog signal is attenuated by the high resistance elements. Accordingly, the high frequency analog signal is not substantially transmitted to control terminal pads. It is therefore possible to suppress an increase in insertion loss.

Abstract: The semiconductor apparatus includes a pad; a first line layer placed immediately beneath the pad; and a lattice-shaped contact being between the pad and the first line layer.

Abstract: A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A layout for a transistor in a standard cell is disclosed. The layout for a transistor includes an active region with at least one portion having a first edge and at least one portion having a second edge all perpendicular to a channel of the transistor; and a gate placed on top of the active region with a distance from an edge of the gate to the first edge being shorter than a distance from the edge of the gate to the second edge of the active region, wherein the active region is of a non-rectangular shape.

Abstract: An interconnect includes an opening formed in a dielectric layer. A conductive barrier is deposited in the opening, over which a first conductive layer is deposited. A conductive oxide is deposited over the first conductive layer, and a second conductive layer, formed from the same material as the first conductive layer, is deposited over the conductive liner.

Abstract: In a first functional block, a source voltage input terminal of a PMOS transistor and a substrate voltage input terminal of an NMOS transistor are connected to their voltage supply terminals, respectively. The substrate voltage input terminal of the PMOS transistor in the ith (1?i?n?1) functional block and the source voltage input terminal of the NMOS transistor therein are connected bijectively with the source voltage input terminal of the PMOS transistor in the i+1th functional block and the substrate voltage input terminal of the NMOS transistor therein. In the nth functional block, the substrate voltage input terminal of the PMOS transistor and the source voltage input terminal of the NMOS transistor are connected to their voltage supply terminals, respectively.

Abstract: A direct-connect signaling system including a printed circuit board and first and second integrated circuit packages disposed on the printed circuit board. A plurality of electric signal conductors extend between the first and second integrated circuit packages suspended above the printed circuit board.

Abstract: A semiconductor device of the present invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage, a ground voltage and a sub-ground voltage are supplied; a driver for generating the sub-power supply voltage and the sub-ground voltage based on the power supply voltage and the ground voltage; a first wiring layer including a sub-power supply line for supplying the sub-power supply voltage and a sub-ground line for supplying the sub-ground voltage; a second wiring layer including source/drain lines for MOS transistors; a third wiring layer including a main power supply line for supplying the power supply voltage and a main ground line for supplying the ground voltage and arranged opposite to the first wiring layer to sandwich the second wiring layer; via structures for connecting the source/drain lines of the second wiring layer to the other layers.

Abstract: A flat panel image display device comprises: a rear plate including plural electron emission elements; a face plate disposed opposed to the rear plate, fluorescent members being disposed on a surface of the face plate opposed to the rear plate, and the fluorescent members being covered with a metal back film; and a voltage applying unit to apply an acceleration voltage of 8 kV to 15 kV between the rear plate and the face plate, wherein the metal back film has a getter material, and a current luminance characteristic of the fluorescent member satisfies ??0.9 if L=kl? (L is luminance, l is an irradiation current, and k is a constant). Thus, a high contrast can be acquired even if electrons scattered backward again bombard and penetrate into the fluorescent member.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Abstract: A pixel structure is provided. The pixel structure comprises a scan line, a data line, a pixel electrode and a thin film transistor. The data line branches out into a plurality of subsidiary lines in the area above the scan line. If there is a short circuit between the scan line and the data line, the short circuit can be repaired by cutting the connections to one of the branching subsidiary lines. In one embodiment of this invention, a repair line is set up on one side of the data line such that a portion of the repair line crosses over the scan line. If there is a short circuit between the scan line and the data line, a laser repair operation can be carried out through the repair line.

Abstract: The present invention is provided with a transmission line element having a ground wiring and a power supply wiring formed interposing an insulating film, on the power supply wiring on a semiconductor chip, lead or printed-circuit board, such that the capacitance per unit length of the transmission line element is boosted to set the characteristic impedance of the transmission line element for the high frequency range to an optimum value. In this way, the power supply wiring inclusive of the transmission line element can have a satisfactory decoupling performance.

Abstract: The present invention includes the steps of forming a first resin film uncured on a wiring substrate including a wiring pattern, burying an electronic parts having a connection terminal on an element formation surface in the first resin film uncured in a state where the connection terminal is directed upward, forming a second resin film for covering the electronic parts, obtaining an insulation film by curing the first and second resin films by heat treatment, forming a via hole in a predetermined portion of the insulation film on the wiring pattern and the connection terminal, and forming an upper wiring pattern connected to the wiring pattern and the connection terminal through the via hole, on the insulation film.

Abstract: In general, this disclosure is directed to circuitry for implementation of headswitches and footswitches in an ASIC for power management. The disclosed circuitry supports not only effective power management, but also efficient use of ASIC area, reduced complexity, and the use of electronic design automation (EDA) tools. In this manner, the disclosed circuitry can support enhanced performance and simplified ASIC design. In some cases, headswitch or footswitch circuitry may be implemented as a switch pad ring that extends around a hard macro forming part of an ASIC core. In other cases, headswitch or footswitch circuitry can be distributed within an ASIC core by embedding distributed headswitch or footswitch components under metal layer power routing coupled to standard cell rows.

Abstract: A microelectronic complex including a body of semi-conductor material containing an integrated circuit, and a plurality of contact pads on the body for receiving signal conducting members for connection to an external substrate. The contact pads allow signals to be exchanged between the integrated circuit and the external substrate via the signal conducting members. A majority of the contact pads are disposed on the body of the microelectronic complex according to a configuration whereby the stress effects on the signal conducting members caused by thermal expansion mismatch between the microelectronic complex and the external substrate are minimized. In a specific configuration, a majority of the contact pads form a cluster circumscribing a predetermined area of the microelectronic complex body, whereby the cluster is characterized by a minimum inter-pad distance among the majority of contact pads on the body of the microelectronic complex.

Abstract: A semiconductor integrated circuit able to reduce a load of a layout design when arranging switches in power lines for preventing leakage current and able to reduce the influence of a voltage drop occurring in the switches on a signal delay, wherein a plurality of groups of power lines are arranged in stripe shapes, power is supplied to circuit cells by a plurality of groups of branch lines branching from the groups of power lines, power switch cells arranged in the groups of branch lines turn on or off the supply of power to the circuit cells, the power switch cells are arranged dispersed in the area of arrangement of the circuit cells, and the supply of power by the power switch cells is finely controlled for every relatively small number of circuit cells.

Abstract: A memory cell includes first and second data holding portions for holding stored data and its inverted data. First and second p channel TFT compensate for charges leaked from first and second capacitors, respectively. A first (second) access transistor has first and second gate electrodes connected to a first (second) word line and to a second (first) node, respectively. The first (second) access transistor discharges the charges leaked from a power supply node via the first (second) p channel TFT in the OFF state in the leakage mode where the first (second) word line is inactivated and the second (first) node is at an H level.

Abstract: A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

Abstract: Methods of supplying voltages to integrated circuits are provided. A high voltage VddH and/or a low voltage VddL can be supplied to a filler cell and routed to other cells. Each of the VddH and VddL is carried by one of a first voltage supply wire and a second voltage supply wire. A voltage routing wire routes desired voltage(s) to a filler cell. The first and the second voltage supply wires are preferably formed parallel to the voltage routing wire with their edges substantially aligned to the edges of the voltage routing wire. Vias are made to route the desire voltage. Also preferably, the first voltage supply wire is an M1 wire formed outside the filler cell while the second voltage supply wire is an M2 wire formed inside the filler cell.

Abstract: The invention provides an electro-optical device in which a voltage drop due to the wiring resistance of a cathode is reduced and therefore steady image signals are transmitted such that erroneous image display, such as low contrast, is reduced or prevented. The invention also provides an electronic apparatus including such an electro-optical device. An electro-optical device includes red, green, and blue luminescent power-supply lines to apply currents to light-emitting elements arranged in an actual display region in a matrix; and a cathode line disposed between the light-emitting elements and a cathode. The cathode line has a width larger than a width of red, green, and blue luminescent power-supply lines.

Abstract: A chip package is provided. The chip package includes at least one chip, an interconnection structure, a plurality of second pads and at least one panel-shaped component, wherein the chip includes a plurality of first pads on a surface thereof. The interconnection structure is disposed on the chip, and the first pads of the chip are electrically coupled to the interconnection structure. The second pads are disposed on the interconnection structure, and the panel-shaped component is embedded in the interconnection structure. The panel-shaped component also includes a plurality of electrodes on its two opposite surfaces, and the second pads are electrically coupled to the first pads of the chip through the interconnection structure and the panel-shaped component.

Abstract: There are provided a metal I/O ring structure for a semiconductor chip and a decoupling capacitance structure using the same. In the Metal I/O ring structure, a plurality of first metal lines are formed on a first metal layer and connected with a power supply voltage, and a plurality of second metal lines are formed on the first metal layer and connected with a ground voltage. The second metal lines are arranged neighboring to the first metal lines. The second metal lines are connected with a second metal layer disposed below the first metal lines on the metal layer, and the first metal lines are connected with the second metal layer disposed below the second metal lines on the first metal layer. An insulating layer is disposed between the first metal layer and the second metal layer, thereby forming a decoupling capacitance between the first metal lines and the second metal lines.

Abstract: A cell 100 includes three wiring layers (a gate electrode layer, a source/drain electrode layer and a terminal layer) on a semiconductor substrate including transistors formed thereon. One of the wiring layers (the terminal layer) in which input terminals 151 and output terminals 152 for connecting the cell to another cell are formed includes a power supply line passing region 153 through which a power supply line for supplying a power supply voltage and a ground voltage from an external power supply to the transistors in the cell can be provided.

Abstract: In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargement of the size of a cell. A power line for data retention for power shutdown is formed with wirings finer than a usual main power line. Preferably, power lines for a data retention circuit are considered as signal lines and wired by automatic placing and mounting. For this purpose, terminals for the power line for data retention are previously designed by providing the terminals therefor for the cell in the same manner as in the existent signal lines. Additional layout for power lines is no longer necessary for the cell, which enables a decrease in the area and design by an existent placing and routing tool.

Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.

Abstract: A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

Abstract: A semiconductor device includes a substrate having an active layer, an element region provided in the active layer, a P-type semiconductor region provided in the element region, and first and second N-type semiconductor regions provided in the element region, located on the sides of the P-type semiconductor region, respectively and spaced in a first direction. The device has an N-type MOS transistor and first and second P-type MOS transistors. The N-type MOS transistor has a first gate electrode provided on the P-type semiconductor region. The first P-type MOS transistor has a second gate electrode provided on the first N-type semiconductor region. The second P-type MOS transistor has a third gate electrode provided on the second N-type semiconductor region.

Abstract: According to a method of designing an integrated circuit, a plurality of outgoing lines branch off from each of main lines of respective power supply paths on the sides of VDD and VSS, and the pitches between adjacent outgoing lines of the plurality of outgoing lines are set so as to be equal to each other. Preferably, branching positions of the plural outgoing lines of one power supply path correspond to branching positions of the plural outgoing lines of another power supply path in the longitudinal direction of the power supply paths, or the lengths of the plural outgoing lines of one power supply path are set so as to be longer than the lengths of the plural outgoing lines of another power supply path.

Abstract: A multilayer metal supply rings structure of an integrated circuit comprises at least two parallel perimetral metal rails defined in metal layers of different levels, geometrically superposed one to the other. Each rail is constituted by using definition juxtaposed modules, each module defining on a metal layer parallel segments, longitudinally separated by a separation cut, of each rail, superposed rails of said multilayer structure constituting one supply node being electrically interconnected through a plurality of interconnection vias through dielectric isolation layers between different metal levels. A feature of the multilayer metal supply rings structure is that the segments of each of said perimetral metal rails modularly defined on each metal level belong alternately to one and another supply node upon changing the metal level. A process of defining a multilayer metal supply rings structure is also disclosed.

Abstract: A composite electronic component having a multi-layer wiring board, a first power terminal electrode, a second power terminal electrode, an external connection power supply terminal, a surface-mounted component, an insulator, and a power supply pattern. The first and the second power terminal electrodes are disposed on a first face of the multi-layer wiring board. The external connection power supply terminal is disposed on a second face opposite to the first face of the multi-layer wiring board and connected with the first power terminal electrode. The surface-mounted component is mounted on the first face of the multi-layer wiring board and connected with the first and the second power terminal electrodes at a first face thereof. The insulator covers at least a second face opposite to the first face of the surface-mounted component, the first power terminal electrode, and the second power terminal electrode with a first face thereof.

Abstract: Well bias circuitry for selectively biasing the voltages of the well areas of an integrated circuit. In one embodiment, the well bias circuitry includes a switching cell located in a row of cells of the integrated circuit for selectively coupling a voltage supply line to a well bias line. The switching cell may include two level shifters, each for providing a voltage to a gate of a coupling transistor to make the coupling transistor non conductive in response to an enable signal. The switching cells may be sequentially coupled such that the coupling transistors of each of the switching cells are not made conductive at the same time so as to reduce inrush current due to changing the well bias from a well bias voltage to a supply voltage. In one example, the switching cells may include delay circuitry for delaying the change in state of the enable signal before being provided to the next switching cell.

Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.

Abstract: A semiconductor device and a production method thereof capable of reducing warps of a semiconductor wafer when packaging at a wafer level in a SiP type semiconductor device, is configured that an insulating layer is formed by stacking a plurality of resin layers on a semiconductor chip formed with an electronic circuit, wiring layers are buried in the insulating layer and electrically connected to electrodes, and formation areas of the plurality of resin layers become gradually smaller from an area of an upper surface of the semiconductor chip as they get farther from the semiconductor chip, so that a side surface and an upper surface of each of the resin layers and the upper surface of the semiconductor chip form a stepwise shape.

Abstract: A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n?2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.

Abstract: A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field effect transistor having a second polysilicon gate electrode and formed in the second device region, a polysilicon pattern extending over the device isolation region from the first polysilicon gate electrode to the second polysilicon gate electrode, and a silicide layer formed on a surface of the first polysilicon gate electrode, a surface of said the polysilicon gate electrode and a surface of the polysilicon pattern so as to extend on the polysilicon pattern from the first polysilicon gate electrode to the second polysilicon gate electrode, the silicide layer having a region of increased film thickness on the polysilicon pattern, wherein the silicide layer has a surface protruding upward in the region of increased film thickness.

Abstract: A semiconductor device capable of effectively eliminating noise on multilayered power lines with a bypass capacitor. A first power line is connected to the bypass capacitor. A second power line is a line from which a part located above the bypass capacitor is removed. Contacts connect the first and second power lines. Therefore, noise appearing on the second power line travels to the first power line, resulting in effectively eliminating the noise with the bypass capacitor.

Abstract: The semiconductor regions for source and drain of unused p-channel type MISFETQp and the power supply wiring 2VDD are electrically connected and the semiconductor regions for source and drain of n-channel type MISFETQn and the power supply wiring 2VSS are electrically connected. Moreover, the switch elements 3SW1, 3SW2 are formed of the p-channel type MISFETQp and n-channel type MISFETQn in the basic cells and these switch elements 3SW1, 3SW2 are discretely arranged in the n-well NWL and p-well PWL. Thereby, noise generated in the wells can be reduced in the semiconductor device where the switch elements are provided between the power supply wiring and wells and the threshold voltage of transistor formed in the well can be controlled through the ON/OFF controls of such switch elements.

Abstract: The disclosed embodiments provide devices and methods for movably connecting module layers of an electronic device to discretely actuate a first predetermined operational mode while locking out other predetermined operational modes. In one embodiment, for example, an electronic device includes a first module layer movable in a first direction and a second module layer movably connected relative to the first module layer. Further, a third module layer is movably connected relative to the second module layer and movable in a second direction. Additionally, a locking member is engageable with the third module layer to prevent movement in the second direction during movement of the first module layer in the first direction. The locking member may also be engageable with the first module layer to prevent movement in the first direction during movement of the third module layer in the second direction.

Abstract: A semiconductor device and method of adding metal layers in a semiconductor device with signal reallocation are disclosed. The device has a first layer with a plurality of signal wires. A second layer adjacent to the first layer is also included that has a plurality of signal wires. The signal wires in the first and second layers are substantially parallel with each other. The signal wires are distributed between the first and second layer in a manner that reduces the wire capacitance and/or resistance thereby permitting higher frequency operation and lower power consumption in the device.

Abstract: A memory includes an insulating layer; a plurality of spaced-apart semiconductor lines formed on the insulating layer; and a plurality of spaced-apart conductive gate lines formed on the insulating layer. Each of the gate lines is disposed to intersect the plurality of semiconductor lines at a plurality of intersections. The semiconductor lines include a plurality of body regions disposed at the intersections, with each of the body regions including a channel formed from a silicon carbide material.

Abstract: To prevent short-circuit due to contact of bonding wires each other and to make a semiconductor device compact. A semiconductor chip with a rectangular main surface may comprise: a first side composing the main surface; a second side opposed to the first side; a main electrode pad group composed of a plurality of main electrode pads, which plurality of main electrode pads is arranged on the main surface along the first side; a first electrode pad group composed of a plurality of first electrode pads, which plurality of first electrode pads is arranged between the first side and the main electrode pad group; a second electrode pad group composed of a plurality of second electrode pads, which plurality of second electrode pads is arranged on the main surface along the second side; a first interconnection connecting the main electrode pad with the first electrode pad; and a second interconnection connecting the main electrode pad with the second electrode pad.

Abstract: A band gap circuit using NPN transistors (10, 12) having collectors connected to a power source voltage is employed, and transistor active regions of the NPN transistors (10, 12) and semiconductor elements constituting other signal processing circuits are integrated in the same floating block (19) with high voltage resistance. As a result, a reference voltage circuit used in the signal processing circuit can be integrated in a compact manner.

Abstract: An electronic power device of improved structure is fabricated with MOS technology to have a gate finger region and corresponding source regions on either sides of the gate region. This device has a first-level metal layer arranged to independently contact the gate region and source regions, and has a protective passivation layer arranged to cover the gate region. Advantageously, a wettable metal layer, deposited onto the passivation layer and the first-level metal layer, overlies said source regions. In this way, the additional wettable metal layer is made to act as a second-level metal.

Abstract: DRAM cells include a common drain region in an integrated circuit substrate and first and second source regions in the integrated circuit substrate, a respective one of which is laterally offset from the common drain region along respective first and second opposite directions. First and second storage nodes are provided on the integrated circuit substrate, a respective one of which is electrically connected to a respective one of the first and second source regions. The first and second storage nodes are laterally offset from the respective first and second source regions along the first direction.

Abstract: A multiple supply gate array structure facilitated by the provision of a shared n-well and an isolated n-well is described. The gate array structure allows implementation of a single voltage circuit or a multiple voltage circuit. In addition, the gate array structure allows metal reprogram to provide standard logic functions, or special logic functions such as a buffer function for a signal crossing a voltage island boundary. Other special logic functions may include, for example, a level-shifter function or a fence-hold function.

Abstract: A wafer-level package includes a semiconductor wafer having at least one semiconductor chip circuit forming region each including a semiconductor chip circuit each provided with test chip terminals and non test chip terminals, at least one external connection terminal, at least one redistribution trace provided on the semiconductor wafer, at least one testing member, and an insulating material. A first end of the redistribution trace is connected to one of the test chip terminals and a second end of said redistribution trace is extended out to a position offset from the chip terminals. The testing member is provided in an outer region of the semiconductor chip circuit forming region, and the second end of the redistribution trace is connected to the testing member.