Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a third substrate of a second polarity different from the first polarity. The first substrate is insulated from a power source or ground to which a source of a MOSFET formed on the substrate is connected. The third substrate is disposed between the first and second substrates in adjacent relation to the first and second substrates. A circuit element is formed on the third substrate.

Abstract: A system for sensing a gas stream constituent comprises: (a) a thermally conductive, electrically insulative substrate, (b) a gas-sensing element mounted on the substrate and capable of sensing the constituent, (c) a reference element mounted on the substrate having electrical properties congruent with the gas-sensing element and being insensitive to the constituent, (d) an electronic circuit interconnecting the gas-sensing element and the reference element. The circuit is capable of actuating both of the elements and measuring the voltage difference between the elements. The voltage difference is proportional to the concentration of the constituent in the gas stream.

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode (2) of a first conductivity type; first semiconductor pillars (3, 4 and 5) with a gate insulating film (18) formed therearound, across the gate insulating film (18) the vertical MOS transistors facing the gate electrode; and a second semiconductor pillar (8) being of the first conductivity type which is the same as the conductivity type of the gate electrode and being in contact with the gate electrode at a portion thereof from which at least a part of the gate insulating film is removed, wherein potential supply (6) to the shared gate electrode (2) is effected through the second semiconductor pillar (8).

Abstract: Semiconductor devices are provided. A semiconductor device can include a substrate and a plurality of dummy line patterns on the substrate that extend in a first direction parallel with one another. Each of the dummy line patterns can include a plurality of sub-line patterns aligned along the first direction and which are separated from each other by at least one cutting region therebetween. The dummy line patterns can include first and second dummy line patterns which are adjacent to each other in a second direction that is perpendicular to the first direction. At least one of the cutting regions between a pair of sub-line patterns of the first dummy line pattern is aligned with and bounded by one of the sub-line patterns of the second dummy line pattern in the second direction.

Abstract: Methods and systems for optimal decoupling capacitance in a dual-voltage power-island architecture. In low-voltage areas of the chip, accumulation capacitors of two different types are used for decoupling, depending on whether the capacitor is located in an area which is always-on or an area which is conditionally powered.

Abstract: A layout method that enables a high power switch mode voltage regulator integrated circuit to generate a large output current and achieve substantially low switching loss is disclosed. The layout method includes forming an array of switching elements on a semiconductor die, each switching element including a plurality of discrete transistors configured to have a substantially reduced ON resistance; and forming a plurality of gate driver circuits on the same die among the switching elements, all using a single metal process. Each gate driver circuit placed substantially close to and dedicated to drive only one switching element so that the gate coupling capacitance resistance product is substantially reduced.

Abstract: With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.

Abstract: A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.

Abstract: In a semiconductor integrated circuit requiring a large number of pads, an internal circuit is arranged in the center portion, and a plurality of two kinds of I/O circuits for inputting and outputting signals from and to the outside and many pads are arranged along four sides of the semiconductor integrated circuit. The plurality of I/O circuits that are of one of the foregoing two kinds are one-pad I/O circuits on which one pad is arranged in a direction toward the internal circuit, whereas the plurality of I/O circuits that are of the other of the foregoing two kinds are two-pad I/O circuits on which two pads are arranged in zigzag relationship in a direction toward the internal circuit. The number of arranged pads equals to the number of pads required for the semiconductor integrated circuit. The one-pad I/O circuits and the two-pad I/O circuits are provided with power source wirings for supplying power thereto.

Abstract: An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective the plurality of IMD layers, wherein the first conductive layers comprise copper; a first passivation layer overlying the plurality of IMD layers and the plurality of first conductive layers; a plurality of first power/ground mesh wiring lines, formed in a second conductive layer overlying the first passivation layer, for distributing power signal or ground signal, wherein the second conductive layer comprise aluminum; and a second passivation layer covering the second conductive layer and the first passivation layer.

Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the central parts of the core power source regions 2, 3 and 5, on the left side of the core power source regions 4 to 8 and at the upper and lower parts of the semiconductor integrated circuit device 1. A power switch region for repeater 11 is formed so as to surround the core power source regions 2 to 8 and the repeater regions 10. The power source lines of the reference potential connected to the repeater regions 10 are laid out at equally spaced intervals throughout the core power source regions 2 to 8, which enables the repeater regions 10 to be flexibly laid out. This permits the repeaters to be more effectively arranged, which improves the performances of semiconductor integrated circuit device 1.

Abstract: A method for routing wires in an integrated circuit includes defining an even number n of initial width routing tracks in a selected routing channel. The n initial routing tracks are separated by a substantially equal first separation distance from the other routing tracks, Vss and Vdd in the routing channel. The n initial width routing tracks and the first separation distance have an initial width about equal to the minimum design width. An odd number of routing tracks less than n are then selected, the odd number of routing tracks have a second pitch greater than the first pitch, assigning the odd number of routing tracks in the routing channel. A third routing pitch can be defined that is wider than the second routing pitch for alternating routing tracks at the odd number of routing tracks if needed. A wire routing system in an integrated circuit is also described.

Abstract: An integrated circuit chip with reduced IR drop and improved chip performance is disclosed. The integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of copper metal layers embedded in respective the plurality of IMD layers; a first passivation layer overlying the plurality of IMD layers and the plurality of copper metal layers; a first power/ground ring of a circuit block of the integrated circuit chip formed in a topmost layer of the plurality of copper metal layers; a second power/ground ring of the circuit block of the integrated circuit chip formed in an aluminum layer over the first passivation layer; and a second passivation layer covering the second power/ground ring and the first passivation layer.

Abstract: An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight.

Abstract: A semiconductor IC-embedded module 100 comprises a multilayer substrate 101 having first and second insulating layers 101a and 101b, and a controller IC 012 and memory IC 103 that are embedded in the multilayer substrate 101. A wiring layer 104 is formed as an internal layer in the multilayer substrate 101. Part of the wiring layer 104 constitutes a bus line 104X. The controller IC 102 or memory IC 103 is embedded in the second insulating layer 101b. First and second ground layers 105a and 105b are provided respectively in the first and second insulating layers 101a and 101b. The effect of noise generated by bus lines is reduced, and an additional reduction in noise and a decrease in size and thickness are achieved by laying out bus lines that connect the semiconductor ICs so that distances are minimized.

Abstract: A double sliding-type portable communication apparatus, in which one housing slidably moves relative to the other housing through double-sliding motions, which includes a main housing extending in a longitudinal axis and a sliding housing moving in said longitudinal and also lateral directions across the main housing whose upper surface faces away from the main housing to allow the sliding housing may become displaced away from the main housing and also slidably return to overlap the main housing, wherein said housings are aligned parallel to each other in the longitudinal axis or a lateral direction across the main housing to expose predetermined regions of an upper surface of the main housing with keys provided thereon.

Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.

Abstract: The height H of several kinds of basic cell are made the same and several kinds of macro cell which have a length which is an integral multiplication of the height H of this basic cell, are prepared, the basic cell and macro cell are mixed and the circuit of a peripheral circuit is designed. A M0 wire of a first wiring layer which is formed on a semiconductor substrate is used as a wire used within a macro cell. The basic cell and the macro cell are connected by a M1 wire of a second wiring layer which is formed on the first wiring layer and a M2 wire M2 of a third wiring layer. The transistor layout of basic cells and macro cells is designed and verified in advance and stored in a cell library, and auto routing by a standard method may be carried out.

Abstract: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.

Abstract: A semiconductor integrated circuit device which is improved in wiring efficiency and area efficiency. Metal layers having respective portions protruding out from an N-type diffusion layer and a P-type diffusion layer in plan view toward respective sides of the diffusion layers opposed to each other are formed over the N-type diffusion layer and the P-type diffusion layer, respectively, and contact portions are formed over the upper surfaces of the protruding portions of the metal layers such that they extend parallel to a power supply line and a ground voltage line. This produces empty spaces over the regions of the upper surfaces of the metal layers, which makes it possible to arrange a large number of conductive traces, and enhance wiring efficiency and space efficiency.

Abstract: A cell array includes a semiconductor substrate including an active region comprising a first region, a second region, and a transition region, the second region being separated from the first region by the transition region, wherein a top surface of the second region is at a different level than a top surface of the first region. The cell array also includes a plurality of word lines crossing over the first region. The cell array also includes a selection line crossing over the active region, wherein at least a portion of the selection line is located over the transition region.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit having a chip layout that reduces line length to achieve faster processing. A cache comprises a TAG memory module and a cache data memory module. The cache data memory module is divided into first and second cache data memory modules which are disposed on both sides of the TAG memory module, and input/output circuits of a data TLB are opposed to the input/output circuit of the TAG memory module and the input/output circuits of the first and second cache data memory modules across a bus area to reduce the line length to achieve faster processing.

Abstract: A non-volatile memory array includes a multiplicity of memory cells, each of whose area is less than 4 F2 per cell (where F is a minimum feature size), and periphery elements to control the memory cells. The present invention also includes a non-volatile memory array which includes word lines and bit lines generally perpendicular to the word lines, with a word line pitch of less than 2 F. In one embodiment, the word lines are made of polysilicon spacers.

Abstract: A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness.

Abstract: A power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device. An embodiment describes the routing of a shield mesh of both power and ground lines to remove noise created by capacitive and inductive coupling. Relatively long signal lines are routed in between fully connected power and ground shield mesh which may be generated by a router during the signal routing phase or during power mesh routing phase. Leaving only the odd tracks or the even tracks for signal routing, power mesh (VDD) and ground mesh (VSS) are routed and fully interconnected leaving shorter segments and thereby reducing the RC effect of the circuit device. Another embodiment presents a technique where the signals are shielded using the power and ground mesh for a gridless routing. Another embodiment presents a multi-layer grid routing technique where signals are routed on even grid and the power and ground lines are routed on odd grid.

Abstract: A microelectronic unit has a structure including a microelectronic element such as a semiconductor chip with a first contact disposed remote from the periphery of the structure. The unit further includes first and second redistribution conductive pads disposed near a periphery of the structure and a conductive path incorporating first and second conductors extending toward the first contact, these conductors being connected to one another adjacent the first contact. The conductive path is connected to the first contact, and can provide signal routing from the periphery of the unit to the contact without the need for long stubs. A package may include a plurality of such units, which may be stacked on one another with the redistribution conductive pads of the various units connected to one another.

Abstract: A low power semiconductor memory device using a power gating is disclosed. The semiconductor memory device includes a standard cell and a power gating cell. The standard cell is provided with a virtual supply voltage and a first supply voltage. The power gating cell generates the virtual supply voltage from a second supply voltage and provides the standard cell with the virtual supply voltage in response to a control signal. The virtual supply voltage and the first supply voltage are provided by a first metal layer and the second supply voltage is provided by a third metal layer. The power gating cell may include at least one slice block and isolator blocks. The respective slice block has a transistor for switching current. The isolator blocks are arranged on both sides of the slice block and insulate the slice block from outside.

Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

Abstract: This invention discloses a integrated circuit (IC) chip having a plurality of modular cells, the chip comprises a first modular cell having a first metal layer, which contains at least two power lines independent of each other; and a second modular cell, juxtaposed to the first modular cell, also having the first metal layer, which contains at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first modular cell do not extend into the second modular cell, and all the power lines on the first metal layer serving the second modular cell do not extend into the first modular cell.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].

Abstract: Provided is a semiconductor device having a high-frequency interconnect, first dummy conductor patterns, an interconnect, and second dummy conductor patterns. The first dummy conductor patterns are arranged in the vicinity of the high-frequency interconnect, and the second dummy conductor patterns are arranged in the vicinity of the interconnect. The minimum value of distance between the high-frequency interconnect and the first dummy conductor patterns is larger than the minimum value of distance between the interconnect and the second dummy conductor patterns.

Abstract: In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer.

Abstract: The invention provides an electro-optical device in which a voltage drop due to the wiring resistance of a cathode is reduced and therefore steady image signals are transmitted such that erroneous image display, such as low contrast, is reduced or prevented. The invention also provides an electronic apparatus including such an electro-optical device. An electro-optical device includes red, green, and blue luminescent power-supply lines to apply currents to light-emitting elements arranged in an actual display region in a matrix; and a cathode line disposed between the light-emitting elements and a cathode. The cathode line has a width larger than a width of red, green, and blue luminescent power-supply lines.

Abstract: Using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise having a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Abstract: A method of forming air gaps within a solid structure is provided. In this method, a sacrificial material is covered by an overlayer. The sacrificial material is then removed through the overlayer to leave an air gap. Such air gaps are particularly useful as insulation between metal lines in an electronic device such as an electrical interconnect structure. Structures containing air gaps are also provided.

Abstract: Memory cells and semiconductor memory devices using the same. A substrate comprises two cross-coupled inverters and first and second pass-gate transistors formed therein, the inverters having a data storage node and a date bar storage node coupled to first terminals of the first and second pass-gate transistors. A first conductive layer is disposed on the substrate and comprises a bit line and a complementary bit line electrically connected to second terminals of the first and second pass-gate transistors respectively. A second conductive layer is disposed on the first conductive layer and comprises two first power lines covering the bit line and the complementary bit line respectively, wherein the first power lines, the bit line and the complementary bit line are parallel.

Abstract: Disclosed are a liquid crystal display and a substrate for the same. The substrate comprises first wires formed in one direction on the substrate; second wires intersecting and insulated from the first wires; pixel electrodes formed in pixel regions defined by the first wires and the second wires; and switching elements connected to the first wires, the second wires and the pixel electrodes, wherein an interval between two adjacent second wires has a predetermined dimension that repeatedly varies from one set of adjacent second wires to the next, and a side of the pixel electrodes adjacent to the second wires is shaped in a pattern identical to the second wires such that the pixel electrodes have a wide portion and a narrow portion.

Abstract: A semiconductor device that reduces the size and cost of functional macro chips used in a chip-on-chip configuration. Functional macro chips each include a macro region. The macro regions are formed adjacent to one another. A pad region for testing the functional macro chips is formed surrounding the macro regions.

Abstract: A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first voltage rail, a second source/drain adapted for connection to the second voltage rail, and a gate adapted for receiving a control signal. The MOS device selectively connects the first voltage rail to the second voltage rail in response to the control signal. The first and second voltage rails form a grid overlying the power switching circuit, the first and second voltage rails being formed in different planes relative to one another. The connection between the power switching circuit and the first voltage rail is made at an interface between the first and voltage rails.

Abstract: Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die or substrate with at least two IO buffers. One of the IO buffers is located a distance from a package pin and another of the IO buffers is located another distance from the package pin. One of the IO buffers includes first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type. In some cases, the floating bond pad is electrically coupled to the circuit implementing the second interface type via a conductive interconnect, and the floating bond pad is electrically coupled to the package pin.

Abstract: A fuse includes a fuse portion laid in such a manner that the direction of each turn of the fuse portion is parallel to the direction in which pads are arranged. The distance between the pads and the fuse portion is defined as the distance between the side of a pad facing the fuse portion and the pad nearest to the turn facing the particular side. The distance between the turn of the fuse portion and the nearest pad is the distance between the pads and the fuse portion. The pads and the fuse portion are distant from each other by a length at least ten times the width of the fuse.

Abstract: A semiconductor memory device is constructed to include a memory cell formed by a plurality of transistors, wherein each of gate wiring layers of all of the transistors forming the memory cell is arranged to extend in one direction.