Abstract: A semiconductor device including: a trench gate; a trench-bottom protecting layer of a second conductivity type provided in a semiconductor layer of a first conductivity type while contacting a bottom of trenches; and a depletion suppressing layer of the first conductivity type provided between adjacent trench-bottom protecting layers, wherein the depletion suppressing layer includes an intermediate point that is horizontally equidistant to the adjacent trench-bottom protecting layers and is formed of a size to contact neither the trenches nor the trench-bottom protecting layers, and an impurity concentration of the depletion suppressing layer is set higher than an impurity concentration of the semiconductor layer.

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to SiC super-junction (SJ) power devices. A SiC-SJ device includes a plurality of SiC semiconductor layers of a first conductivity-type, wherein a first and a second SiC semiconductor layer of the plurality of SiC semiconductor layers comprise a termination region disposed adjacent to an active region with an interface formed therebetween, an act wherein the termination region of the first and the second SiC semiconductor layers comprises a plurality of implanted regions of a second conductivity-type, and wherein an effective doping profile of the termination region of the first SiC semiconductor layer is different from an effective doping profile of the termination region of the second SiC semiconductor layer.

Abstract: A global shutter image sensor of a back-illuminated type includes a semiconductor substrate and pixels. Each pixel includes a photosensitive area, a storage area, a readout area and areas for transferring charges between these different areas. The image sensor includes, for each pixel, a protector extending at least partly into the substrate from the back of the substrate to ensure that the storage area is protected against back illumination.

Abstract: Each pixel region PX includes a photoelectric conversion region S1, a resistive gate electrode R, a first transfer electrode T1, a second transfer electrode T2, a barrier region B positioned directly beneath the first transfer electrode T1 in a semiconductor substrate 10, and a charge accumulation region S2 positioned directly beneath the second transfer electrode T2 in the semiconductor substrate 10. An impurity concentration of the barrier region B is lower than an impurity concentration of the charge accumulation region S2, and the first transfer electrode T1 and the second transfer electrode T2 are electrically connected to each other.

Abstract: Objects are to obtain a minute transistor by reducing the channel length L of a transistor used in a semiconductor integrated circuit such as an LSI, a CPU, or a memory, increase the operation speed of the circuit, and reduce power consumption. Oxide layers having compositions different from the composition of an oxide semiconductor layer including a channel formation region are provided below and over the oxide semiconductor layer, and in the oxide semiconductor layer including the channel formation region, low-resistance regions are provided to interpose the channel formation region therebetween in the lateral direction. The low-resistance regions are formed in a region other than the channel formation region so as to be in contact with a metal film or a metal oxide film by diffusion of a metal element (e.g., aluminum) contained in the metal or metal oxide films into the parts of the oxide semiconductor layer.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions. The nanowire structure has a first band gap energy section joined with a second band gap energy section. The first band gap energy section is coupled to the source region and has a band gap energy level greater than the band gap energy level of the second band gap energy section. The second band gap energy section is coupled to the drain region. The first band gap energy section comprises a first material and the second band gap energy section comprises a second material wherein the first material is different from the second material. The semiconductor device further comprises a gate region around the junction between the first band gap energy section and the second band gap energy section.

Abstract: A semiconductor device includes a first type region including a first conductivity type and a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a gate electrode surrounding at least some of the channel region. A first gate edge of the gate electrode is separated a first distance from a first type region edge of the first type region and a second gate edge of the gate electrode is separated a second distance from a second type region edge of the second type region. The first distance is less than the second distance.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.

Abstract: An MOSFET includes a silicon carbide substrate, an active layer, a gate oxide film, and a gate electrode. The active layer includes a body region where an inversion layer is formed at a region in contact with the gate oxide film by application of voltage to the gate electrode. The body region includes a low concentration region arranged at a region where an inversion layer is formed, and containing impurities of low concentration, and a high concentration region adjacent to the low concentration region in the carrier mobile direction in the inversion layer, arranged in a region where the inversion layer is formed, and containing impurities higher in concentration than in the low concentration region.

Abstract: A solid-state imaging device including, active elements configured to handle the charge captured in a photoreceiving region, an element isolation region configured to isolate regions of the active element, a first impurity region configured to surround the element isolation region, and a second impurity region including an impurity region lower in impurity concentration than the first impurity region, the second impurity region being provided between the first impurity region and active elements.

Abstract: A method of manufacturing an image pickup device includes a step of forming a filling member such that the filling member covers a light guiding part and a peripheral part provided in a film. The light guiding part is positioned on an image pickup region of the image pickup device and has openings that correspond to respective photoelectric conversion portions. The peripheral part is positioned on a peripheral region of the image pickup device. The filling member fills in the openings. The method includes a step of processing the filling member. The method includes a step of forming light guiding members, which is performed after the step of processing filling member has been performed, by a polishing process performed on the filling member so that the light guiding part is exposed. The light guiding members are part of the filling member and disposed in the openings.

Abstract: A solid-state imaging apparatus includes a plurality of pixels each including a photoelectric conversion unit and pixel transistors, which are formed on a semiconductor substrate; a floating diffusion unit in the pixel; a first-conductivity-type ion implantation area for surface pinning, which is formed over the surface on the side of the photoelectric conversion unit and the surface of the semiconductor substrate; and a second-conductivity-type ion implantation area for forming an overflow path serving as an overflow path for the floating diffusion unit, the second-conductivity-type ion implantation area being formed below the entire area of the first-conductivity-type ion implantation area. An overflow barrier is formed using the second-conductivity-type ion implantation area. A charge storage area is formed using an area in which the second-conductivity-type semiconductor area and the second-conductivity-type ion implantation area superpose each other.

Abstract: Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region.

Abstract: A CIS and a method of manufacturing the same, the CIS including a substrate having a first surface and second surface opposite thereto, the substrate including an APS array region including a photoelectric transformation element and a peripheral circuit region; an insulating interlayer on the first surface of the substrate and including metal wirings electrically connected to the photoelectric transformation element; a light blocking layer on the peripheral circuit region of the second surface of the substrate, exposing the APS array region, and including a plurality of metal wiring patterns spaced apart from one another to form at least one drainage path along a boundary region between the APS array region and the peripheral circuit region; a color filter layer on the second surface of the substrate covering the APS array region and the light blocking layer; and a microlens on the color filter layer on the APS array region.

Abstract: A FET includes a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile. A semiconductor manufacturing process produces a FET including a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile.

Abstract: A plurality of pixels PX include effective pixels and optical black pixels. Signal lines VL are provided corresponding to each column of the pixels PX and supplied with output signals of the pixels PX of the corresponding column. Clip transistors CL are provided corresponding to the respective signal lines VL and limit a potential of the corresponding vertical signal lines VL based on a gate potential. At least in a predetermined operating mode, a potential Vclip_dark is supplied to a gate of one of the clip transistors CL corresponding to at least one pixel column formed of the optical black pixels when reading a noise level from the pixels PX corresponding to the clip transistors CL and when reading a data level from the pixels PX corresponding to the clip transistors CL.

Abstract: An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

Abstract: An image sensor includes an active region including a photoelectric conversion region and a floating diffusion region, which are separated from each other, defined by a device isolation region on a semiconductor substrate, and a transfer transistor including a first sub-gate provided on an upper surface of the semiconductor substrate and a second sub-gate extending within a recessed portion of the semiconductor substrate on the active region between the photoelectric conversion region and the floating diffusion region, wherein the photoelectric conversion region includes a plurality of photoelectric conversion elements, which vertically overlap each other within the semiconductor substrate and are spaced apart from the recessed portion.

Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.

Abstract: Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

Abstract: A thin film transistor with favorable electric characteristics is provided. The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer which includes a microcrystalline semiconductor region and an amorphous semiconductor region, an impurity semiconductor layer, a wiring, a first oxide region provided between the microcrystalline semiconductor region and the wiring, and a second oxide region provided between the amorphous semiconductor region and the wiring, wherein a line tangent to the highest inclination of an oxygen profile in the first oxide region (m1) and a line tangent to the highest inclination of an oxygen profile in the second oxide region (m2) satisfy a relation of 1<m1/m2<10, on the semiconductor layer side from an intersection of a profile of an element included in the wiring and a profile of an element included in the semiconductor layer.

Abstract: According to one exemplary embodiment, an asymmetric transistor includes a channel region having a drain-side channel portion and a source-side channel portion. The asymmetric transistor can be an asymmetric MOSFET. The source-side channel portion can comprise silicon, for example. The drain-side channel portion can comprise germanium, for example. The asymmetric transistor comprises a vertical heterojunction situated between the drain-side channel portion and the source-side channel portion. According to this exemplary embodiment, the bandgap of the source-side channel portion is higher than the bandgap of the drain-side channel portion and the carrier mobility of the drain-side channel portion is higher than the carrier mobility of the source-side channel portion. The transistor can further include a gate oxide layer situated over the drain-side channel portion and the source-side channel portion, and can also include a gate situated over the gate oxide layer.

Abstract: A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2?) is formed on a substrate (1?). A p-type conductive layer (3?) is formed thereon. A second n-type conductive layer (4?) is formed thereon. On the under surface of the substrate (1?), there is a drain electrode (13?) connected to the first n-type conductive layer (2?). On the upper surface of the substrate (1?), there is a source electrode (11?) in ohmic contact with the second n-type conductive layer (4?), and a gate electrode (12?) in contact with the first n-type conductive layer (2?), p-type conductive layer (3?), the second n-type conductive layer (4?) through an insulation film (21?). The gate electrode (12?) and the source electrode (11?) are alternately arranged. The p-type conductive layer (3?) includes In.

Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Abstract: A lens forming method according to the present invention for forming lenses capable of focusing light on a plurality of respective photoelectric conversion sections constituting of a semiconductor apparatus is described. The method includes a lens forming step of processing a lens forming material, in which an average gradient of a ? curve indicating a residual film thickness with respect to the amount of irradiation light is between ?15 and ?0.8 nm·cm2/mJ within the range of a residual film ratio of 10 to 50% or within the range of the amount of irradiation light of 55 to 137 mJ/cm2 into a lens surface shape, using a photomask with an optical transmittance that is varied according to a lens surface shape, as an exposure mask.

Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.

Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.

Abstract: A semiconductor device has at least two main carbon-rich regions and two additional carbon-rich regions. The main carbon-rich regions are separately located in a substrate so that a channel region is located between them. The additional carbon-rich regions are respectively located underneath the main carbon-rich regions. The carbon concentrations is higher in the main carbon-rich regions and lower in the additional carbon-rich regions, and optionally, the absolute value of a gradient of the carbon concentration of the bottom portion of the main carbon-rich regions is higher than the absolute value of a gradient of the carbon concentration of the additional carbon-rich regions. Therefore, the leakage current induced by a lattice mismatch effect at the carbon-rich and the carbon-free interface can be minimized.

Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.

Abstract: A method of fabricating a transistor is provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.

Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor includes: a lower structure; a semiconductor layer formed on the lower structure and including a plurality of doping regions; a first insulating layer and a second insulating layer formed on the semiconductor layer and separated from each other; a third insulating layer formed on the first insulating layer and the second insulating layer; and a gate electrode layer formed between regions of the third insulating layer respectively corresponding to the first insulating layer and the second insulating layer.

Abstract: A multicolor CMOS pixel sensor formed in a p-type semiconductor region includes a first detector formed from an n-type region of semiconductor material located near the surface of the p-type region. A first pinned p-type region is formed at the surface of the p-type region over the first detector, and has a surface portion extending past an edge of the pinned p-type region. A second detector is formed from an n-type region located in the p-type semiconductor region below the first detector. A second-detector n-type deep contact plug is in contact with the second detector and extends to the surface of the p-type semiconductor region. A second pinned p-type region is formed at the surface of the p-type semiconductor region over the top of the second-detector n-type deep contact plug. A surface portion of the second-detector deep contact plug extends past an edge of the second pinned p-type region.

Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.

Abstract: Various illustrative embodiments of methods for manufacturing a semiconductor device are described. These methods may include, for example, forming a first polysilicon layer above a substrate, wherein the first polysilicon layer comprises a doped portion, and forming a second polysilicon layer over a surface of the first polysilicon layer. Also, various illustrative embodiments of semiconductor devices are described that may be manufactured such as by the various methods described herein.

Abstract: Disclosed are embodiments of a field effect transistor (FET) having decreased drive current temperature sensitivity. Specifically, any temperature-dependent carrier mobility change in the FET channel region is simultaneously counteracted by an opposite strain-dependent carrier mobility change to ensure that drive current remains approximately constant or at least within a predetermined range in response to temperature variations. This opposite strain-dependent carrier mobility change is provided by a straining structure that is configured to impart a temperature-dependent amount of a pre-selected strain type on the channel region. Also disclosed are embodiments of an associated method of forming the field effect transistor.

Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.

Abstract: First and second evaluation substrates are prepared, a direction perpendicular to a surface of the first evaluation substrate being defined by first indices, and the direction defined by the first indices being inclined from a normal direction of a surface of the second evaluation substrate. Ion implantation is performed for the first evaluation substrate in a vertical direction. Ion implantation is performed for the second evaluation substrate by using an ion beam parallel to the direction defined by the first indices. Impurity concentration distributions in a depth direction of the first and second evaluation substrates are measured. A first impurity concentration distribution on an extension line of an ion beam and a second impurity concentration distribution in a direction perpendicular to the extension line are predicted from the measured impurity concentration distributions of the first and second evaluation substrates.

Abstract: A transistor and a method of fabricating the same are provided. The transistor includes a SiGe epitaxial layer formed in a recess region of a substrate at both side of a gate electrode and a SiGe capping layer formed on the SiGe epitaxial layer. The transistor further includes a SiGe seed layer formed under the SiGe epitaxial layer and a silicon capping layer formed on the SiGe capping layer.

Abstract: A solid state imaging device includes a transfer transistor for transferring signal charges generated by photoelectric conversion to a floating diffusion layer, a reset transistor for resetting a potential of the floating diffusion layer, and an amplifying transistor for outputting a signal corresponding to the potential of the floating diffusion layer. A low concentration impurity region having an impurity concentration lower than that of the first conductivity type semiconductor region is formed in part of a surface portion of the first conductivity type semiconductor region which is located below a gate electrode of the amplifying transistor and serves as a well region of the amplifying transistor.

Abstract: Four regions (a narrow NMOS region, a wide NMOS region, a wide PMOS region, and a narrow PMOS region) are defined on a semiconductor substrate. Then, after a gate insulating film and a polysilicon film are sequentially formed on the semiconductor substrate, n-type impurities are introduced into the polysilicon film in the wide NMOS region. Next, by patterning the polysilicon film, gate electrodes are formed in the four regions. Then, n-type impurities are introduced into the gate electrodes in the narrow NMOS region and the wide NMOS region. As a result, an impurity concentration of the gate electrode in the narrow NMOS region becomes lower than that of the gate electrode in the wide NMOS region.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the standard cells, wherein each of the gate electrodes of the standard cells and the reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.

Abstract: A light-receiving element includes: a first-conductivity-type semiconductor region configured to be formed over an element formation surface; a second-conductivity-type semiconductor region configured to be formed over the element formation surface; an intermediate semiconductor region configured to be formed over the element formation surface between the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region, and have an impurity concentration lower than impurity concentrations of the first-conductivity-type semiconductor region and the second-conductivity-type semiconductor region. The light-receiving element further includes: a first electrode configured to be electrically connected to the first-conductivity-type semiconductor region; a second electrode configured to be electrically connected to the second-conductivity-type semiconductor region; and a control electrode configured to be formed in an opposed area that exists on the element formation surface.

Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.

Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.

Abstract: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a second polarity voltage on the gate of a transfer transistor during a charge integration period.

Abstract: A solid-state imaging device includes an N-type semiconductor substrate, an N-type impurity region provided in the surficial portion of the N-type semiconductor substrate, a photo-electric conversion unit formed in the N-type impurity region, a charge accumulation unit formed in the N-type impurity region so as to contact with the photo-electric conversion unit, and temporarily accumulating charge generated in the photo-electric conversion unit, a charge hold region (barrier unit) formed in the N-type impurity region so as to contact with the charge accumulation unit, and allowing the charge accumulation unit to accumulate the charge, and a charge accumulating electrode provided to the charge accumulation unit. The charge accumulation unit and the charge hold region are formed to be N?-type.

Abstract: A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.