Majority Signal Carrier (e.g., Buried Or Bulk Channel, Or Peristaltic) Patents (Class 257/216)
  • Patent number: 11081424
    Abstract: Embodiments of the present invention are directed to microchannels having varied critical dimensions for efficient cooling of semiconductor integrated circuit chip packages. In a non-limiting embodiment of the invention, a patterning stack is formed over a substrate. The patterning stack includes a hard mask, an etch transfer layer on the hard mask, and a photoresist on the etch transfer layer. A manifold trench is formed in a first region of the substrate and is recessed below a surface of the etch transfer layer. A microchannel trench is formed in a second region of the substrate to expose the surface of the etch transfer layer. The manifold trench and the microchannel trench are recessed such that the manifold trench extends into the hard mask and the microchannel trench extends into the etch transfer layer. A manifold and a microchannel are formed in the substrate by pattern transfer.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ravi K. Bonam, Kamal K. Sikka, Joshua M. Rubin, Iqbal Rashid Saraf, Fee Li Lie
  • Patent number: 11043431
    Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Mingo Liu
  • Patent number: 10446547
    Abstract: The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuites.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: October 15, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober
  • Patent number: 10283506
    Abstract: The present invention relates to an improvement to a current field effect transistor and trans-impedance MOS devices based on a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. The present invention further relates to a super-saturation current field effect transistor (xiFET), having a source, a drain, a diffusion, a first gate, and a second gate terminals, in which a source channel is defined between the source and diffusion terminals, a drain channel is defined between the drain and diffusion terminals. The first gate terminal is capacitively coupled to the source channel; and the second gate terminal is capacitively coupled to said drain channel. The diffusion terminal receives a current causing change in diffused charge density throughout said source and drain channel. The xiFET provides a fundamental building block for designing various analog circuits.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 7, 2019
    Assignee: Circuit Seed, LLC
    Inventors: Susan Marya Schober, Robert C. Schober
  • Patent number: 10262902
    Abstract: The multiplexer includes a plurality of transmission gates each formed by four-terminal double insulated gate N-type and P-type field effect transistors connected in parallel. One of gates of the N-type gate field effect transistor is connected to a first threshold voltage control node, and a first resistor is connected between the first threshold voltage control node and a first threshold voltage control voltage source. One of gates of the P-type gate field effect transistor is connected to a second threshold voltage control node, and a second resistor is connected between the second threshold voltage control node and a second threshold voltage control voltage source.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: April 16, 2019
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihiro Sekigawa, Masakazu Hioki, Hanpei Koike
  • Patent number: 10205016
    Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser, Detlef Weber, Karl-Heinz Gebhardt
  • Patent number: 10151845
    Abstract: A photon counting system includes a photon sensor, a charge-sensitive amplifier (CSA) and an analog-to-digital converter (ADC). The CSA is configured to convert photon energy detected by the photon sensor to voltage pulses. The ADC is configured to digitize the voltage pulses generated by the CSA. The ADC includes successive approximation circuitry. The successive approximation circuitry includes an N-bit digital-to-analog converter (DAC), an N-bit successive approximation register (SAR), a plurality of N-bit registers, and a multiplexer configured to selectively route outputs of the SAR and outputs of the N-bit registers to the DAC for conversion to an analog signal.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 11, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rakul Viswanath, Nagesh Surendranath, Goli Sravana Kumar
  • Patent number: 10024900
    Abstract: Systems, methods, and devices of the various embodiments provide a field effect transistor (FET) that controls equilibrium by reversing the effects of leakage currents affecting the gate response of the FET by using an equilibrium pump electrode. The equilibrium reversing gate FETs (ergFETs) of the various embodiments, may include an equilibrium pump electrode located within a non-conducting gap. The ergFETs of the various embodiments may provide solid state ephemeral electric potential and electric field sensor systems and methods for measuring ephemeral electric potentials and electric fields.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: July 17, 2018
    Assignee: UNITED STATES OF AMERICA AS REPRESENTED BY THE ADMINISTRATOR OF NASA.
    Inventor: Edward R. Generazio
  • Patent number: 9984621
    Abstract: An image display device includes: a pixel array part formed of first to fourth scanning lines arranged in rows, signal lines arranged in columns, pixel circuits in a matrix connected to the scanning lines and signal lines, and a plurality of power source lines which supplies first to third potentials necessary for the operations of pixel circuit; a signal part which supplies a video signal to the signal lines; and a scanner part which supplies a control signal to the first to fourth scanning lines, and in turn scans the pixel circuit for every row, wherein the pixel circuits include a sampling transistor, a drive transistor, first to third switching transistors, a pixel capacitance, and a light emitting device, and a channel length of the drive transistor is made longer than a channel length of the switching transistors to suppress fluctuations in threshold voltage.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: May 29, 2018
    Assignee: Sony Corporation
    Inventors: Junichi Yamashita, Yutaka Mitomi, Tetsuo Minami, Takao Tanikame
  • Patent number: 9985025
    Abstract: An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 29, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Il Kim, Seung-Jin Mun, Kwang-Yong Yang, Young-Mook Oh, Ah-Young Cheon, Seung-Mo Ha
  • Patent number: 9985107
    Abstract: A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu, Chen Zhang
  • Patent number: 9966383
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a semiconductor substrate, a non-volatile memory cell, and a gate stack. The non-volatile memory cell is formed in the semiconductor substrate, and a top surface of the non-volatile memory cell is coplanar with or below a top surface of the semiconductor substrate. The gate stack is formed on the semiconductor substrate.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Ko-Chi Chen, Shen-De Wang
  • Patent number: 9911845
    Abstract: A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the substrate. The first doped region and the second doped region are in the substrate. The first doped region and the second doped region are of a same conductivity type and separated by the gate. The length of the first doped region is greater than a length of the second doped region in a direction substantially perpendicular to a channel length defined between the first doped region and the second doped region.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ker-Hsiao Huo, Kong-Beng Thei, Chien-Chih Chou, Yi-Min Chen, Chen-Liang Chu
  • Patent number: 9807323
    Abstract: An imaging system includes a plurality of pixel circuits each having a photodiode, a biasing circuit and a charge-to-voltage converter. The photodiode is configured to generate charges in response to light or radiation. The biasing circuit is configured to provide a constant bias voltage across the photodiode so as to drain the charges generated by the photodiode. The charge-to-voltage converter is configured to accumulate the charges drained by the biasing circuit and convert the accumulated charges into a corresponding output voltage.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 31, 2017
    Assignee: VAREX IMAGING CORPORATION
    Inventors: Arundhuti Ganguly, Pieter Gerhard Roos
  • Patent number: 9666485
    Abstract: A semiconductor device is disclosed. The device includes an epitaxial layer on a substrate, wherein the epitaxial layer includes first trenches and second trenches alternately arranged along a first direction. The epitaxial layer between the adjacent first and second trenches includes a first doping region and a second doping region, and the first doping region and the second doping region have different conductivity types. An interface is between the first doping region and the second doping region to form a super-junction structure. A gate structure is on the epitaxial layer. The epitaxial layer under the gate structure includes a channel extending along a second direction, and the first direction is perpendicular to the second direction.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: May 30, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang, Hsiung-Shih Chang
  • Patent number: 9640704
    Abstract: A photodetector including a photoelectric conversion structure made of a semiconductor material and, on a light-receiving surface of the conversion structure, a stack of first and second diffractive elements, the second element being above the first element, wherein: the first element includes at least one pad made of a material having an optical index n1, laterally surrounded with a region made of a material having an optical index n2 different from n1; the second element includes at least one pad made of a material having an optical index n3, laterally surrounded with a region made of a material having an optical index n4 different from n3; the pads of the first and second elements are substantially vertically aligned; and optical index differences n1?n2 and n3?n4 have opposite signs.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 2, 2017
    Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics SA
    Inventors: Laurent Frey, Michel Marty
  • Patent number: 9590066
    Abstract: Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Ramaswamy, Kirk D. Prall, Wayne Kinney
  • Patent number: 9553679
    Abstract: A method and system for processing a signal in the RF environment is disclosed. The method includes using an Analog Radio Frequency Memory (ARFM) to store an analog amplitude representation of the signal in the form of elemental charge packets. The stored signal is played back by converting the elemental charge packets back to their representative voltages to rejuvenate the original signal.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: January 24, 2017
    Assignee: BAE Systems Information and Electronic Systems Integrations Inc.
    Inventor: Julius Insler
  • Patent number: 9437694
    Abstract: A transistor is formed by defining a gate stack on top of a semiconductor layer. The gate stack includes a gate dielectric and a gate electrode. A layer of a first dielectric material, having a first dielectric constant, is deposited on side walls of the gate stack to form sacrificial sidewall spacers. Raised source-drain regions are then epitaxially grown on each side of the gate stack adjacent the sacrificial sidewall spacers. The sacrificial sidewall spacers are then removed to produce openings between each raised source-drain region and the gate stack. A layer of a second dielectric material, having a second dielectric constant less than the first dielectric constant, is then deposited in the openings and on side walls of the gate stack to form low-k sidewall spacers.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 6, 2016
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Clement Gaumer, Daniel Benoit
  • Patent number: 9435948
    Abstract: Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a <110> crystallographic direction to a <100> crystallographic direction.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Robert K. Leidy, Mark D. Levy, Qizhi Liu, Gary L. Milo, Steven M. Shank
  • Patent number: 9368616
    Abstract: The semiconductor device includes: a semiconductor layer in which a trench is formed having a side surface and a bottom surface; a second conductivity-type layer formed on the semiconductor layer on the side surface and the bottom surface of the trench; a first conductivity-type layer formed on the semiconductor layer so as to contact the second conductivity-type layer; a first electrode electrically connected to the first conductivity-type layer; a second electrode embedded in the trench and electrically connected to the second conductivity-type layer; and a barrier-forming layer which is arranged between the second electrode and the side surface of the trench and which, between said barrier-forming layer and the second conductivity-type layer, forms a potential barrier higher than the potential barrier between the second conductivity-type layer and the second electrode.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: June 14, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Hiroyuki Sakairi
  • Patent number: 9171847
    Abstract: A semiconductor structure includes a semiconductor substrate, an active area in the semiconductor substrate, two trenches intersecting the active area to thereby divide the active area into a source region and two drain regions spaced apart from the source region, a saddle-shaped N+/N?/N+ structure in the source region of the active area; and two N+ drain doping regions in the two drain regions, respectively.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 27, 2015
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Tzung-Han Lee, Neng-Tai Shih, Yaw-Wen Hu
  • Patent number: 8841707
    Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor region, a first diffusion layer, a second diffusion layer, a third diffusion layer, an insulating film, a potential layer, and a read electrode. The semiconductor region includes first and second surfaces. The first diffusion layer is formed in the first surface. The first diffusion layer's concentration is a maximum value in a position at a first depth. The charge accumulation layer has a second depth. The second diffusion layer contacts the first diffusion layer. The third diffusion layer is formed in a position which faces the second diffusion layer in respect to the first diffusion layer. The insulating film is formed on the first surface. The potential layer is formed on the insulating film and has a predetermined potential. The read electrode is formed on the insulating film.
    Type: Grant
    Filed: September 17, 2010
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirofumi Yamashita
  • Patent number: 8772840
    Abstract: In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8748901
    Abstract: This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: June 10, 2014
    Assignee: Panasonic Corporation
    Inventors: Kunimasa Takahashi, Masahiko Niwayama, Masao Uchida, Chiaki Kudou
  • Patent number: 8698207
    Abstract: The instant disclosure describes a photodetector that includes at least one portion of a semiconducting layer formed directly on at least a portion of a reflective layer and to be illuminated with a light beam, at least one pad being formed on the portion of the semiconducting layer opposite the reflective layer portion, wherein the pad and the reflective layer portion are made of a metal or of a negative permittivity material, the optical cavity formed between said at least one reflective layer portion and said at least one pad has a thickness strictly lower than a quarter of the ratio of the light beam wavelength to the optical index of the semiconducting layer, and typically representing about one tenth of said ratio.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: April 15, 2014
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: Jérôme Le Perchec, Yohan Desieres
  • Patent number: 8536625
    Abstract: An electronic image sensor includes a semiconductor substrate having a first surface configured for accepting illumination to a pixel array disposed in the substrate. An electrically-doped channel region for each pixel is disposed at a second substrate surface opposite the first substrate surface. The channel regions are for collecting photogenerated charge in the substrate. An electrically-doped channel stop region is at the second substrate surface between each channel region. An electrically-doped shutter buried layer, disposed in the substrate at a depth from the second substrate surface that is greater than that of the pixel channel regions, extends across the pixel array. An electrically-doped photogenerated-charge-extinguishment layer, at the first substrate surface, extends across the pixel array.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 17, 2013
    Assignee: Massachusetts Institute of Technology
    Inventor: Barry E. Burke
  • Patent number: 8426280
    Abstract: There is provided a charge trap type non-volatile memory device and a method for fabricating the same, the charge trap type non-volatile memory device including: a tunnel insulation layer formed over a substrate; a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer; a charge barrier layer formed over the charge trap layer; a gate electrode formed over the charge barrier layer; and an oxide-based spacer formed over sidewalls of the charge trap layer and provided to isolate the charge trap layer.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: April 23, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cha-Deok Dong
  • Patent number: 8334551
    Abstract: Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: December 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaro Itagaki, Yoshihisa Iwata, Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Hideaki Aochi, Akihiro Nitayama
  • Patent number: 8207583
    Abstract: In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: June 26, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 8193564
    Abstract: A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: June 5, 2012
    Assignee: DENSO CORPORATION
    Inventors: Naohiro Suzuki, Eiichi Okuno, Hideo Matsuki
  • Publication number: 20120038904
    Abstract: A unit pixel included in a photo-detection device, the unit pixel including a floating diffusion region in a semiconductor substrate, a ring-shaped collection gate over the semiconductor substrate, a ring-shaped drain gate over the semiconductor substrate, and a drain region in the semiconductor substrate, wherein the collection gate and the drain gate are respectively arranged between the floating diffusion region and the drain region.
    Type: Application
    Filed: July 21, 2011
    Publication date: February 16, 2012
    Inventors: Eric R. FOSSUM, Yoon-Dong Park
  • Patent number: 8105924
    Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Patent number: 8101474
    Abstract: A novel buried-channel graphene device structure and method for manufacture. The new structure includes a two level channel layer comprised of a buried-channel graphene layer with an amorphous silicon top channel layer. The method for making such structure includes the steps of depositing a graphene layer on a substrate, depositing an amorphous silicon layer on the graphene layer, converting the upper layer of the amorphous silicon layer to a gate dielectric by nitridation, oxidation or oxynitridation, while keeping the lower layer of the amorphous silicon layer to serve as part of the channel to form the buried-channel graphene device.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventor: Wenjuan Zhu
  • Patent number: 8008147
    Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
  • Patent number: 7892927
    Abstract: A transistor including a germanium-rich channel. The germanium-rich channel is produced by oxidation of the silicon contained in the silicon-germanium intermediate layer starting from the lower surface of the said intermediate layer. The germanium atoms are therefore caused to migrate towards the upper surface of the silicon-germanium intermediate layer, and are stopped by the gate insulating layer. The migration of the atoms during the oxidation step is thus less prejudicial to the performance of the transistor, since the gate insulator of the transistor has already been produced and is not modified during this step. The migration of the germanium atoms towards the gate insulator, which is immobile, leads to a limitation of the surface defects between the channel and the insulator.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: February 22, 2011
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Stephane Monfray, Thomas Skotnicki, Didier Dutartre, Alexandre Talbot
  • Patent number: 7842558
    Abstract: According to another embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: November 30, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 7759706
    Abstract: The present invention provides a solid-state imaging device having an array of unit pixels, each unit pixel including a photoelectric conversion element and an amplifier transistor for amplifying a signal corresponding to charge obtained by photoelectric conversion through the photoelectric conversion element and outputting the resultant signal. The amplifier transistor includes a buried channel MOS transistor. According to the present invention, 1/f noise can be basically reduced.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: July 20, 2010
    Assignee: Sony Corporation
    Inventors: Kazuichiro Itonaga, Suzunori Endo, Ikuo Yoshihara
  • Patent number: 7691734
    Abstract: A far subcollector, or a buried doped semiconductor layer located at a depth that exceeds the range of conventional ion implantation, is formed by ion implantation of dopants into a region of an initial semiconductor substrate followed by an epitaxial growth of semiconductor material. A reachthrough region to the far subcollector is formed by outdiffusing a dopant from a doped material layer deposited in the at least one deep trench that adjoins the far subcollector. The reachthrough region may be formed surrounding the at least one deep trench or only on one side of the at least one deep trench. If the inside of the at least one trench is electrically connected to the reachthrough region, a metal contact may be formed on the doped fill material within the at least one trench. If not, a metal contact is formed on a secondary reachthrough region that contacts the reachthrough region.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 6, 2010
    Assignee: International Business Machines Corporation
    Inventors: Bradley A. Orner, Robert M. Rassel, David C. Sheridan, Steven H. Voldman
  • Patent number: 7659569
    Abstract: A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: February 9, 2010
    Assignee: Spansion LLC
    Inventors: Wei Zheng, Kuo-Tung Chang, Sung-Yong Chung, Ashot Melik-Martirosian
  • Patent number: 7646062
    Abstract: A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 12, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshikazu Yamaoka, Satoru Shimada
  • Patent number: 7535038
    Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: May 19, 2009
    Assignee: Sony Corporation
    Inventors: Kazushi Wada, Kouichi Harada, Shuji Otsuka, Mitsuru Sato
  • Patent number: 7414279
    Abstract: Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: August 19, 2008
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Joon-Soo Park
  • Patent number: 7351661
    Abstract: A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Hwa Heo, Soo-Jin Hong
  • Publication number: 20080048212
    Abstract: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage, a third electrode for transferring the signal charges to the voltage conversion portion, provided between the first electrode and the voltage conversion portion, wherein the second electrode is provided on a side opposite to the third electrode and the voltage conversion portion with respect to the first electrode.
    Type: Application
    Filed: July 31, 2007
    Publication date: February 28, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Hayato Nakashima, Ryu Shimizu
  • Patent number: 7173294
    Abstract: The CCD image sensor addresses the problem of noise, due to background charge generated by Compton scattering of gamma rays. In applications, in which an imager must operate in a high-radiation environment, such background noise reduces the video signal/noise. This imager reduces the amount of charge collected from Compton events, while giving up very little sensitivity to photons in the visible/near IR.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 6, 2007
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Barry E. Burke, Robert K. Reich
  • Patent number: 7148543
    Abstract: A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: December 12, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamada, Hajime Nagano, Ichiro Mizushima, Tsutomu Sato, Hisato Oyamatsu, Shinichi Nitta
  • Patent number: 7138671
    Abstract: A first p+-type region on a surface of a photodiode unit is formed over a region from a surface of the photodiode unit through a surface of a signal charge read-out unit until reaching the charge transfer unit. Also, the following structure is adapted: the structure in which a boundary between the first p+-type region and a p++-type region is not on a same plane with a boundary of an n-type impurity region which forms the photodiode unit on a side of the signal charge read-out unit. Further, a second p+-type region is formed between the first p+-type region and the p++-type region on the surface of the photodiode unit. The second p+-type region has an impurity concentration between the impurity concentrations of the first p+-type region and the p++-type region.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Jun Hirai, Tooru Yamada
  • Patent number: 7098512
    Abstract: Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface strip structure, and an axial sub-surface strip structure. A particular layout pattern is selected for an area of the semiconductor device according to several factors.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: August 29, 2006
    Assignee: Transmeta Corporation
    Inventors: Mike Pelham, James B. Burr
  • Patent number: 7091530
    Abstract: A charge-coupled device imager including an array of super pixels disposed in a semiconductor substrate having a surface that is accessible to incident illumination. For each super pixel there is provided a plurality of subpixels which each correspond to one in the sequence of image frames. Each subpixel includes a doped photogenerated charge collection channel region opposite the illumination-accessible substrate surface, a charge collection channel region control electrode, doped charge drain regions adjacent to the channel region, a charge drain region control electrode, and a doped charge collection control region. To each subpixel are provided channel region and drain region control voltage connections, for independent collection and storage of photogenerated charge from the substrate at the charge collection channel region of a selected subpixel during one in the sequence of image frames and for drainage of photogenerated charge from the substrate to a drain region.
    Type: Grant
    Filed: July 2, 2003
    Date of Patent: August 15, 2006
    Assignee: Massachusetts Institute of Technology
    Inventors: Robert K. Reich, Bernard B. Kosicki, Jonathan C. Twichell, Barry E. Burke, Dennis D. Rathman