Abstract: An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2.

Abstract: An auto-zeroed charge transfer circuit uses an output MOS transistor having a gate, a source and a drain; the gate of the MOS transistor being maintained to a predetermined control voltage and the drain of the MOS transistor being connected by default to a current sink; and a control circuit arranged to, in response to an input signal, bring the MOS transistor to a non-conductive state where any drop in voltage of the MOS transistor source causes the MOS transistor to conduct and, after connecting the drain of the MOS transistor away from the current sink and to an output node, pull down the source of the MOS transistor until a predetermined charge is sent to the output node through the MOS transistor.

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract: A method of manufacturing a laser diode device includes: forming, in a semiconductor laser bar, separation trenches extending across all of a transverse dimension of the semiconductor laser bar and defining a mesa stripe, each of the separation trenches having wide portions located at longitudinal edge portions of the semiconductor laser bar and a narrow portion located in a longitudinal central portion of the semiconductor laser bar; scribing, in the semiconductor laser bar, grooves extending parallel to the separation trenches and terminating before reaching longitudinal edge portions of the semiconductor laser bar; and splitting the semiconductor laser bar along the grooves to form cleaved surfaces extending from a bottom surface of the semiconductor laser bar to bottom surfaces of the separation trenches.

Abstract: Disclosed are semiconductor die packages, systems, and methods therefor. An exemplary package comprises a patterned conductive layer having a first surface, a second surface, and a first thickness between its first and second surfaces; a semiconductor die disposed over the first surface of the patterned conductive layer and electrically coupled thereto; a plurality of conductive bodies disposed at the second surface of the patterned conductive layer and electrically coupled thereto, each conductive body having a thickness that is greater than the first thickness; and a body of electrically insulating material disposed on the semiconductor die and a portion of the first surface of the patterned conductive layer. A further embodiment farther comprises a second semiconductor die disposed over the second surface of the patterned conductive layer and electrically coupled thereto.

Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.

Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.

Abstract: Provided is a plasma display panel (PDP), which minimizes an elevation in reflection brightness caused by reflection of external light and improves in contrast and discharge efficiency. The PDP includes a front substrate transmitting visible rays; a rear substrate disposed substantially parallel to the front substrate; barrier ribs interposed between the front and rear substrates and defining a plurality of discharge cells along with the front and rear substrates, the barrier ribs formed of a dielectric material; two or more kinds of discharge electrodes disposed on at least one of the front substrate, the rear substrate, and the barrier ribs; a dielectric layer disposed on a rear surface of the front substrate; phosphor layers disposed in the discharge cells; and a discharge gas filled in the discharge cells.

Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode, an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area, and a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.

Abstract: In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-plane side than the charge accumulating units. The depletion prevention layer prevents a depletion region around the charge accumulating units from reaching the second plane of the semiconductor base. The depletion prevention layer can suppress surface dark current going into the charge accumulating units. Meanwhile, an energy ray incident from the second-plane side pass through the depletion prevention layer to generate signal charges in the charge accumulating units (depletion regions). The charge accumulating units collect, on a pixel-by-pixel basis, the signal charges which are to be transported to the charge transfer unit under voltage control or the like, and then are read to exterior as image signals.

Abstract: A memory device includes a semiconducting polymer film, which includes an organic dopant. The semiconducting polymer film has a first side and a second side. The memory device also includes a first plurality of electrical conductors substantially parallel to each other coupled to the first side of the semiconducting polymer layer, and a second plurality of electrical conductors substantially parallel to each other, coupled to the second side of the semiconducting polymer layer. The first and second pluralities of electrical conductors are substantially mutually orthogonal to each other. Further, an electrical charge is localized on the organic dopant.

Abstract: The present invention relates to a CMOS active pixel sensor which includes a compensation circuit capable of compensating a lowered pixel voltage output due to leakage current of a photodiode. The CMOS active pixel sensor having a light sensing unit for generating an output voltage when light is incident thereupon, the sensing unit having an amount of leakage current before the incidence of light. A reset unit resets the output voltage of the light sensing unit to an initial reset voltage in response to a reset signal. A sense transistor has a source, a drain coupled to a power source voltage, and a gate coupled to the output of the light sensing unit. A select transistor has a drain connected to a source of the sense transistor, and provides the voltage of the sense transistor to a bit line, in response to a select signal. A compensation unit supplies a voltage corresponding to the output voltage of the light sensing unit lowered by the leakage current.

Abstract: A method for forming solder bumps on an electronic structure including the steps of first providing a mold made by a sheet of a mold material having a thickness greater than that of the solder bumps to be formed, the mold material has sufficient optical transparency so as to allow the inspection of a solder material subsequently filled into the mold cavities that are formed in the mold material, and a coefficient of thermal expansion that is substantially similar to the substrate which the mold will be mated to, forming a multiplicity of mold cavities in the sheet of mold material, filling the multiplicity of mold cavities with a solder material, cooling the mold to a temperature that is sufficient to solidify the solder material in the multiplicity of mold cavities, positioning the mold intimately with the electronic structure such that the cavities facing the structure, and heating the mold and the structure together to a temperature sufficiently high such that the solder material transfers onto the electro

Abstract: A charge generation device configured within a semiconductor region of a substrate. The device includes a source for providing an input charge and an input diffusion which receives said input charge. A barrier gate associated with the input diffusion determines a selected potential of the input diffusion. A preset diffusion presets the input diffusion to the selected potential. An output element receives the input charge from the input diffusion. A first coupling means is provided for coupling the preset diffusion to the input diffusion subsequent to the output diffusion receiving the input charge during a first clock cycle, and for decoupling the preset diffusion from the input diffusion prior to the input diffusion receiving the input charge during a second clock cycle.

Abstract: Disclosed is a charge transfer device which has charge transfer registers, a floating diffusion layer for receiving a signal charge transferred from the charge transfer registers, a reset circuit for extracting a signal charge transferred from the floating diffusion layer and resetting a potential of the floating diffusion layer periodically to a predetermined potential, and an output circuit of a source follower formed by a MOSFET having a gate connected to the floating diffusion layer and a load resistance connected to a source of the MOSFET. The load resistance includes a substrate of a first conductivity type, a diffusion layer of a second conductivity type which is provided on the substrate, and a carrier accumulation layer of the first conductivity type which is provided at the top surface of the diffusion layer.

Abstract: A general absolute value circuit for developing a true, symmetric or bipolar, absolute value output signal from an input charge signal, compact enough to be used on a sensor chip incorporated into (or used in combination with) a pixel processor of the type used in imaging and other systems that collect electromagnetic radiation as part of on-chip circuitry, includes a balanced differential amplifier combined with a merged dual shelf transistor structure. The balanced differential amplifier, in response to an input charge signal, drives the merged dual shelf transistor structure which in turn generates the desired true absolute value output signal. Such circuitry may be used in imaging systems to implement focal-plane processing algorithms or may be used for performing a single read true absolute value computation by a pixel processor located on a sensor chip. The merged dual shelf transistor structure enhances performance and speed of the processor in which it is incorporated.

Abstract: A horizontal charge coupled device (HCCD) is provided with a multiple reset gate in order to establish a more stable, less noisy voltage in an output node floating diffusion. Charges are transferred from an input of the HCCD to the floating diffusion by multiple, overlapping gate structures. Signal charges are detected or read out from the floating diffusion through an amplifier/inverter circuit. Periodically, the voltage of the floating diffusion is established to a reference level by application of a reset signal to a multiple reset gate structure, which results in charges in the floating diffusion being transferred to a reset drain. Noise induced by the reset operation is lessened on average due to the multiple reset gate structure.

Abstract: A solid state imaging apparatus which prevents occurrence of small aperture fading by diffraction of light and can control the amplitude level of an image signal within a prescribed range. The solid state imaging apparatus employs a solid state imaging element such as a CCD. When the level of an image signal outputted from the solid state imaging element exceeds a predetermined value, a driving motor is driven to effect adjustment of an iris. The capacitance of a variable capacitance diode provided in a voltage converting section of the solid state imaging element is controlled in accordance with the amplitude level of the image signal to control the voltage conversion efficiency of the voltage converting section of the solid state imaging element so as to fix the level of the image signal.

Abstract: The semiconductor image sensor element comprises a transistor gate potential well 102, a virtual potential well 100 adjacent the transistor gate potential well 102, a clear gate barrier 104 adjacent the virtual potential well 100, a clear drain 30 adjacent the clear gate barrier 104, and a charge sensor 28 for sensing charge levels in the transistor gate potential well 102. The charge levels are responsive to light incident on the device. Charge is stored in the virtual potential well 100 during charge integration. After charge integration, the charge is transferred into the transistor gate potential well 102 from the virtual potential well 100 for charge detection by the charge sensor 28. After charge detection, the charge is transferred from the transistor potential well 102 to the clear drain 30.

Abstract: A charge coupled device according to the present invention, having an output terminal, for detecting an electric charge and for outputting a detection signal corresponding to the electric charge from the output terminal, comprises a semiconductor substrate having a main surface, further having a first, second and third regions in the main surface, both the first and second regions defining the third region therebetween, a charge supply formed in the vicinity of the first region, for supplying the electric charge to the first region, a first impurity formed in the first region, for transferring the electric charge to the third region, a floating gate electrode overlying the third region, coupled to the output terminal, for detecting the electric charge and outputting the detection signal corresponding to the electric charge from the output terminal in a first condition, for transferring the electric charge to the second region in a second condition, a transfer electrode overlying the second region, applied a c