Signal Applied To Field Effect Electrode Patents (Class 257/236)
  • Patent number: 10879839
    Abstract: Power converter circuitry includes a direct current (DC) input comprising a first DC input node and a second DC input node, an alternating current (AC) output comprising a first AC output node coupled to the first DC input node and a second AC output node, a first boost switch coupled between the second DC input node and a boost intermediate node, a second boost switch coupled between the boost intermediate node and a common node, a boost inductor coupled between the boost intermediate node and the first DC input node, a link capacitor coupled between the second DC input node and the common node, a first half-bridge switch coupled between the second DC input node and a half-bridge intermediate node, a second half-bridge switch coupled between the half-bridge intermediate node and the common node, and a half-bridge inductor coupled between the half-bridge intermediate node and the second AC output node.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: December 29, 2020
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Rajapandian Ayyanar, Yinglai Xia, Jinia Roy
  • Patent number: 9923014
    Abstract: An image sensor includes a first charge storage region of a first conductive type disposed in a substrate, a second charge storage region of a second conductive type disposed on one side of the first charge storage region, a first floating diffusion region spaced apart from the first charge storage region, a second floating diffusion region spaced apart from the second charge storage region, a first transfer gate disposed on the substrate between the first charge storage region and the first floating diffusion region, and a second transfer gate disposed on the substrate between the second charge storage region and the second floating diffusion region.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: March 20, 2018
    Assignee: DB HITEK CO., LTD.
    Inventor: In Guen Yeo
  • Patent number: 9722944
    Abstract: A rate adaptation system includes a barrel shift slot register and a rate adaptation register. The barrel shift slot register includes a plurality of slots with one of a valid read request or a dummy read request. A rate adaptation register is configured to sequentially cycle through the slots of the barrel shift register in response to a clock providing valid read requests to a FIFO buffer and to skip provision of valid read requests for clock cycles of the first clock associated with slots that include dummy read requests. The rate adaption register may also receive data blocks from the FIFO buffer and provide those data blocks to another FIFO buffer.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: August 1, 2017
    Assignee: VINTOMIE NETWORKS B.V., LLC
    Inventors: Praveen Gopalapuram, Mani Kumaran, Tamleigh Ross
  • Patent number: 9681077
    Abstract: A device for transferring charges photogenerated in a portion of a semiconductor layer delimited by at least two parallel trenches, each trench including, lengthwise, at least a first and a second conductive regions insulated from each other and from the semiconductor layer, including the repeating of a first step of biasing of the first conductive regions to a first voltage to form a volume accumulation of holes in the area of this portion located between the first regions, while the second conductive regions are biased to a second voltage greater than the first voltage, and of a second step of biasing of the first regions to the second voltage and of the second regions to the first voltage.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: June 13, 2017
    Assignees: STMicroelectronics SA, STMicroelectronics (Grenoble 2) SAS
    Inventors: Cedric Tubert, Francois Roy, Pascal Mellot
  • Patent number: 9385118
    Abstract: A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first capacitor electrode, a second capacitor electrode over the first capacitor electrode, a third capacitor electrode adjacent to first sidewalls of the first and second capacitor electrodes, a fourth capacitor electrode adjacent to second sidewalls of the first and second capacitor electrodes, and a fifth capacitor electrode adjacent to the fourth capacitor electrode.
    Type: Grant
    Filed: April 22, 2015
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yvonne Lin, Wen-Ting Chu
  • Patent number: 9313430
    Abstract: Since the great number of elements constituting a unit pixel having an amplification function would hinder reduction of pixel size, unit pixel n,m arranged in a matrix form is comprised of a photodiode, a transfer switch for transferring charges stored in the photodiode, a floating diffusion for storing charges transferred by the transfer switch, a reset switch for resetting the floating diffusion, and an amplifying transistor for outputting a signal in accordance with the potential of the floating diffusion to a vertical signal line, and by affording vertical selection pulse ?Vn to the drain of the reset switch to control a reset potential thereof, pixels are selected in units of rows.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: April 12, 2016
    Assignee: SONY CORPORATION
    Inventors: Takahisa Ueno, Kazuya Yonemoto, Ryoji Suzuki, Koichi Shiono
  • Patent number: 8962442
    Abstract: A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Patent number: 8896033
    Abstract: The object of the invention is to provide a three-terminal switch (electrochemical transistor) capable of achieving sharp on-off operation. A source electrode and a drain electrode are juxtaposed with an insulator interposed between them, and on the assembly there is an ion diffusion member such as Ta2O5 located. On the opposite surface of the ion diffusion member, there is a gate electrode located that is capable of supplying metal ions such as copper ions. By application of voltage to the gate electrode, the metal ions going out of the gate electrode are reversibly precipitated as metal on both source and drain electrodes as well as on the insulator near them, thereby controlling conduction and non-conduction between the source electrode and the drain electrode.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 25, 2014
    Assignee: National Institute for Materials Science
    Inventors: Tsuyoshi Hasegawa, Masakazu Aono, Kazuya Terabe, Tohru Tsuruoka, Yaomi Itoh
  • Patent number: 8847287
    Abstract: A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge.
    Type: Grant
    Filed: August 31, 2013
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Zhengwen Li, Fei Liu, Zhen Zhang
  • Patent number: 8735794
    Abstract: A CCD image sensor includes vertical CCD shift registers and gate electrodes disposed over the vertical CCD shift registers. The gate electrodes are divided into distinct groups of gate electrodes. The CCD image sensor is adapted to operate in an accumulation mode and a charge transfer mode, an accumulation mode and a charge shifting mode, or an accumulation mode, a charge transfer mode, and a charge shifting mode. The charge transfer mode has an initial charge transfer phase and a final charge transfer phase. The charge shifting mode has an initial charge shifting phase and a final charge shifting phase.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 27, 2014
    Assignee: Truesense Imaging, Inc.
    Inventor: Christopher Parks
  • Patent number: 8624332
    Abstract: A vertical conduction electronic power device includes respective gate, source and drain areas in an epitaxial layer arranged on a semiconductor substrate. The respective gate, source and drain metallizations may be formed by a first metallization level. Corresponding gate, source and drain terminals or pads may be formed by a second metallization level. The power device is configured as a set of modular areas extending parallel to each other, each having a rectangular elongate source area perimetrically surrounded by a narrow gate area. The modular areas are separated from each other by regions with the drain area extending parallel and connected at the opposite ends thereof to a second closed region with the drain area forming a device outer peripheral edge.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magrì
  • Patent number: 8541804
    Abstract: An object of the present invention is to realize a numerical aperture higher than that of a pixel having a conventional construction by using a pixel circuit having a novel construction in an electro-optical device. Therefore, it is utilized that the electric potential of a gate signal line in a row except for an i-th row is set to a constant electric potential in a period except for when a gate signal line (106) in the i-th row is selected. A gate signal line 111 in an (i?1)-th row is also used as an electric current supply line for an EL element (103) controlled by the gate signal line (106) in the i-th row. Thus, wiring number is reduced and high numerical aperture is realized.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 24, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8362528
    Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: January 29, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Min-Hwa Chi
  • Patent number: 8222101
    Abstract: A MOS transistor suppressing a short channel effect includes a substrate, a first diffusion region and a second diffusion region separated from each other by a channel region in an upper portion of the substrate, a gate insulating layer including a first gate insulating layer disposed on a surface of the substrate in the channel region and a second gate insulating layer having a specified depth from the surface of the substrate to be disposed between the first diffusion region and the channel region, and a gate electrode disposed on the first gate insulating layer.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: July 17, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Kyoung-Bong Rouh
  • Patent number: 8168495
    Abstract: A technique of the invention reduces significantly the distance between the gate and single-walled carbon nanotubes to improve performance and efficiency of a carbon nanotube transistor device. Without using a porous template structure, single-walled carbon nanotubes are grown perpendicularly to a substrate between a base metal layer and a middle mesh layer. The nanotubes are insulated with a thin insulator and then gate regions are formed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 1, 2012
    Assignee: Etamota Corporation
    Inventors: Brian Y. Lim, Jon W. Lai
  • Patent number: 8039870
    Abstract: A multifinger carbon nanotube field-effect transistor (CNT FET) is provided in which a plurality of nanotube top gated FETs are combined in a finger geometry along the length of a single carbon nanotube, an aligned array of nanotubes, or a random array of nanotubes. Each of the individual FETs are arranged such that there is no geometrical overlap between the gate and drain finger electrodes over the single carbon nanotube so as to minimize the Miller capacitance (Cgd) between the gate and drain finger electrodes. A low-K dielectric may be used to separate the source and gate electrodes in the multifinger CNT FET so as to further minimize the Miller capacitance between the source and gate electrodes.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: October 18, 2011
    Assignee: RF Nano Corporation
    Inventors: Peter J. Burke, Steffen McKernan, Dawei Wang, Zhen Yu
  • Patent number: 7998828
    Abstract: A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 16, 2011
    Assignees: International Business Machines Corporation, Infineon Technologies North America
    Inventors: Fen Chen, Armin Fischer
  • Publication number: 20110186913
    Abstract: In a solid state imaging device with an electron multiplying function, in a section normal to an electron transfer direction of a multiplication register EM, an insulating layer 2 is thicker at both side portions than in a central region. A pair of overflow drains 1N is formed at a boundary between a central region and both side portions of an N-type semiconductor region 1C. Each overflow drain 1N extends along the electron transfer direction of the multiplication register EM. Overflow gate electrodes G extend from the thin portion to the thick portion of the insulating layer 2. The overflow gate electrodes G are disposed between both ends of each transfer electrode 8 in a longitudinal direction and the insulating layer 2, and they also function as shield electrodes for each electrode 8 (8A and 8B).
    Type: Application
    Filed: January 27, 2010
    Publication date: August 4, 2011
    Applicant: Hamamatsu Photonics K.K.
    Inventors: Hisanori Suzuki, Yasuhito Yoneta, Shin-ichiro Takagi, Kentaro Maeta, Masaharu Muramatsu
  • Patent number: 7952633
    Abstract: A method and apparatus for propagating charge through a sensor and implementation thereof is provided. The method and apparatus may be used to inspect specimens, the sensor operating to advance an accumulated charge between gates of the TDI sensor. The design implementation provides a set of values representing a plurality of out of phase signals, such as sinusoidal or trapezoidal signals. These out of phase signals are converted and transmitted to the sensor. The converted signals cause the sensor to transfer charges in the sensor toward an end of the sensor. Aspects such as feed through correction and correction of nonlinearities are addressed.
    Type: Grant
    Filed: December 1, 2005
    Date of Patent: May 31, 2011
    Assignee: KLA-Tencor Technologies Corporation
    Inventors: David Lee Brown, Kai Cao, Yung-Ho Chuang
  • Patent number: 7952121
    Abstract: An image sensor includes a charge storage portion for storing and transferring signal charges, a first electrode for forming an electric field storing the signal charges in the charge storage portion, a charge increasing portion for increasing the signal charges stored in the charge storage portion and a second electrode for forming another electric field increasing the signal charges in the charge increasing portion, wherein the quantity of the signal charges storable in the charge storage portion is not less than the quantity of the signal charges storable in the charge increasing portion.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: May 31, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Ryu Shimizu
  • Patent number: 7884398
    Abstract: Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: February 8, 2011
    Assignee: Polytechnic Institute of New York University
    Inventors: Kalle Levon, Arifur Rahman, Tsunehiro Sai, Ben Zhao
  • Patent number: 7732857
    Abstract: A TFT substrate with reduced pixel defect rate is presented. The TFT substrate includes a pixel electrode, a negative line to apply a reverse voltage to the pixel electrode, and a recovery transistor including a drain electrode overlapping a part of the negative line with a insulating layer disposed between the negative line and the drain electrode. A contact hole is formed on the negative line and the drain electrode, and a bridge electrode connects the negative line and the drain electrode through the contact hole. The thin film transistor substrate and a display apparatus presented herein protect a data line assembly metal layer and decrease pixel defect. An improved reverse voltage efficiency is applied to a pixel electrode to protect a drain electrode.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 8, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Song-mi Hong, Jung-soo Rhee, Beohm-rock Choi, Jin-koo Chung, Jianpu Wang, Dong-won Lee
  • Patent number: 7592652
    Abstract: An object of the present invention is to realize a numerical aperture higher than that of a pixel having a conventional construction by using a pixel circuit having a novel construction in an electro-optical device. Therefore, it is utilized that the electric potential of a gate signal line in a row except for an i-th row is set to a constant electric potential in a period except for when a gate signal line (106) in the i-th row is selected. A gate signal line 111 in an (i?1)-th row is also used as an electric current supply line for an EL element (103) controlled by the gate signal line (106) in the i-th row. Thus, wiring number is reduced and high numerical aperture is realized.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: September 22, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 7485840
    Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.
    Type: Grant
    Filed: February 8, 2007
    Date of Patent: February 3, 2009
    Assignee: DALSA Corporation
    Inventor: Leonid Yurievich Lazovsky
  • Patent number: 7468532
    Abstract: An imaging device having a pixel array in which one plate of a storage capacitor is coupled to a storage node while another plate is formed by an electrode of a photo-conversion region.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: December 23, 2008
    Assignee: Aptina Imaging Corporation
    Inventor: Jeffrey A. McKee
  • Patent number: 7462890
    Abstract: An integrated circuit layout of a carbon nanotube transistor device includes a first and second conductive material. The first conductive material is connected to ends of single-walled carbon nanotubes below (or above) the first conductive material. The second conductive material is not electrically connected to the nanotubes below (or above) the second conductive material. The first conductive material may be metal, and the second conductive material may be polysilicon or metal. The nanotubes are perpendicular to the first conductive material. In one implementation, the first and second conductive materials form interdigitated fingers. In another implementation, the first conductive material forms a serpentine track.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: December 9, 2008
    Assignee: Atomate Corporation
    Inventors: Thomas W. Tombler, Jr., Brian Y. Lim
  • Patent number: 7329912
    Abstract: A photodiode device including a well located in a substrate, a floating node located in the well and shallow trench isolation (STI) regions located over and laterally opposing the floating node. A borderless contact buffer layer is located over at least the floating node, and an interlevel dielectric layer is located over the borderless contact buffer layer. A borderless contact extends through the interlevel dielectric layer and the borderless contact buffer layer to the floating node.
    Type: Grant
    Filed: August 12, 2005
    Date of Patent: February 12, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Dun-Nian Yaung
  • Patent number: 7199409
    Abstract: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: April 3, 2007
    Assignee: Massachusetts Institute of Technology
    Inventor: Michael P. Anthony
  • Patent number: 7026690
    Abstract: The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) constructions. The base region of the bipolar device can be physically and electrically connected to one of the source/drain regions of the FET to act as a storage node for the memory cell. The semiconductor material of the SOI constructions can comprise Si/Ge, and the active region of the FET can extend into the Si/Ge. The SOI constructions can be formed over any of a number of substrates, including, for example, semiconductive materials, glass, aluminum oxide, silicon dioxide, metals and/or plastics.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7022287
    Abstract: The present invention discloses an electrochemical device for detecting single particles, and methods for using such a device to achieve high sensitivity for detecting particles such as bacteria, viruses, aggregates, immuno-complexes, molecules, or ionic species. The device provides for affinity-based electrochemical detection of particles with single-particle sensitivity. The disclosed device and methods are based on microelectrodes with surface-attached, affinity ligands (e.g., antibodies, combinatorial peptides, glycolipids) that bind selectively to some target particle species. The electrodes electrolyze chemical species present in the particle-containing solution, and particle interaction with a sensor element modulates its electrolytic activity. The devices may be used individually, employed as sensors, used in arrays for a single specific type of particle or for a range of particle types, or configured into arrays of sensors having both these attributes.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: April 4, 2006
    Assignee: Sandia National Laboratories
    Inventors: Joseph Schoeniger, Albert W. Flounders, Robert C. Hughes, Antonio J. Ricco, Karl Wally, Stanley H. Kravitz, Richard P. Janek
  • Patent number: 6958499
    Abstract: Provided is a field emission device having a mesh gate. The object of this research is to provide a field emission display (FED) using a triode field emission device for preventing increase of operation voltage, and securing high concentration of electron beams. The operation properties of the FED is different based on a structure of an extraction electrode. In this research, the extraction electrode is formed on the electron emitting source and it has a plurality of openings corresponding to the locations of carbon nanotube mixture. The concentration of the electron beams is raised and leakage current is suppressed by using an insulating mesh gate plate. The upper part of the openings has a smaller diagram than the lower part. The high concentration of electron beams and little leakage current can be generated by adding auxiliary electrodes or optimizing the shape of electrodes.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: October 25, 2005
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chi-Sun Hwang, Yoon-Ho Song, Bong-Chul Kim, Choong-Heui Chung
  • Patent number: 6862333
    Abstract: This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such as M sections (U1-UM), each of which is a CMD unit U that can perform a charge multiplication operation, set in series. Each section of CMD unit Ui has plural (such as 4) electrodes G1, G2, G3, G4 set in a row via an insulating film, such as silicon oxide film 100, on a silicon insulating film. Among driving voltages P1, P2, P3, P4 applied on the electrodes G1, G2, G3 and G4, P1 and P2 are applied in the same cycle as the transfer clock, P4 for impact ionization is applied in intermittent cycles with respect to P1 and P2, and P3 is applied as a DC voltage at a prescribed level.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Shunji Kashima, Kyoichi Yahata, Izumi Kobayashi
  • Patent number: 6815791
    Abstract: A semiconductor detector of electromagnetic radiation which utilizes a dual-purpose electrode which extends significantly beyond the edge of a photodiode. This configuration reduces the sensitivity of device performance on small misalignments between manufacturing steps while reducing dark currents, kTC noise, and “ghost” images. The collection-mode potential of the dual-purpose electrode can be adjusted to achieve charge confinement and enhanced collection efficiency, reducing or eliminating the need for an additional pinning layer. Finally, the present invention enhances the fill factor of the photodiode by shielding the photon-created charge carriers formed in the substrate from the potential wells of the surrounding circuitry.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: November 9, 2004
    Assignee: FillFactory
    Inventor: Bart Dierickx
  • Patent number: 6780666
    Abstract: A pixel cell having two capacitors connected in series where each capacitor has a capacitance approximating that at of the periphery capacitors and such that the effective capacitance of the series capacitors is smaller than that of each of the periphery capacitors. The series-connected capacitors are coupled to the floating diffusion (FD) region for receiving “surplus” charge from the FD region during saturation conditions.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Brent A. McClure
  • Patent number: 6777911
    Abstract: A charge transformer is disclosed for coupling charge from a first device to a charge sensitive device, such as a single electron transistor. The charge transformer includes a plurality of capacitors that are alternatively connected in parallel and series such that a power signal from the first device charges the capacitors when they are connected in parallel, and the capacitors are discharged to the charge sensitive device when they are connected in series.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: August 17, 2004
    Assignee: The Regents of the University of Michigan
    Inventors: Kim Michelle Lewis, Cagliyan Kurdak
  • Patent number: 6683337
    Abstract: A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6653740
    Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: November 25, 2003
    Assignee: International Rectifier Corporation
    Inventors: Daniel M. Kinzer, Aram Arzumanyan, Tim Sammon
  • Publication number: 20030178653
    Abstract: The present invention relates to high-temperature low alternating current (AC) loss superconducting coil (110A-C), to methods of fabricating such superconducting coils (110A-C) and to devices which utilize high temperature superconductor [HTS] tape coils such as transformer, motors, generators, etc.
    Type: Application
    Filed: May 22, 2003
    Publication date: September 25, 2003
    Inventors: Chandra T. Reis, Michael S. Walker
  • Patent number: 6586784
    Abstract: A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: July 1, 2003
    Assignee: Eastman Kodak Company
    Inventor: Christopher Parks
  • Publication number: 20030111677
    Abstract: When a digital video signal inputted to a latch circuit is Hi electric potential, undesirably a current flows continuously for one horizontal period at maximum, and this causes a great increase in power consumption of a semiconductor device. Therefore an object of the present invention is to provide a display device in which power consumption can be reduced by minimizing occurrence of the current path during the circuit operation, as well as a driving method. The present invention provides a semiconductor device in which two outputs, a non-inverted output and an inverted output, are obtained when a digital video signal is inputted and therefore occurrence of the current path can be minimized in a downstream buffer driven by these signals. Furthermore, a semiconductor device with reduced power consumption is provided by using the structure described above.
    Type: Application
    Filed: November 27, 2002
    Publication date: June 19, 2003
    Inventor: Hiroyuki Miyake
  • Patent number: 6580106
    Abstract: In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: June 17, 2003
    Assignee: Isetex. Inc
    Inventor: Jaroslav Hynecek
  • Publication number: 20030098476
    Abstract: A synapse configured of an A-MOS transistor has a learning function and can implement high integration similar to that of a DRAM because of its simplified circuit configuration and compact circuit size. With the presently cutting-edge technology (0.15 &mgr;m CMOS), approximately 1G synapses can be integrated on one chip. Accordingly, it is possible to implement a neural network with approximately 30,000 neurons all coupled together on one chip. This corresponds to a network scale capable of associatively storing approximately 5,000 patterns.
    Type: Application
    Filed: November 25, 2002
    Publication date: May 29, 2003
    Applicant: Exploitation of Next Generation Co., Ltd.
    Inventor: Yutaka Arima
  • Patent number: 6512254
    Abstract: In a solid-state image pickup device, a transfer register 10 is provided with an overflow control gate OFCG and an overflow drain OFD, and the gate electrode 12A of the overflow control gate OFCG is formed so as to be superposed on the lower-layer electrodes St1, 13 of the transfer register 10 side and the overflow drain OFD side.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: January 28, 2003
    Assignee: Sony Corporation
    Inventor: Satoshi Yoshihara
  • Patent number: 6510193
    Abstract: By providing a semiconductor device including a charge transfer channel to one end of which electric charges supplied from a charge supply unit are input, and which includes a plurality of branching regions at an intermediate portion, a plurality of gate electrodes provided on the corresponding branching regions of the charge transfer channel via insulating films, an input-signal supply unit for supplying each of the gate electrodes with an input signal, a transfer electrode, provided on the charge transfer channel via a gate insulating film, for performing control so that the electric charges are transferred in a predetermined direction within the charge transfer channel, a conversion unit for coverting the transferred electric charges into a voltage, and a sense amplifier to which an output signal from the conversion unit is input, and by providing a semiconductor circuit which includes such a device, it is possible to reduce the scale of circuitry, increase the calculation speed, and reduce electric power
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: January 21, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsunobu Kochi, Mamoru Miyawaki
  • Patent number: 6489179
    Abstract: A monolithic three dimensional charged coupled device (3D-CCD) which utilizes the entire bulk of the semiconductor for charge generation, storage, and transfer. The 3D-CCD provides a vast improvement of current CCD architectures that use only the surface of the semiconductor substrate. The 3D-CCD is capable of developing a strong E-field throughout the depth of the semiconductor by using deep (buried) parallel (bulk) electrodes in the substrate material. Using backside illumination, the 3D-CCD architecture enables a single device to image photon energies from the visible, to the ultra-violet and soft x-ray, and out to higher energy x-rays of 30 keV and beyond. The buried or bulk electrodes are electrically connected to the surface electrodes, and an E-field parallel to the surface is established with the pixel in which the bulk electrodes are located. This E-field attracts charge to the bulk electrodes independent of depth and confines it within the pixel in which it is generated.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: December 3, 2002
    Assignee: The Regents of the University of California
    Inventors: Alan D. Conder, Bruce K. F. Young
  • Publication number: 20020167030
    Abstract: There is provided a solid state imaging device using a MOS image sensor of a threshold voltage modulation system employed in a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like. In configuration, in the solid state imaging device that comprises a photo diode formed in a second semiconductor layer 15a of opposite conductivity type in a first semiconductor layer 12 and 32 of one conductivity type, and a light signal detecting insulated gate field effect transistor formed in a fourth semiconductor layer 15b of opposite conductivity type in a third semiconductor layer 12 of one conductivity type adjacently to the photo diode, a carrier pocket 25 is provided in the fourth semiconductor layer 15b, and a portion of the first semiconductor layer 12, 32 under the second semiconductor layer 15a is thicker than a portion of the third semiconductor layer 12 under the fourth semiconductor layer 15b in a depth direction.
    Type: Application
    Filed: June 21, 2002
    Publication date: November 14, 2002
    Inventor: Takashi Miida
  • Patent number: 6465819
    Abstract: A solid state imaging apparatus includes a detection capacitor storing a signal charge, and an output amplifier including a plurality of transistors, and outputting the signal charge stored in the detection capacitor as a voltage signal. A gate electrode of one of the plurality of transistors as an input transistor is connected to the detection capacitor. Also, the plurality of transistors other than the input transistor has a thinner gate insulating film than the input transistor.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: October 15, 2002
    Assignee: NEC Corporation
    Inventor: Masayuki Furumiya
  • Patent number: 6365950
    Abstract: The present invention relates to a CMOS active pixel sensor which includes a compensation circuit capable of compensating a lowered pixel voltage output due to leakage current of a photodiode. The CMOS active pixel sensor having a light sensing unit for generating an output voltage when light is incident thereupon, the sensing unit having an amount of leakage current before the incidence of light. A reset unit resets the output voltage of the light sensing unit to an initial reset voltage in response to a reset signal. A sense transistor has a source, a drain coupled to a power source voltage, and a gate coupled to the output of the light sensing unit. A select transistor has a drain connected to a source of the sense transistor, and provides the voltage of the sense transistor to a bit line, in response to a select signal. A compensation unit supplies a voltage corresponding to the output voltage of the light sensing unit lowered by the leakage current.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: April 2, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Il-Young Sohn
  • Publication number: 20020033504
    Abstract: An object of the present invention is to provide a sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high ESD resistance. In the semiconductor device according to the present invention, lateral polysilicon diodes are formed and connected between high-frequency I/O signal line and the external supply voltage VDD, and between the ground GND and the high-frequency I/O signal line respectively. The forward direction of the diodes is the direction from the high-frequency I/O signal line to the VDD and the direction from the ground GND to the high-frequency I/O signal line respectively.
    Type: Application
    Filed: July 25, 2001
    Publication date: March 21, 2002
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takahiro Ohnakado