Abstract: An isolator includes a first electrode; a first insulating portion on the first electrode; a second electrode on the first insulating portion; a second insulating portion around the second electrode; and a first dielectric portion on the second electrode and the second insulating portion. The second insulating portion is provided along a first plane perpendicular to a first direction from the first electrode toward the second electrode. The second electrode including a bottom surface facing the first insulating portion, an upper surface facing the first dielectric portion, a first side surface connected to the bottom surface, and a second side surface connected to the upper surface and the first side surface. The upper surface is wider than the bottom surface in a second direction along the first plane. The first side surface is tilted with respect to the bottom surface and the second side surface.

Abstract: It is an object to suppress deterioration of characteristics of a transistor in a driver circuit. A first switch for controlling whether to set a potential state of an output signal by being turned on and off in accordance with the first input signal, and a second switch for controlling whether to set a potential state of an output signal by being turned on and off in accordance with the second input signal are included. A first wiring and a second wiring are brought into electrical continuity by turning on and off of the first switch or the second switch.

Abstract: A solid-state imaging device includes a plurality of pixels in a two-dimensional array. Each pixel includes a photoelectric conversion element that converts incident light into electric charge, and a charge holding element that receives the electric charge from the photoelectric conversion element, and transfers the electric charge to a corresponding floating diffusion. The charge holding element further includes a plurality of electrodes.

Abstract: A solid-state imaging device includes a plurality of pixels in a two-dimensional array. Each pixel includes a photoelectric conversion element that converts incident light into electric charge, and a charge holding element that receives the electric charge from the photoelectric conversion element, and transfers the electric charge to a corresponding floating diffusion. The charge holding element further includes a plurality of electrodes.

Abstract: Nano-electromechanical systems (NEMS) devices that utilize thin electrically conductive membranes, which can be, for example, graphene membranes. The membrane-based NEMS devices can be used as sensors, electrical relays, adjustable angle mirror devices, variable impedance devices, and devices performing other functions.

Abstract: A range image sensor capable of improving its aperture ratio and yielding a range image with a favorable S/N ratio is provided. A range image sensor RS has an imaging region constituted by a plurality of one-dimensionally arranged units on a semiconductor substrate 1 and yields a range image according to a charge amount issued from the units.

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: Non-volatile switches and methods for making the same include a gate material formed in a recess of a substrate; a flexible conductive element disposed above the gate material, separated from the gate material by a gap, where the flexible conductive element is supported on at least two points across the gap, and where a voltage above a gate threshold voltage causes a deformation in the flexible conductive element such that the flexible conductive element comes into contact with a drain in the substrate, thereby closing a circuit between the drain and a source terminal. The gap separating the flexible conductive element and the gate material is sized to create a negative threshold voltage at the gate material for opening the circuit.

Abstract: A high voltage trench MOS and its integration with low voltage integrated circuits is provided. Embodiments include forming, in a substrate, a first trench with a first oxide layer on side surfaces, a narrower second trench, below the first trench with a second oxide layer on side and bottom surfaces, and spacers on sides of the first and second trenches; removing a portion of the second oxide layer from the bottom surface of the second trench between the spacers; filling the first and second trenches with a first poly-silicon to form a drain region; removing the spacers, exposing side surfaces of the first poly-silicon; forming a third oxide layer on side and top surfaces of the first poly-silicon; and filling a remainder of the first and second trenches with a second poly-silicon to form a gate region on each side of the drain region.

Abstract: A method of manufacturing a laser diode device includes: forming, in a semiconductor laser bar, separation trenches extending across all of a transverse dimension of the semiconductor laser bar and defining a mesa stripe, each of the separation trenches having wide portions located at longitudinal edge portions of the semiconductor laser bar and a narrow portion located in a longitudinal central portion of the semiconductor laser bar; scribing, in the semiconductor laser bar, grooves extending parallel to the separation trenches and terminating before reaching longitudinal edge portions of the semiconductor laser bar; and splitting the semiconductor laser bar along the grooves to form cleaved surfaces extending from a bottom surface of the semiconductor laser bar to bottom surfaces of the separation trenches.

Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

Abstract: The semiconductor device (100) comprises at least one semiconductor element (20), a metallization structure comprising a first (31) and a second line (32) and extending thereon a resistor. An electrically insulating protection layer (36) is present on the resistor (35) and is defined in a pattern that is substantially identical to the resistor pattern and has a temperature stability up to a temperature that is at least equal to a deposition temperature of a passivation layer (37) to be deposited thereon so as to cover the metallization structure. Both the resistor (35) and the protection layer (36) are deposited conformally on the metallization structure and any underlying substrate.

Abstract: A vertical transistor and a method for forming the same. The vertical transistor includes a semiconductor substrate having pillar type active patterns formed on a surface thereof; first junction regions formed in the surface of the semiconductor substrate on both sides of the active patterns; screening layers formed on sidewalls of the first junction regions; second junction regions formed on upper surfaces of the active patterns; and gates formed on sidewalls of the active patterns including the second junction regions to overlap with at least portions of the first junction regions.

Abstract: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (?T), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (?S), and a reset transistor. During the accumulating period of photoelectric charge, voltage (?) over that applied on the semiconductor substrate, or ?0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.

Abstract: A pixel is formed in a semiconductor substrate (S) with a plane surface for use in a photodetector. It comprises an active region for converting incident light (In) into charge carriers, photogates (PGL, PGM, PGR) for generating a lateral electric potential (?(x)) across the active region, and an integration gate (IG) for storing charge carriers generated in the active region and a dump site (Ddiff). The pixel further comprises separation-enhancing means (SL) for additionally enhancing charge separation in the active region and charge transport from the active region to the integration gate (IG). The separation-enhancing means (SL) are for instance a shield layer designed such that for a given lateral electric potential (?(x)), the incident light (In) does not impinge on the section from which the charge carriers would not be transported to the integration gate (IG).

Abstract: A solid image capturing element comprising a plurality of vertical shift registers arranged to each correspond to a column of a plurality of light receiving pixels in a matrix arrangement, a horizontal shift register provided on an output side of the plurality of vertical shift registers, and an output section provided on an output side of the horizontal shift register. In this solid image capturing element, a reverse conductive semiconductor region is formed over one major surface of one conductive semiconductor substrate, the plurality of light receiving pixels, the plurality of vertical shift registers, the horizontal shift register, and the output section are formed in the semiconductor region, and a portion of the semiconductor region where the output section is formed has a higher dopant concentration than the portion of the semiconductor region where the horizontal shift register is formed.

Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Abstract: In a wafer (1) with a number of exposure fields (2), each of which exposure fields (2) comprises a number of lattice fields (3) with an IC (4) located therein, two groups (5, 7) of dicing paths (6, 8) are provided and two control module fields (A1, A2, B1, B2, C1, D1, D2, E1, E2, F1) are assigned to each exposure field (2), each of which control module fields extends parallel to a first direction (X) and contains at least one optical control module (OCM-A1, OCM-A2, OCM-BI, OCM-B2, OCM-C1, OCM-D1, OCM-D2, OCM-E1, OCME2, OCM-F1), wherein a first control module field (OCM-A1, OCM-B1, OCM-C1, OCMD1, OCM-E1, OCM-F1) of each exposure field (2) is located between a first edge (R1, S1, T1, U1, V1, Z1) and a row of lattice fields (3) of the exposure field (2) in question and a second control module field (OCM-A2, OCM-B2, OCM-D2, OCM-E2) is located between two rows of lattice fields (3) of the exposure field (2) in question, which are arranged adjacent to a second edge (R2, S1, U2, V2), and wherein both the first contr

Abstract: An imaging device having a pixel array in which one plate of a storage capacitor is coupled to a storage node while another plate is formed by an electrode of a photo-conversion region.

Abstract: In the solid-state imaging device of the present invention having a photoelectric conversion section and a charge transfer section equipped with a charge transfer electrode for transferring an electric charge generated in the photoelectric conversion section, the charge transfer electrode has an alternate arrangement of a first layer electrode including a first layer electrically conducting film and a second layer electrode including a second layer electrically conducting film, which are formed on a gate oxide film including a laminate film consisting of a silicon oxide film and a metal oxide thin film, and the first layer electrode and the second layer electrode are separated by insulation with an interelectrode insulating film including a sidewall insulating film formed by a CVD process to cover the lateral wall of the first layer electrode.

Abstract: An amplifying solid-state image pickup device includes photoelectric conversion transfer parts respectively composed of a photodiode and a transfer transistor, and a switched capacitor amplification part provided for every k (k: natural number) photoelectric conversion transfer parts. The switched capacitor amplification part includes an inverting amplifier composed of transistors, a reset transistor and a capacitor respectively inserted between input and output of the inverting amplifier, and a select transistor inserted between output side of the inverting amplifier and a vertical signal line. Input side of the inverting amplifier of the switched capacitor amplification part serves as a signal charge storage part common to k photoelectric conversion transfer parts. Output side of the inverting amplifier of the switched capacitor amplification part is connected to the vertical signal line via the select transistor.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.

Abstract: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.

Abstract: An adjustable charge coupled device (CCD) charge splitter includes a channel control structure and an associated plurality of output channels. Control signals applied to the channel control structure determine an amount of charge, which passes into each one of the plurality of output channels.

Abstract: In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-plane side than the charge accumulating units. The depletion prevention layer prevents a depletion region around the charge accumulating units from reaching the second plane of the semiconductor base. The depletion prevention layer can suppress surface dark current going into the charge accumulating units. Meanwhile, an energy ray incident from the second-plane side pass through the depletion prevention layer to generate signal charges in the charge accumulating units (depletion regions). The charge accumulating units collect, on a pixel-by-pixel basis, the signal charges which are to be transported to the charge transfer unit under voltage control or the like, and then are read to exterior as image signals.

Abstract: There is provided an amplifying solid-state image pickup device capable of improving S/N and maintaining a charge-voltage conversion efficiency high. In the amplifying solid-state image pickup device, signal charges of a plurality of photodiodes 1 are added up on an input side of a switched capacitor amplification part 20 via the transfer transistors 2.

Abstract: A signal sharing circuit includes a first pad adapted to receive a signal and a first sharing device associated with a first microelectronic die. The first sharing device is adapted to selectively share the signal with at least a second microelectronic die on one side of the first microelectronic die in response to a first share control signal.

Abstract: An image pick-up unit includes an image pick-up device; and a plurality of optical filters which are cemented together in layers and positioned in front of the image pick-up device. At least two optical filters among the plurality of optical filters, which have different optical properties, are different in shape from each other.

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized.

Abstract: The present invention relates to a photodiode of an image sensor. Particularly, the photodiode is formed on a substrate so that an occupying area of a unit pixel of the image sensor is reduced.

Abstract: A method of fabricating a non-volatile ferroelectric memory transistor includes forming a bottom electrode; depositing a ferroelectric layer over an active region beyond the margins of the bottom electrode; depositing a top electrode on the ferroelectric layer; and metallizing the structure to form a source electrode, a gate electrode and a drain electrode. A non-volatile ferroelectric memory transistor includes a bottom electrode formed above a gate region, wherein the bottom electrode has a predetermined area within a peripheral boundary; a ferroelectric layer extending over and beyond the bottom electrode peripheral boundary; and a top electrode formed on said ferroelectric layer.

Abstract: A semiconductor device having: a substrate having a first area and a second area surrounding the first area; an insulating film formed in the second area; electrodes formed above the surface of the substrate in the first area; dielectric films formed above the electrodes; and an opposing electrode formed above the dielectric films, wherein the shape of a side wall of the insulating film includes a shape reflecting the outer peripheral shape of a side wall of the electrode facing the side wall of the insulating film. The semiconductor device of high integration, low cost and high reliability can be realized.

Abstract: When a digital video signal inputted to a latch circuit is Hi electric potential, undesirably a current flows continuously for one horizontal period at maximum, and this causes a great increase in power consumption of a semiconductor device. Therefore an object of the present invention is to provide a display device in which power consumption can be reduced by minimizing occurrence of the current path during the circuit operation, as well as a driving method. The present invention provides a semiconductor device in which two outputs, a non-inverted output and an inverted output, are obtained when a digital video signal is inputted and therefore occurrence of the current path can be minimized in a downstream buffer driven by these signals. Furthermore, a semiconductor device with reduced power consumption is provided by using the structure described above.

Abstract: In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: A system for generating a reference voltage is provided that includes a first p-type, thick-gate transistor, a second p-type, thick-gate transistor, a third p-type, thick-gate transistor, and a fourth p-type, thick-gate transistor. The first p-type transistor has a source that is coupled to an external power supply, a gate, and a drain that is coupled to the gate. The second p-type transistor has a source that is coupled to the drain of the first p-type transistor, a gate, and a drain that is coupled to the gate. The third p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive a mode indicator, and a drain that is coupled to ground. The fourth p-type transistor has a source that is coupled to the drain of the second p-type transistor, a gate that is operable to receive an inverted mode indicator, and a drain that is coupled to ground.

Abstract: A charge transfer device is provided which is capable of reducing a reset field-through noise in a stable manner without being affected by characteristics of transistors and without occurrence of a mustache-shaped pulse-like noise. The charge transfer device is made up of a floating diffusion region used to convert a signal charge transferred from a CCD (Charge Coupled Device) into a voltage, resetting unit used to eject the signal charge accumulated in the floating diffusion region in response to a reset pulse, a first stage source follower used to current-amplify the voltage and second stage source follower in which load is changed in response to the reset pulse and which is used to current-amplify an output voltage of the first stage source follower.

Abstract: A semiconductor integrated circuit includes a plurality of functional circuits, a plurality of signal transmission lines disposed to interconnect among the functional circuits for transfer of a plurality of control signals which are to be supplied to respective functional circuits and are different in timing from one another, and a control circuit for generation of the control signals. The control circuit has a plurality of stages of control signal generator circuits that generate and issue the control signals respectively. The control signal generator circuits are specifically linked together so that when one generator circuit at a certain stage generates at its output a control signal to be transferred over a corresponding signal line, another circuit at the next stage is activated in response to receipt of this control signal.

Abstract: A charge transfer device has a charge transfer region under charge transfer electrodes for stepwise conveying charge packets through potential wells to a floating diffusion region, and the charge transfer region has a boundary sub-region contracting toward the floating diffusion region, wherein the final potential well is created at a certain portion in said boundary sub-region close to the floating diffusion region so that each charge packet travels over a short distance, thereby enhancing a charge transfer efficiency.

Abstract: A simulation circuit for MOS transistors is provided in which neither oscillation nor a change in a characteristic of feedback capacitance occurs. A ratio of a junction capacitance characteristic of a third diode and an electrostatic capacity characteristic of a capacitor to be displayed, changes in response to a change in a voltage between a drain and a gate and the junction capacitance characteristic of the third diode and the electrostatic capacity characteristic of the capacitor are displayed at an equal ratio in a region where a voltage between the drain and gate is almost 0 (zero) V and, therefore, normal simulation testing can be done and no oscillation occurs. Moreover, since no resistor component is connected in series in the third diode and the capacitor, there is no time constant. Therefore, a characteristic curve of the feedback capacitance can be normally obtained irrespective of the change rate of the voltage between the drain and gate.

Abstract: The present invention relates to a CMOS active pixel sensor which includes a compensation circuit capable of compensating a lowered pixel voltage output due to leakage current of a photodiode. The CMOS active pixel sensor having a light sensing unit for generating an output voltage when light is incident thereupon, the sensing unit having an amount of leakage current before the incidence of light. A reset unit resets the output voltage of the light sensing unit to an initial reset voltage in response to a reset signal. A sense transistor has a source, a drain coupled to a power source voltage, and a gate coupled to the output of the light sensing unit. A select transistor has a drain connected to a source of the sense transistor, and provides the voltage of the sense transistor to a bit line, in response to a select signal. A compensation unit supplies a voltage corresponding to the output voltage of the light sensing unit lowered by the leakage current.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.

Abstract: In a charge transfer device and a driving method therefor, electrons are injected through an insulating film into floating gate 108 or electrons are extracted through the insulating film from the floating gate 108, whereby the potential of the floating gate is converged to a fixed voltage.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A semiconductor integrated circuit, particularly a circuit for a high-speed low-power-consumption table look-aside buffer mounted in a microprocessor LSI. The semiconductor integrated circuit is provided with field effect transistors for comparing inputted multibit data signals with stored data and a coincidence-detecting signal line (25) to which current is applied at least while the data signals are compared with stored data. When the data signals coincide with the stored data, the transistors (26) conduct. The number of transistors (26) is equal to that of the inputted data signals. The drains of the transistors (260 are connected in parallel, and the sources are also connected in parallel and supplied with a predetermined voltage. By the integrated circuit, whether or not the inputted data signals coincide with the stored data is detected by detecting the potential of the coincidence-detecting signal line (25) upon a change of the applied current.

Abstract: This invention is directed to a capacitor having a multilevel interconnection technology. At least one solder ball is reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contact. On this reflowed solder ball a cap of low melting point metal is secured. This can be done in a number of ways. The preferred way is to positioning a mask over the solder ball such that a portion of the solder ball is exposed through openings in the mask. At least one layer of a low melting point metal is deposited on the exposed surface of the solder ball through the mask, and thereby forming a capacitor with a multilevel interconnect cap. The low melting point metal can interact with the surface of the solder ball to form a cap of an eutectic or a liquefied portion. The cap portion can then be joined to the object.

Abstract: A charge transfer device is disclosed in which the number of transfer clocks can be decreased, and also, power consumption, the heating amount and parasitic emissions are also reduced. Three groups of electrodes are repeatedly disposed in an alternating sequence above an N-type channel (transfer channel). Among the three groups of electrodes, a predetermined DC bias voltage supplied from a DC power supply is applied to one group of electrodes. Between the remaining two groups of electrodes, a single-phase transfer clock H.phi. supplied from the exterior of the device is directly applied to one group of electrodes, while a transfer clock H.phi.' produced by delaying the transfer clock H.phi. by a predetermined delay time in a delay circuit is applied to the other group of electrodes. Also disclosed is a solid-state imaging apparatus using the above-described charge transfer device.

Abstract: Channel coupled feedback- technology for implementing many analog and digital signal processing functions in a single-polysilicon digital IC fabrication process is described. Field effect transistors are constructed having a common channel and the substrate regions of the field effect transistors in the channel are electronically connected. Thus, a fixed amount of charge can freely move within the channel in response to the application of the signal to be processed. By sensing the charge transferred within the channel when the input signal is applied, many signal processing functions are possible. Fixed-gain amplifiers, offset compensated amplifiers, integrators, differentiators, analog-to-digital converters, digital-to-analog converters, switchable gain amplifiers, automatic gain control systems, and linear transform computation circuits are constructed entirely with field effect transistors, eliminating the need for passive components for most signal processing functions.