Changing Width Or Direction Of Channel (e.g., Meandering Channel) Patents (Class 257/240)
  • Patent number: 11296421
    Abstract: An antenna module includes: an IC package including an IC; first and second antenna portions including respective patch antenna patterns, respective feed vias connected to the respective patch antenna patterns, and respective dielectric layers surrounding the respective feed vias; and a connection member having an upper surface on which the first and second antenna portions are disposed and a lower surface on which the IC package is disposed, the connection member forming an electrical connection path between the IC and the feed via of the first antenna portion and an electrical connection path of the second antenna portion. The connection member includes a first region disposed between the IC package and the first antenna portion, a second region on which the second antenna portion is disposed, and a third region electrically connecting the first and second regions and being more flexible than the dielectric layer of the first antenna portion.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 5, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myeong Woo Han, Ju Hyoung Park, Dae Ki Lim, Jeong Ki Ryoo, Won Cheol Lee, Nam Ki Kim
  • Patent number: 11088154
    Abstract: A semiconductor device includes a first dielectric layer, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, an ferroelectric random-access memory (FeRAM) cell in the second dielectric layer, a third dielectric layer over the second dielectric layer, and a second conductive feature in the third dielectric layer, the second conductive feature being electrically coupled to the top electrode. The FeRAM cell includes a bottom electrode contacting the first conductive feature, a ferroelectric material layer completely covering an upper surface of the bottom electrode, and a top electrode on the ferroelectric material layer.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sai-Hooi Yeong, Chi On Chui
  • Patent number: 10734704
    Abstract: An antenna package includes a patterned antenna structure and an encapsulant. The patterned antenna structure includes a first surface, a second surface opposite the first surface and a third surface extended between the first surface and the second surface. The encapsulant is disposed on the first surface of the patterned antenna structure. The third surface of the patterned antenna structure includes a first portion covered by the encapsulant and a second portion exposed from the encapsulant.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: August 4, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee
  • Patent number: 10712595
    Abstract: The present disclosure relates to a full screen module and a smartphone. The full screen module includes a display panel, a driving chip electrically connected to the display panel, a first flexible circuit board electrically connected to the driving chip, a photoreceptor panel configured on the display panel, and a second flexible circuit board electrically connected to the photoreceptor panel and the first flexible circuit board. The photoreceptor panel is configured to receive light signals, to transform the light signals into digital signals, and to transmit the digital signals to the driving chip. The driving chip is configured to transform the digital signals into data signals, and to drive the display panel to display images. The photoreceptor panel may replace the front camera module of the conventional smartphone. As such, the screen ration of the smartphone may be improved.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: July 14, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Sijie Yang
  • Patent number: 10714822
    Abstract: A wireless module, including: a substrate; an electronic circuit mounted in a first region on a one face of the substrate; a conductive pattern formed in a second region on another face of the substrate and serving as an antenna; a resin layer sealing the electronic circuit in the first region; and a shielding layer formed on a surface of the resin layer and having conductivity.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 14, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Jin Mikata, Masaya Shimamura, Mikio Aoki, Takehiko Kai, Taiji Ito
  • Patent number: 10665936
    Abstract: A wireless module, including: a substrate; an electronic circuit mounted in a first region on a one face of the substrate; a conductive pattern formed in a second region on another face of the substrate, the conductive pattern being connected to a radio communication section of the electronic circuit, and the conductive pattern serving as an antenna when transmitting/receiving radio wave, the second region being different from the first region; a resin layer sealing the electronic circuit in the first region; a shielding layer formed on a surface of the resin layer; and a shield disposed in either one of a top layer of the substrate and an inner layer of the substrate, the shield being for shielding noise radiated from the electronic circuit.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Jin Mikata, Masaya Shimamura, Mikio Aoki, Takehiko Kai, Taiji Ito
  • Patent number: 10121751
    Abstract: A semiconductor module comprises an integrated circuit device, the IC device embedded in a compound material, wherein the compound material at least partially extends lateral to the IC device. The semiconductor module further comprises interconnect structures arranged lateral to the IC device to provide at least one external electrical contact; a patch antenna structure integrated in the semiconductor module and electrically connected to the IC device and a layer interfacing the IC device and the compound, wherein the layer comprises first and second planar metal structures coupled to the IC device, wherein the first planar metal structure is electrically connected to the IC device and the interconnect structures and wherein the second planar metal structure is electrically connected to the IC device and the patch antenna structure.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: November 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Patent number: 10062722
    Abstract: An image sensor includes a pixel array having plurality of pixel cells arranged into a plurality of rows and a plurality of columns of pixel cells in a first semiconductor die. A plurality of pixel support circuits are arranged in a second semiconductor die that is stacked and coupled together with the first semiconductor die. A plurality of interconnect lines are coupled between the first and second semiconductor dies, and each one of the plurality of pixel cells is coupled to a corresponding one of the plurality of pixel support circuits through a corresponding one plurality of interconnect lines. A plurality of shield bumps are disposed proximate to corners of the pixel cells in the pixel array and between the first and second semiconductor dies such that each one of the plurality of shield bumps is disposed between adjacent interconnect lines along a diagonal of the pixel array.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: August 28, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Sohei Manabe, Keiji Mabuchi, Takayuki Goto, Vincent Venezia, Boyd Albert Fowler, Eric A. G. Webster
  • Patent number: 9748231
    Abstract: A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: August 29, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Makoto Yasuda, Taiji Ema, Mitsuaki Hori, Kazushi Fujita
  • Patent number: 9660014
    Abstract: A semiconductor device includes: a semiconductor substrate; and a thin film resistor formed over an upper surface of the semiconductor substrate, the thin film resistor including first thin film resistor units and second thin film resistor units alternately connected in series, each of the first thin film resistor units having an elongated main portion and end portions that are connected to the elongated main portion, the end portions each forming a U-shape together with the elongated main portion in a plan view, and respectively overlapping with two of the second thin film resistor units that are adjacent to and connected to the first thin film resistor unit in series.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 23, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaru Saito
  • Patent number: 9502529
    Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: November 22, 2016
    Assignee: SONY CORPORATION
    Inventor: Yasushi Tateshita
  • Patent number: 9425284
    Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: August 23, 2016
    Assignee: SONY CORPORATION
    Inventor: Yasushi Tateshita
  • Patent number: 9041000
    Abstract: A thin film transistor array substrate includes: a driving thin film transistor including an active layer having a bent shape, where the active layer includes: a first active pattern extending substantially in a first direction; and a second active pattern extending substantially in a second direction perpendicular to the first direction and connected to the first active pattern, and a gate electrode disposed on the active layer, where gate electrode overlaps the first active pattern and exposes the second active pattern; and a capacitor including a first electrode defined by the gate electrode of the driving thin film transistor, and a second electrode disposed on the first electrode, where the second electrode overlaps substantially an entire surface of the first electrode.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 26, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Mu-Kyung Jeon
  • Patent number: 9000526
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 8921902
    Abstract: An object is to provide a semiconductor device with improved reliability in which a defect stemming from an end portion of a semiconductor layer provided in an island shape is prevented, and a manufacturing method thereof. Over a substrate having an insulating surface, an island-shaped semiconductor layer is formed, a first alteration treatment is performed, a first insulating film is formed on a surface of the island-shaped semiconductor layer, the first insulating film is removed, a second alteration treatment is performed on the island-shaped semiconductor from which the first insulating film is removed, a second insulating film is formed on a surface of the island-shaped semiconductor layer, and a conductive layer is formed over the second insulating film. An upper end portion of the island-shaped semiconductor layer has curvature by the first alteration treatment and the second alteration treatment.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoru Okamoto
  • Patent number: 8901673
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: December 2, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Takamitsu Onda
  • Patent number: 8878256
    Abstract: In various embodiments, image sensors incorporate multiple output structures by including multiple sub-arrays, at least one of which includes a region of active pixels, a dark pixel region that is fanned and/or slanted, a dark pixel region that is unfanned and unslanted, a horizontal CCD, and an output structure for conversion of charge to voltage.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Shen Wang
  • Patent number: 8878255
    Abstract: In various embodiments, image sensors incorporate multiple output structures by including multiple sub-arrays, at least one of which includes a region of active pixels, a dark pixel region that is fanned and/or slanted, a dark pixel region that is unfanned and unslanted, a horizontal CCD, and an output structure for conversion of charge to voltage.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Shen Wang
  • Patent number: 8835994
    Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph Ervin, Jeffrey B. Johnson, Paul C. Parries, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 8803247
    Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Patent number: 8796744
    Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: August 5, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Xiaolong Ma, Huaxiang Yin, Sen Xu, Huilong Zhu
  • Patent number: 8748945
    Abstract: Image sensors are provided. The image sensors may include first and second stacked impurity regions having different conductivity types. The image sensors may also include a floating diffusion region in the first impurity region. The image sensors may further include a transfer gate electrode surrounding the floating diffusion region in the first impurity region. Also, the transfer gate electrode and the floating diffusion region may overlap the second impurity region.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Cheol Shin
  • Patent number: 8643073
    Abstract: A plurality of pixels PX include effective pixels and optical black pixels. Signal lines VL are provided corresponding to each column of the pixels PX and supplied with output signals of the pixels PX of the corresponding column. Clip transistors CL are provided corresponding to the respective signal lines VL and limit a potential of the corresponding vertical signal lines VL based on a gate potential. At least in a predetermined operating mode, a potential Vclip_dark is supplied to a gate of one of the clip transistors CL corresponding to at least one pixel column formed of the optical black pixels when reading a noise level from the pixels PX corresponding to the clip transistors CL and when reading a data level from the pixels PX corresponding to the clip transistors CL.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: February 4, 2014
    Assignee: Nikon Corporation
    Inventor: Toru Shima
  • Patent number: 8637910
    Abstract: An image sensor includes an active region including a photoelectric conversion region and a floating diffusion region, which are separated from each other, defined by a device isolation region on a semiconductor substrate, and a transfer transistor including a first sub-gate provided on an upper surface of the semiconductor substrate and a second sub-gate extending within a recessed portion of the semiconductor substrate on the active region between the photoelectric conversion region and the floating diffusion region, wherein the photoelectric conversion region includes a plurality of photoelectric conversion elements, which vertically overlap each other within the semiconductor substrate and are spaced apart from the recessed portion.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: January 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junemo Koo, Ihara Hisanori, Yoondong Park, HoonSang Oh, Sangjun Choi, HyungJin Bae, Tae Eung Yoon, Sungkwon Hong
  • Patent number: 8552510
    Abstract: A semiconductor device includes: a substrate; a transistor that has a ring-shaped gate electrode formed on the substrate; a plurality of external dummy electrodes that are arranged outside the gate electrode and are formed in the same layer as the gate electrode; and at least one internal dummy electrode that is arranged inside the gate electrode and is formed in the same layer as the gate electrode.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 8, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Takamitsu Onda
  • Patent number: 8487352
    Abstract: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: July 16, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung
  • Patent number: 8436402
    Abstract: An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region. The dots arrayed in a row or a column of the first transmission region, which is adjacent to the second transmission region, have an area intermediate between areas of dots arrayed on both sides of the row or the column.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 7, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ken Tomita
  • Patent number: 8377758
    Abstract: A thin film transistor for a thin film transistor liquid crystal display (TFT-LCD), an array substrate and manufacturing method thereof are provided. The thin film transistor comprises a source electrode, a drain electrode, and a channel region between the source electrode and drain electrode. A source extension region is connected with the source electrode, a drain extension region is connected with the drain electrode, and the source extension region is disposed opposite to the drain extension region to form a channel extension region therebetween.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: February 19, 2013
    Assignee: Beijing Boe Optoelectronics Technology Co., Ltd.
    Inventors: Xinxin Li, Wei Wang, Chunping Long
  • Patent number: 8294079
    Abstract: Each of even-numbered photodiodes 1 and 2 for constituting a diode of the present invention (i) has regions (regions 1a through 1c and regions 2a through 2c) whose sizes in a certain direction are identical to sizes of regions of a reference diode 5, and (ii) has a channel width equal to ½ of a channel width W of the reference diode 5. The regions 1a through 1c and the regions 2a through 2c are arranged so as to (i) extend parallel to the certain direction which is provided parallel to a channel length L of the reference diode 5, and so as to be (ii) line-symmetric or point-symmetric to each other as a whole. The photodiodes 1 and 2 are electrically connected to each other in series so as to carry out an equivalent operation to that of the reference diode 5. Employing of the photodiodes 1 and 2 provides a configuration of diodes each having an identical characteristic and occupying a reduced area on a substrate.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: October 23, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kohei Tanaka, Christopher Brown
  • Patent number: 8264029
    Abstract: The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density, and a method of manufacturing such a semiconductor device. The semiconductor device includes: first bit lines formed on a substrate; an insulating layer that is provided between the first bit lines on the substrate, and has a higher upper face than the first bit lines; channel layers that are provided on both side faces of the insulating layer, and are coupled to the respective first bit lines; and charge storage layers that are provided on the opposite side faces of the channel layers from the side faces on which the insulating layers are formed.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: September 11, 2012
    Assignee: Spansion LLC
    Inventors: Yukio Hayakawa, Hiroyuki Nansei
  • Patent number: 8232583
    Abstract: The objective is to develop a device that generates power with high efficiency and utilizes the obtained electrical energy effectively without external combustion energy such as fossil fuels or the like. Electrical energy is obtained by carriers passing through a potential barrier due to a field effect, and thus energy is pre-supplied to the carriers to increase the number of carriers contributing to electrical energy generation, whereby a highly efficient field power generation device can be realized.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: July 31, 2012
    Inventor: Norio Akamatsu
  • Patent number: 8203151
    Abstract: A method for fabricating a semiconductor device includes the steps of forming a SiC film, forming trenches at a surface of the SiC film, heat-treating the SiC film with silicon supplied to the surface of the SiC film, and obtaining a plurality of macrosteps to constitute channels, at the surface of the SiC film by the step of heat-treating. Taking the length of one cycle of the trenches as L and the height of the trenches as h, a relation L=h(cot ?+cot ?) (where ? and ? are variables that satisfy the relations 0.5??, ??45) holds between the length L and the height h. Consequently, the semiconductor device can be improved in property.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: June 19, 2012
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8203875
    Abstract: An anti-parallel diode structure and method of fabrication is presently disclosed. In some embodiments, an anti-parallel diode structure has a semiconductor region comprising a first insulator layer disposed between a first semiconductor layer and a second semiconductor layer. The semiconductor region can be bound on a first side by a first metal material and bound on a second side by a second metal material so that current below a predetermined value is prevented from passing through the semiconductor region and current above the predetermined value passes through the semiconductor region.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: June 19, 2012
    Assignee: Seagate Technology LLC
    Inventors: Nurul Amin, Insik Jim, Venugopalan Vaithyanathan, Wei Tian, YoungPil Kim
  • Patent number: 8115237
    Abstract: A solid-state image pickup element comprises a first-conductive type planar semiconductor layer formed on a second-conductive type planar semiconductor layer, a hole portion formed in the first-conductive type planar semiconductor layer to define a hole therein, and a first-conductive type high-concentration impurity region formed in a bottom wall of the hole portion. The solid-state image pickup element also includes a first-conductive type high-concentration impurity-doped element isolation region, a second-conductive type photoelectric conversion region, a transfer electrode formed on the sidewall of the hole portion through a gate dielectric film, a second-conductive type CCD channel region, and a read channel formed in a region of the first-conductive type planar semiconductor layer sandwiched between the second-conductive type photoelectric conversion region and the second-conductive type CCD channel region.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 14, 2012
    Assignee: Unisantis Electronics Singapore PTE Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 8080842
    Abstract: Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode includes stacked conductive and semiconductor layers, but the peripheral gate electrode includes stacked semiconductor layers. The conductive layer of the cell gate electrode is different from the lowest semiconductor layer of the peripheral gate electrode in material, which can improve characteristics of memory cells and peripheral transistors without causing mutual interference with each other.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: December 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chang-Hyun Lee
  • Patent number: 8039889
    Abstract: A non-volatile memory device includes a semiconductor substrate having a first section including a substantially planar first top surface, a second section including a substantially planar second top surface, and a sidewall extending between the first and second top surfaces. The second top surface of the substrate is closer to a bottom surface of the substrate than is the first top surface. A charge storage pattern extends on the first and second top surfaces of the substrate and along the sidewall therebetween. A source region in the first section of the substrate extends from the first top surface into the second section of the substrate and has a stepped portion defined by the sidewall and the second top surface. Related fabrication methods and methods of operation are also discussed.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Weon-Ho Park
  • Patent number: 8039876
    Abstract: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Kim, Tae-Young Chung
  • Patent number: 8035169
    Abstract: A technique that makes it possible to suppress a crystal defect produced in an active area and thereby reduce the fraction defective of semiconductor devices is provided. A first embodiment relates to the planar configuration of SRAM. One of the features of the first embodiment is as illustrated in FIG. 4. That is, on the precondition that the active areas in n-channel MISFET formation regions are all configured in the isolated structure: the width of the terminal sections is made larger than the width of the central parts of the active areas. For example, the terminal sections are formed in an L shape.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Ishida, Atsushi Maeda, Minoru Abiko, Takehiko Kijima, Takashi Takeuchi, Shoji Yoshida, Natsuo Yamaguchi, Yasuhiro Kimura, Tetsuya Uchida, Norio Ishitsuka
  • Patent number: 7999290
    Abstract: An organic electroluminescent device includes first and second substrates facing each other and spaced apart from each other; a gate line on an inner surface of the first substrate; a data line and a power line crossing the gate line and spaced apart from each other; a switching thin film transistor connected to the gate line and the data line; a driving thin film transistor connected to the switching thin film transistor and the power line, the driving thin film transistor including a channel region having a ring shape; an electric connection pattern connected to the driving thin film transistor, the connection pattern being disposed over the driving thin film transistor; and an organic electroluminescent diode on an inner surface of the second substrate, the organic electroluminescent diode being connected to the electric connection pattern.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: August 16, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Yong Park
  • Patent number: 7982247
    Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: July 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lionel J. Riviere-Cazaux
  • Patent number: 7956388
    Abstract: It is intended to provide a solid-state image pickup element capable of reducing an area of a read channel to increase a light-receiving area. The solid-state image pickup element comprises a p-type planar semiconductor, a hole formed in the p-type planar semiconductor, a p+-type region formed in a bottom of the hole, a p+-type isolation region formed in a part of a sidewall of the hole and connected to the p+-type region, an n-type photoelectric conversion region formed beneath the p+-type region, a transfer electrode formed on the entire sidewall of the hole through a gate dielectric film, a CCD channel region formed in a top of the p-type planar semiconductor, and a read channel formed in a region of the p-type planar semiconductor between the n-type photoelectric conversion region and the CCD channel region.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: June 7, 2011
    Assignee: Unisantis Electronics (Japan) Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 7897969
    Abstract: A solid-state image pickup device includes a pixel array area in which pixels each including a photoelectric conversion element are two-dimensionally arranged; first control means for performing control such that signals of pixels in a desired region of the pixel array area are sequentially read row by row; and second control means for performing control such that, when the signals of the pixels in the desired region are sequentially read row by row by the first control means, pixels in particular regions below and above the desired region are sequentially reset row by row.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: March 1, 2011
    Assignee: Sony Corporation
    Inventors: Yoshinori Muramatsu, Takahiro Abiru, Takaichi Hirata
  • Patent number: 7880206
    Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: February 1, 2011
    Assignee: Crosstek Capital, LLC
    Inventor: Hee-Jeong Hong
  • Patent number: 7858481
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: December 28, 2010
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Patent number: 7727821
    Abstract: An image sensing device can include one or more image sensing cells. Each image sensing cell can have a charge store element formed from a semiconductor material doped to a first conductivity type. The charge store element can be in contact with a channel region formed from a semiconductor material doped to a second conductivity type. The charge store element can have one or more surfaces for exposure to an image source. Each image sensing cell can also include a charge electrode formed from a semiconductor material doped to the first conductivity type that is separated from the charge store element by a semiconductor material doped to the second conductivity type. In addition, one or more current detection electrodes can be included in each image sensing cell. A current detection electrode can pass a current flowing through the channel region in a read operation. Such an image sensing cell can be compact in size and/or have a large image sensing area.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: June 1, 2010
    Assignee: SuVolta, Inc.
    Inventor: Madhu B. Vora
  • Patent number: 7723741
    Abstract: Methods of packaging microelectronic imagers and packaged microelectronic imagers. An embodiment of such a method can include providing an imager workpiece having a plurality of imager dies arranged in a die pattern and providing a cover substrate through which a desired radiation can propagate. The imager dies include image sensors and integrated circuitry coupled to the image sensors. The method further includes providing a spacer having a web that includes an adhesive and has openings arranged to be aligned with the image sensors. For example, the web can be a film having an adhesive coating, or the web itself can be a layer of adhesive. The method continues by assembling the imager workpiece with the cover substrate such that (a) the spacer is between the imager workpiece and the cover substrate, and (b) the openings are aligned with the image sensors. The attached web is not cured after the imager workpiece and the cover substrate have both been adhered to the web.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 25, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Warren M. Farnworth, Alan G. Wood, James M. Wark, David R. Hembree, Rickie C. Lake
  • Patent number: 7692217
    Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: April 6, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
  • Patent number: 7646042
    Abstract: When capacity coupling between an output gate electrode (OG) and a last-stage transfer electrode is large at an output end of a CCD shift register, an electric potential of the OG is varied according to transfer clocks with the result that noise is liable to generate in an output signal. As measures for this, convex portions projecting horizontally are formed in those positions of the last-stage transfer electrode and the OG, which correspond to a channel region, and overlap between the electrodes is caused only on the convex portions. A clearance is formed between the OG and the transfer electrode except those locations, in which the convex portions are provided. In that location, in which the OG and the transfer electrode, respectively, are extended relatively lengthily toward wirings, the electrodes do not overlap each other. In this manner, capacity coupling between the electrodes is reduced.
    Type: Grant
    Filed: January 19, 2006
    Date of Patent: January 12, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Takahiko Ogo
  • Patent number: 7608871
    Abstract: A solid image pick-up element comprises: a photoelectric converting portion; a charge transmitting portion comprising a charge transmitting electrode that transmits a charge generated by the photoelectric converting portion; and a peripheral circuit portion connected to the charge transmitting portion, wherein a surface level of a field oxide film provided at the peripheral circuit portion and the charge transmitting portion to surround an effective image pick-up region of the photoelectric converting portion is to a degree the same as a surface level of the photoelectric converting portion.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 27, 2009
    Assignee: Fujifilm Corporation
    Inventors: Tsutomu Aita, Hideki Kooriyama, Maki Saito
  • Patent number: 7605411
    Abstract: An HCCD includes a channel 21 that transfers electric charges in an X direction, a channel 25 that transfers the electric charges in a Z1 direction, a channel 23 that transfers the electric charges in a Z2 direction, and a channel 22 that connects the channels 23, 25 to the channel 21. The following relation is satisfied in impurity concentration of the channels: channel 21 channel 22 channel 23, 25. A fixed DC voltage is applied to branch electrodes 12a, 12b above the channel 22. The channel 22 has protrusion portions 19 that protrude inward from an outer circumference, which connects T1 and T2, and an outer circumference, which connects T3 and T4. The protrusion portions 19 causes charges below the transfer electrode 11b to move near the center of the channel 22 in a Y direction. Thereby, the travel distance of the charges in the channel 22 is reduced.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 20, 2009
    Assignee: Fujifilm Corporation
    Inventors: Hirokazu Shiraki, Makoto Kobayashi, Katsumi Ikeda