Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: Transistors and/or methods of fabricating transistors that include a source contact, drain contact and gate contact are provided. In some embodiments, a channel region is provided between the source and drain contacts and at least a portion of the channel regions includes a hybrid layer comprising semiconductor material. In particular embodiments of the present invention, the transistor is a current aperture transistor. The channel region may include pendeo-epitaxial layers or epitaxial laterally overgrown layers. Transistors and methods of fabricating current aperture transistors that include a trench that extends through the channel and barrier layers and includes semiconductor material therein are also provided.

Abstract: A data driving apparatus for a liquid crystal display includes a plurality of data driving integrated circuits adjacent to a liquid crystal display panel for converting input pixel data into pixel voltage signals, one or more multiplexor arrays provided adjacent to the liquid crystal display panel to make a time-division of a plurality of data lines into a plurality of regions to selectively apply the pixel voltage signals from the plurality of data driving integrated circuits to the plurality of data lines.

Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

Abstract: A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the source/drain region.

Abstract: A high-performance solid-state imaging device is provided. The solid-state imaging device includes: a plurality of pixel cells; and a driving unit. Each of the plurality of pixel cells includes: a photodiode that converts incident light into a signal charge and stores the signal charge; a MOS transistor that is provided for reading out the signal charge stored in the photodiode; an element isolation portion that is formed of a STI that is a grooved portion of the semiconductor substrate so that the photodiode and the MOS transistor are isolated from each other; and a deep-portion isolation implantation layer that is formed under the element isolation portion for preventing a flow of a charge from the photodiode to the MOS transistor.

Abstract: A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.

Abstract: A sensor includes an array of pixels organized in rows and columns and a plurality of metal busses overlaying the array of pixels. A first column of pixels includes a proximal set of first pixels and a distal set of first pixels separated by a first jog region. A second column of pixels includes a proximal set of second pixels and a distal set of second pixels separated by a second jog region. The first jog region is displaced in a column direction and in a lateral direction transverse to the column direction from the second jog region. A first metal bus is insulatively disposed over both the first and second jog regions.

Abstract: An image processing apparatus capable of acquiring a high resolution image without a reduction in sensitivity includes a plurality of sensor chips connected to one another, each sensor chip including a first pixel row and a second pixel row, which are formed on the same semiconductor chip. The first pixel row has a plurality of pixels arranged in the main scanning direction, and the second pixel row has a plurality of pixels shifted along the main scanning direction with respect to the first pixel row.

Abstract: In a solid-state imaging device, a plurality of vertical charge transfer paths is arranged at a horizontal pitch A within a photoelectric conversion region, and at a pitch B that is smaller than the pitch A in a portion where the signals are input into the horizontal charger transfer path. A read-out amplifier and a horizontal charge transfer path for receiving signals from vertical charge transfer paths are provided for each photoelectric conversion block into which the photoelectric conversion region has been partitioned. The read-out amplifiers have the same shape and their positional relation is one of parallel displacement in regions that are obtained by changing the pitch of the vertical charge transfer portions. Thus, a solid-state imaging device is achieved that is not so easily influenced by mask misalignments or skewed ion implantation angles, and in which signal read-out at high speeds is possible.

Abstract: In a solid-state image pickup device in which a large number of photoelectric converters are disposed in a shifted-pixel layout, a charge transfer channel configuring a vertical transfer CCD includes a section having a first width and being contiguous to a readout gate region and a section having a second width and being separated therefrom. The first width is less than the second width. Alternatively, a relative positional relationship between each photoelectric converter and the readout gate region corresponding thereto is fixed for all pixels. This makes it possible to easily prevent the event in which the light collecting efficiency and sensitivity of each pixel vary between two adjacent pixel rows. It is also possible to increase the pixel density while suppressing the decrease in area of the light receiving section of each pixel.

Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: According to one exemplary embodiment, a structure comprises a laminate substrate having a top surface for receiving a semiconductor die. The structure further comprises an antenna element situated on the top surface of the laminate substrate, where the antenna element is coupled to a laminate substrate bond pad. For example, the antenna element may also be coupled to the laminate substrate bond pad by a trace on the top surface of the laminate substrate. According to this exemplary embodiment, the structure further comprises a bonding wire that provides an electrical connection between the laminate substrate bond pad and a semiconductor die bond pad. For example, the input impedance of the antenna element coupled to the laminate substrate bond pad may match the output impedance at the semiconductor die bond pad. The structure may further comprise a capacitor coupled to the antenna element.

Abstract: The present invention relates to a method for fabricating a semiconductor transistor device. The method comprises: forming a first conductive type well in a semiconductor substrate having a device isolation film formed thereon; implanting first conductive type impurity ions into the first conductive type well, so as to form a punch-through stopper region; implanting the first conductive type impurity ions into the upper portion of the resulting structure at fixed tilt angle and ion implantation energy, so as to form a channel region; forming a gate electrode including a gate insulating film on the semiconductor substrate; forming LDD regions in the semiconductor substrate at both sides of the gate electrode; forming an insulating spacer film on the side of the gate electrode; and forming source and drain regions in the semiconductor substrate at portions below the sides of the insulating spacer films.

Abstract: In a solid-state image pick-up device of FIG. 1, a plurality of photoelectric converting devices 100 having almost square light receiving regions are provided like a tetragonal grid over the surface of a semiconductor substrate and a plurality of vertical transfer sections 200 are provided corresponding to the respective photoelectric converting device strings respectively. The vertical transfer section 200 includes a vertical transfer channel and a plurality of vertical transfer electrodes provided on the upper layer of the vertical transfer channel, and the vertical transfer channel is provided in winding shape between the photoelectric converting devices 100 constituting the corresponding photoelectric converting device strings.

Abstract: A local oscillation FET has a source connecting pad, a drain connecting pad and a gate connecting pad. The source connecting pad occupies one corner of a substrate, and the drain and gate connecting pads are placed at the neighboring corners so that the three connecting pads form an L shape on the substrate. As a modification to this configuration, another source connecting pad is placed at the remaining corner of the substrate so that the drain and gate connecting pads are shielded from each other by the two source connecting pads. These device configurations contribute to size reduction of the local oscillation FET.

Abstract: Disclosed herein is a solid-state imaging device having an effective pixel portion, an optical black portion, and a charge transfer register portion commonly provided in the effective pixel portion and the optical black portion, wherein the register width of a portion of the charge transfer register portion in the optical black portion is set larger than the register width of a portion of the charge transfer register portion in the effective pixel portion. With this configuration, the general dynamic range in the solid-state imaging device can be improved.

Abstract: A charge-coupled device (CCD) includes first-level transfer electrodes and second-level transfer electrodes alternately arranged along a transfer channel, wherein charge storage sections underlying the first-level transfer electrodes have a larger width than barrier sections underlying the second-level transfer electrodes. First and second interconnect lines supply two-phase driving signals to the transfer electrodes. Contact plugs connecting the first interconnect line to the transfer electrodes and contact plugs connecting the second interconnect line are located at opposite sides with respect to the center line of the transfer channel.

Abstract: A honeycomb CCD, whose light receiving portion and a certain light receiving portion 105 adjoining thereto are arranged at a position to be shifted by half a pixel pitch in line and row directions, has charge transfer electrodes 111-114 formed of double-layered polysilicon electrode, a metal wiring 125, having smaller resistivity thereto, which is arranged in the longitudinal direction along each VCCD to intersect and cross over the charge transfer electrodes 111-114 being connected by a contact hole 126, by which electrical resistance of the polysilicon layer of the charge transfer electrodes can be lowered without increasing thickness thereof.

Abstract: A method for forming a high-k gate dielectric film (106) by CVD of a M-SiN or M-SION, such as HfSiO2. Post deposition anneals are used to adjust the nitrogen concentration.

Abstract: As solid-state image pickup devices are spread in the world, improvement of performance and reduction of the production cost thereof are required. It is difficult for the solid-state image pickup devices of a configuration of the prior art to meet the requirements. In a solid-state image pickup device to meet the requirements, a large number of photoelectric converters are disposed in a surface of a semiconductor substrate in of a matrix pattern having a plurality of row and a plurality of column, a vertical charge transfer channel is arranged for each column of the photoelectric converters, and a read-cum-transfer electrode is formed for each row of the photoelectric converters such that the read-cum-transfer electrode surrounds each photoelectric converter element of the associated row of the photoelectric converters in a plan view.

Abstract: A three-dimensional ferroelectric structure and fabrication method are provided. The ferroelectric capacitor structure permits immediate contact between a noble metal capacitor electrode and a transistor electrode. This direct connection minimizes process steps and electrical resistance between capacitor and transistor. A damascene capacitor electrode formation process makes the task of etching the noble metal less critical. Regardless of whether a noble metal capacitor electrode is used, the damascene formation process permits both larger, and more space efficient, capacitors. Further, the damascene capacitor formation process can be used to simultaneously form electrical interlevel interconnections to the transistor drain. Another variation of the invention provides for a dual damascene version of the ferroelectric capacitor.

Abstract: An image pickup device is provided with a reduced profile. There is provided a circuit board that is formed with a predetermined circuit pattern having bonding portions and which has a through hole, a pickup element that has a light-receiving portion and bonded portions and which is secured to one surface of the circuit board by bonding the bonded portions to the bonding portions of the circuit pattern, and a cover body which has a lens portion for guiding incident light to the light-receiving portion of the pickup element through the through hole of the circuit board and that is secured to another surface of the circuit board opposite to the above-mentioned surface such that the through hole is covered.

Abstract: In a solid-state image pickup device, a transfer register 10 is provided with an overflow control gate OFCG and an overflow drain OFD, and the gate electrode 12A of the overflow control gate OFCG is formed so as to be superposed on the lower-layer electrodes St1, 13 of the transfer register 10 side and the overflow drain OFD side.

Abstract: A CCD device incorporates Charge Multiplication in its CCD registers together with charge domain Dynamic Range compression. This structure preserves the high dynamic range available in the charge domain of these devices, and avoids limiting it by an inadequate voltage swing of the charge detection nodes and amplifiers. The Dynamic Range compression is logarithmic from a predetermined built in threshold and noiseless. The technique has an additional advantage of maintaining the compact size of the registers, and the registers may also include antiblooming devices to prevent blooming.

Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

Abstract: In transistors with sub-micron channels, short-channel effects, such as a lowering of the threshold voltage, are usually suppressed by means of a halo (or pocket) implant in the source/drain regions, which operation is performed jointly with the LDD implantation. The halo implant, however, decreases the analog performance of transistors. To combine suppression of short-channel effects with a high analog performance, it is proposed to provide only transistors T1, which are not intended for analog functions with the halo implant (16), and to mask the analog transistors T2 with a mask (15) against the halo implant. To avoid short-channel effects in T2, this transistor is provided with a channel whose length is larger than that of transistor T1.

Abstract: An electronic component having an image sensing device (41, 71, 86, 132, 182, 212) and a method for improving pixel charge transfer in the image sensing device (41, 71, 86, 132, 182, 212). The image sensing device (41, 71, 86, 132, 182, 212) has a transfer gate (42, 82) between a source region (43, 83) and an image sensing region. The image sensing region is formed to have a wider device width proximate to the transfer gate (42, 82) than at a point distal from the transfer gate (42, 82).

Abstract: The invention provides a semiconductor device, manufactured with low manufacturing costs, that prevents the breakdown voltage from lowering.

Abstract: To improve such a fact that a signal electric charge from a sensor unit in an MOS imaging device can not be completely read out by a low read-out voltage. To this end, in an arrangement in which a plurality of unit pixels each of which has a sensor unit (S) with a photoelectric conversion region (20) as well as an insulating gate transistor MOS for reading out a signal electric charge from the sensor unit (S) are disposed, a photoelectric conversion region of the sensor unit (S) is so constructed as to form a single potential dip for the signal electric charge and a gate electrode (18) of the insulating gate transistor (MOS) is formed into a pattern in which the middle portion in a channel width direction thereof is positioned above the central portion of the potential dip or its vicinity.

Abstract: In a floating diffusion output type or a floating gate output type charge-to-voltage converter, the floating diffusion or the floating gate is coupled to one or more diffusion regions by means of one or more switch elements, and such elements are selectively turned on or off in such a manner that the the charge-to-voltage conversion factor is raised to obtain a great voltage amplitude when a small quantity of signal charge is input, or the conversion factor is lowered to obtain a small voltage amplitude when a large quantity of signal charge is input.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: There is provided a charge transfer device including (a) a charge transfer channel for transferring signal charges therethrough, (b) a floating diffusion region for accumulating therein charges transferred from the charge transfer channel, (c) a field effect transistor for resetting the floating diffusion region so that the floating diffusion region is at a predetermined potential and (d) a bias charge input section through which a bias charge is supplied and which is connected to either the charge transfer channel or the floating diffusion region. The field effect transistor includes a reset gate electrode and a reset drain.

Abstract: The invention relates to a charge-coupled device. Such devices comprise at least one insulated conducting gate (3) connecting two semiconductor zones. According to the invention, each insulated conducting gate (3) has a width progressively increasing from the first semiconductor zone (1) to the second semiconductor zone (2). The width of each gate (3) is sufficiently narrow for the potential well created by the application of a voltage V to the gate to have a depth increasing progressively from the first zone (1) to the second zone (2), thus enabling the charges to be driven away. The invention applies to any type of charge-coupled device and particularly to photodiodes.

Abstract: A solid-state imaging device includes a plurality of sensor portions, and a vertical shift register corresponding to each of a series of sensor portions. A transfer electrode of the vertical shift register is formed of a first electrode and a second electrode which are repeatedly provided corresponding to the respective series of sensor portions and also formed continuously between the sensor portions adjacent to each other in the vertical direction. A signal charge is read out from each of the sensor portions through a portion below a read gate portion of the first electrode between sensor portions located in the vertical direction.

Abstract: A bidirectional horizontal charge transfer device and method includes a charge transfer area formed within a substrate, a plurality of first, second, third and fourth poly gates formed over the charge transfer area,an insulating layer formed between the first, second, third and fourth poly gates, a first clock signal applied to the first and second poly gates, a second clock signal applied to the third and fourth poly gates, and a biasing circuit for selectively applying a bias signal to the first and second clock signals so as to selectively change a charge transfer direction.

Abstract: A semiconductor well region has a groove into which a block-shaped floating gate is formed. The block-shaped floating gate has a bottom surface facing a bottom surface of the semiconductor well region served as a first channel region, a first side surface facing one of side surfaces of the semiconductor well region served as a second channel region, a second side surface facing the other of side surfaces of the semiconductor well region served as a third channel region, thereby a channel width is trebled.

Abstract: A solid state image pickup device includes a semiconductor substrate, a CCD channel region in the semiconductor substrate, a plurality of polygates over the CCD channel regions, and a photoelectric conversion region having a portion above an uppermost surface of the semiconductor substrate.

Abstract: An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combiner for adding the third and sixth charge packets and the fourth and fifth charge packets.

Abstract: A solid-state imaging device used as a linear sensor of the TDI mode in which resolution is improved and moire phenomenon takes place to less degree. This solid-state imaging device comprises first pixel trains comprised of plural pixels, second pixel trains comprised of plural pixels disposed in the state respectively shifted by half pitches in the horizontal and vertical directions with respect to the first pixel trains, a charge storage section for storing signal charges transferred to a signal processing section, first shift electrodes disposed between respective corresponding pixels of the first and second pixel trains and adapted for sequentially transferring signal charges, and second shift electrodes for transferring signal charges of the pixels of the final transfer stage of the first and second pixel trains to the charge transfer section through a shift register and an output circuit.

Abstract: A multidirectional charge transfer device configured in a charge storage medium. The device includes an array of charge storage regions. Each of said charge storage regions includes a plurality of first gates, each of which is arranged in a first portion of each charge storage region, a plurality of second gates, each of which is arranged in a second portion of each charge storage region, a plurality of third gates, each of which is arranged in a third portion of each charge storage region, and a plurality of fourth gates, each of which is arranged in a fourth portion of each charge storage region. The plurality of gates and charge storage regions are configured to define at least three bidirectional charge transfer paths which are noncollinear with respect to each other. The plurality of gates are sequentially biased to establish charge transfer along one of said bidirectional charge transfer paths and forming blocking potentials to charge transfer in the remaining charge transfer paths.

Abstract: An apparatus and method of equalizing a first and second charge packet. The apparatus includes a charge splitter for splitting the first charge packet into a third charge packet on the first side of the charge splitter and a fourth charge packet on the second side of the charge splitter. The second charge component is split into a fifth charge component on the first side of the charge splitter and a sixth charge component on the second side of the charge splitter. The apparatus includes a charge combinet for adding the third and sixth charge packets and the fourth and fifth charge packets.

Abstract: In a charge coupled device having a plurality of output structures, the plurality of output structures including first and second output structures, a channel structure is defined in a channel region beneath a gate electrode and coupled to each of the plurality of output structures. The channel structure includes a plurality of area structures, each area structure being characterized by a uniform potential which is different from the potential characterizing each of the other area structures. The plurality of area structures are arranged within the channel region to define a first increasing stepped potential gradient from any point within the channel region to the first output structure and define a second increasing stepped potential gradient from any point within the channel region to the second output structure.

Abstract: A fast-timing bi-directional charge coupled device ("CCD") is disclosed. The CCD operates at a much faster overall rate than conventional CCD's, while paradoxically slowing down the readout rate of the pixels. Lower power consumption is required, less heat is generated, thermal noise is lower, and digital noise is lower. The novel CCD is capable of 10-25 .mu.sec timing resolution (or even faster). The configuration entirely eliminates the (formerly) rate-determining step of transferring data "horizontally" from the "top" of the CCD columns. Instead, the charges on columns are transferred either "up" or "down" in an alternating manner. For example, the charges in odd-numbered columns might be transferred one row "up" with each clock cycle, and charges in even-numbered columns might be transferred "down." This alternating charge transfer architecture is termed "bi-directional.

Abstract: A transistor having reduced hot carrier implantation is disclosed which is formed on an outer surface (12) of a semiconductor substrate (10). The transistor comprises a source region (22) and a drain region (24) which define there between a channel region (34). A gate insulator layer (14) insulates a gate conductor (16) from the channel region (34). A sidewall insulator body (20) is formed such that a thickened region of insulator separates an end of gate conductor (16) from a portion of channel region (34) proximate drain region (24). This thickened insulator reduces the local electric field in channel region (34) near drain region (24) and correspondingly reduces the implantation into gate insulator (14) of hot carriers generated from impact ionization.

Abstract: The invention relates to a charge coupled device with a buried channel in which charge is detected by a MOST (MOS transistor) incorporated in the channel and having a surface channel of the conductivity type opposed to that of the charge coupled device. The source zone is situated in the centre of the CCD channel and is formed simultaneously with the channel bounding zone. The gate electrode comprises two portions situated on either side of the source zone, which portions, seen at the surface, do not overlap the source and drain zones. Below the gate electrode, a zone is formed of the same conductivity type as but with a higher doping than the CCD channel, which zone forms a charge storage region for the charge packet to be read out during the reading-out process. The source and drain zones are connected to the MOST channel region by means of extensions. The detector can be manufactured in a self-aligned manner, has a high charge storage capacity, a good noise behaviour, and a high speed.

Abstract: A charge transfer device has trapezoidal shape impurity-implanted regions (1, 51, . . . ) in n-type regions (271, 371) at least in the through-paths between a first HCCD (27) and a second HCCD (28), and its isolation regions (41) under the transfer gate (29) are trapezoidal shaped, and thereby charge transfer loss and hence FPN is minimized and the transfer efficiency is much improved.

Abstract: A semiconductor device comprising a source region, a channel region, and a drain region, provided that one or both of the phase boundary between the channel forming region and the source region and that between the channel forming region and the drain region are shaped into an uneven shape, and optionally, periodically. Also claimed is a process for fabricating the same.

Abstract: A CCD shift register includes a first gate electrode, a second gate electrode disposed adjacent to and longitudinally spaced from the first gate electrode, and a buried layer having a first dopant impurity concentration. The first gate electrode is disposed over the buried layer so as to define a first buried layer area. The second gate electrode is disposed over the buried layer so as to define a second buried layer area greater than the first buried layer area. In the buried layer, a trench region is formed so as to have a second dopant impurity concentration greater than the first dopant impurity concentration. The first gate electrode is disposed over the trench region so as to define a first trench area. The second gate electrode being disposed over the trench region so as to define a second trench area less than the first trench area.

Abstract: A photoelectric converter with improved charge transfer efficiency from a light receiving portion. The photoelectric converter includes a light receiving portion having an output end and a gate portion having a first side and a second side that both define a readout gate width for the light receiving portion, where the first side of the gate portion confronts the output end of the light receiving portion. The photoelectric converter also includes a charge transfer portion formed to confront the second side of the gate portion, where the readout gate width of said gate portion is wider at the first side confronting said light receiving portion than at the second side confronting said charge transfer portion.