Abstract: The present invention provides an apparatus for adding or subtracting an amount charge to or from a charge packet in a CCD as the packet traverses the CCD. The apparatus uses a “wire transfer” device structure to perform the addition or subtraction of charge during the charge packets traversal across the device. A pair of electrically interconnected diffusions are incorporated within the charge couple path to provide an amount of charge which can be added or subtracted from packets as the packets traverse the CCD.

Abstract: The present invention provides a water-soluble luminescent quantum dot, a biomolecular conjugate thereof and a composition comprising such a quantum dot or conjugate. Additionally, the present invention provides a method of obtaining a luminescent quantum dot, a method of making a biomolecular conjugate thereof, and methods of using a biomolecular conjugate for ultrasensitive nonisotopic detection in vitro and in vivo.

Abstract: According to one aspect of the invention, a method of constructing a memory array is provided. An insulating layer is formed on a semiconductor wafer. A first metal stack is then formed on the insulating layer and etched to form first metal lines. A polymeric layer is formed over the first metal lines and the insulating layer. A puddle of smoothing solvent is then allowed to stand on the wafer. The smoothing solvent is then removed. After the smoothing solvent is removed, the polymeric layer has a reduced surface roughness. A second metal stack is then formed on the polymeric layer and etched to form second metal lines.

Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.

Abstract: The driving device of a solid-state imaging device comprises a driving unit for driving the solid-state imaging device in either an addition driving mode in which a plurality of pixels are added and read as a single pixel or a non-addition driving mode, and a substrate bias voltage supply for applying a bias voltage to the substrate of the solid-state imaging device according to the driving mode. The substrate bias voltage is set according to the number of pixels added in the addition driving mode so that the overflow level of the charge accumulating portion may be lower in the addition driving mode than in the normal driving mode. This suppresses the input of excess charges to the horizontal transfer path even in the addition driving mode, thereby preventing the generation of horizontal streak noise.

Abstract: An interline transfer type image sensing device that can be operated at high speed and with low image smear is described. The device incorporates a refractory metal layer which is used for both a light shield over the vertical charge transfer region and as a wiring layer for low resistance strapping of poly crystalline silicon (polysilicon) gate electrodes for the vertical charge transfer region. Plugs provided by a separate metallization layer connect the refractory light shield to the polysilicon gate electrode. These plugs allow high temperature processing after refractory light shield patterning for improved sensor performance without degradation of the polysilicon gate electrode or the refractory lightshield layer.

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: In a solid-state imaging device, a plurality of vertical charge transfer paths is arranged at a horizontal pitch A within a photoelectric conversion region, and at a pitch B that is smaller than the pitch A in a portion where the signals are input into the horizontal charger transfer path. A read-out amplifier and a horizontal charge transfer path for receiving signals from vertical charge transfer paths are provided for each photoelectric conversion block into which the photoelectric conversion region has been partitioned. The read-out amplifiers have the same shape and their positional relation is one of parallel displacement in regions that are obtained by changing the pitch of the vertical charge transfer portions. Thus, a solid-state imaging device is achieved that is not so easily influenced by mask misalignments or skewed ion implantation angles, and in which signal read-out at high speeds is possible.

Abstract: A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.

Abstract: In a semiconductor integrated circuit device in which the number of the PMOS transistors to be used is relatively larger than that of the NMOS transistors and the PMOS transistor is used as an output driver, there is provided a semiconductor integrated circuit device having excellent stability, reliability, and performance while being inexpensive, and a manufacturing method thereof. In such a semiconductor integrated circuit device, complementary MOS circuits are composed of a P-type MOSFET (36) and an N-type MOSFET (37) which are a horizontal, an output driver is composed of a P-type vertical MOSFET (38) having a trench structure, and a conductivity type of the gate electrode of the respective MOSFETs is set as a P-type.

Abstract: In a solid-state image sensing device, photoelectric conversion elements are two-dimensionally arrayed in a matrix on a semiconductor substrate. A transfer gate portion is arranged adjacent to each photoelectric conversion element to read signal charges stored in the photoelectric conversion element. A vertical CCD is arranged adjacent to the transfer gate portion to transfer the signal charges read from the photoelectric conversion element in a vertical direction. A horizontal CCD transfers the signal charges transferred from the vertical CCD in a horizontal direction. A charge detection portion detects the signal charges transferred from the horizontal CCD and outputs them. Four vertical transfer electrodes are formed adjacent to each other on the vertical CCD in a vertical transfer direction of the signal charges. The vertical transfer electrodes include first and second transfer electrodes adjacent to each other in the vertical transfer direction.

Abstract: A digital camera including a CCD imager and a complementary color filter mounted on a light receiving surface thereof. The complementary color filter has color blocks each having 8 rows×4 columns while the CCD imager has, at its light receiving surface, pixel blocks corresponding to those color blocks. The color block is assigned in its each row, with all the kinds of color components, i.e., G, Mg, Ye and Cy, at least one in number per kind. A timing generator reads, from respective columns, pixel signals including all the kinds, of color components at least one in number per kind. A timing generator reads from respective rows pixel signals including all tile kinds of color components at least one in number per kind, and transfers the read pixel signals in vertical direction. The timing generator also transfers the pixel signals in a horizontal direction each time vertical transfer by 8 rows has been completed.

Abstract: A controllable field-effect semiconductor component has a semiconductor body including a first surface, a first layer of a first conduction type, and a second layer of the first conduction type lying above the first layer. The semiconductor component also has a first terminal zone that can be contact-connected at the first surface of the semiconductor body. The first terminal zone is formed in the second layer. A channel zone of a second conduction type surrounds the first terminal zone. Compensation zones of the second conduction type that are formed in the second layer are provided. Additionally, the semiconductor component has a second terminal zone of the first conduction type that can be contact-connected at the first surface of the semiconductor body. The second terminal zone is formed in the second layer.

Abstract: According to a disclosed embodiment, a base region is grown on a transistor region. A dielectric layer is next deposited over the base region. The dielectric layer can comprise, for example, silicon dioxide, silicon nitride, or a suitable low-k dielectric. Subsequently, an opening is fabricated in the dielectric layer, and an emitter layer is formed on top of the dielectric layer and in the opening. Thereafter, an anisotropic polymerizing etch chemistry is utilized to etch the emitter layer down to a first depth, forming an emitter region in the opening. Next, a non-polymerizing etch chemistry having isotropic components is used to create a notch in the dielectric layer below the emitter region. The formation of the notch reduces the overlap area of a capacitor that forms between the emitter region and the base region, which translates to a lower level of emitter to base capacitance.

Abstract: A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers.

Abstract: In DRAM memory cells, individual memory cells are isolated from one another by an isolation trench (STI). In such a case, a vertical transistor is formed by the isolation trench as SOI transistor because its channel region is isolated from a substrate by the isolation trench. A vertical transistor that is used, for example, in a DRAM memory cell and a method for making the transistor includes connecting the channel region of the vertical transistor to the substrate by disposing a conductive layer in the isolation trench between a lower insulation filling and an upper insulation filling.

Abstract: There is provided a method of driving a solid-state image sensor, including the steps of transferring signal charges from photoelectric transfer devices to vertical CCDs constituted of a plurality of pixels, when a pulse is applied to the pixel, the pulse being applied to the pixels in at least two pixel lines so that a trailing edge of a first pulse to be applied in a first pixel line corresponds with a leading edge of a second pulse to be applied in a second pixel line, transferring the signal charges from the vertical CCDs to a horizontal CCD, and outputting the signal charges from horizontal CCD to an external circuit. The method makes it possible to prevent an increase in a substrate voltage at which charges are reversely transferred to photodiodes, which increase is caused by simultaneously applying pulses to all signal readers.

Abstract: Signal charges are read out from light-receiving portions during a vertical blanking period by applying a read-out voltage pulse to read-out electrodes that are provided separately from vertical transfer electrodes, while signal charges are prevented from leaking from the light-receiving portions during a vertical scanning period by applying a negative voltage to the read-out electrodes. The read-out voltage pulse also is applied to vertical transfer electrodes, whereby signal charges are read out from the light-receiving portions more efficiently. Signal charges are read out from light-receiving portions in a predetermined region by applying a read-out voltage pulse to read-out electrodes while applying a negative voltage to a part of the vertical transfer electrodes.

Abstract: A flip-chip MOSFET structure has a vertical conduction semiconductor die in which the lower layer of the die is connected to a drain electrode on the top of the die by a diffusion sinker or conductive electrode. The source and gate electrodes are also formed on the upper surface of the die and have coplanar solder balls for connection to a circuit board. The structure has a chip scale package size. The back surface of the die, which is inverted when the die is mounted may be roughened or may be metallized to improve removal of heat from the die. Several separate MOSFETs can be integrated side-by-side into the die to form a series connection of MOSFETs with respective source and gate electrodes at the top surface having solder ball connectors. Plural solder ball connectors may be provided for the top electrodes and are laid out in respective parallel rows. The die may have the shape of an elongated rectangle with the solder balls laid out symmetrically to a diagonal to the rectangle.

Abstract: A solid state image pickup device having: a mode selector for selecting one of first and second modes; a plurality of photoelectric converters for converting received light into electric charges; transfer paths each having a plurality of packets for receiving the electric charges from the plurality of photoelectric converters and transferring the electric charges in each packet; a controller for reading the electric charges from each of the plurality of photoelectric converters and supplying the read electric charges to the transfer paths; and a driver for driving the transfer means in the selected first or second mode at the number of drive phases different from the number of drive phases of the non-selected mode.

Abstract: In an image sensing array, the structure of the image sensor pixel is based on a vertical punch through transistor with a junction gate surrounding its source and connected to it, the junction gate being further surrounded by an MOS gate. The new pixel has a large conversion gain, high dynamic range, blooming protection, and low dark current. It senses charge nondestructively with a complete charge removal, which avoids generation of kTC noise. The pixel fabrication is compatible with CMOS processing that includes two metal layers. The array also includes the pixel reset through column sense lines, polysilicon field plate in the image-sensing area for improved pixel isolation, denser pixel packing, and either n-channel or p-channel addressing transistor.

Abstract: A structure and a process for fabricating a bipolar junction transistor (BJT) that is compatible with the fabrication of a vertical MOSFET is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate, where the substrate includes a buried collector region for the BJT and a source region for the MOSFET. After the at least three layers are formed on the substrate, two windows or trenches are formed in the layers. The first window terminates at the surface of the silicon substrate where the source region has been formed; the second window terminates at the buried collector region. Both windows are then filled with semiconductor material. For the BJT, the bottom portion of the window is filled with material of a conductivity type matching the conductivity of the buried collector, while the upper region of the semiconductor material is doped the opposite conductivity to form the BJT base.

Abstract: The trench-gate (11) of, for example, a cellular power MOSFET comprises doped poly-Si or other semiconductor material (11a) adjacent to the gate dielectric layer (17) adjacent to the channel-accommodating region (15) of the device. The gate (11) also comprises a sizeable silicide part (11b) that reduces gate resistance. This silicide part (11b) protrudes upwardly from the trench (20) over a distance (z) typically larger than the width (w) of the trench (20), so forming an upstanding part (11b) of a metal silicide material between its top and sidewalls above the level of the body surface (10a). The gate dielectric layer (17) at least adjacent to the channel-accommodating region (15) is protected from the metal silicide by at least the semiconductor part (11a) of the gate and by the protrusion (z) of the silicide part (11b) upwardly above the level of the body surface (10a).

Abstract: A power field effect transistor utilizes a retrograded-doped transition region to enhance forward on-state and reverse breakdown voltage characteristics. Highly doped shielding regions may also be provided that extend adjacent the transition region and contribute to depletion of the transition region during both forward on-state conduction and reverse blocking modes of operation. In a vertical embodiment, the transition region has a peak first conductivity type dopant concentration at a first depth relative to a surface on which gate electrodes are formed. A product of the peak dopant concentration and a width of the transition region at the first depth is preferably in a range between 1×1012 cm−2 and 7×1012 cm−2.

Abstract: A solid state image pickup device has a photo diodes for producing charge packets from image-carrying light, a vertical overflow drain formed under the photo diodes, charge transfer channel regions selectively connected to the photo diodes through transfer gate transistors, resistive gate electrodes capacitively coupled to said charge transfer channel regions, respectively, and a pulse signal source connected to far ends of the resistive gate electrodes and near ends of the resistive gate electrodes closer to a horizontal charge transfer unit, and the pulse signal source produces a potential gradient in the charge transfer channel regions after transfer of the charge packets to the charge transfer channel regions so that the charge packets are conveyed through the horizontal charge transfer unit without a large horizontal charge transfer signal.

Abstract: A MOS control diode is provided for power switching. In the MOS control diode, a switching speed is high and a reverse leakage current characteristic is improved without additionally needing processes for improving reverse recovery time by converting a power MOSFET which is a majority carrier device to diode having two terminals. Such a MOS control diode can be achieved by forming a discontinuous area in a gate oxide film formed on the surface of a semiconductor substrate so that the conductive gate electrode is connected to the semiconductor substrate. Also, it is possible to form a trench in the semiconductor substrate, to form the gate oxide films on the sidewall of a trench, and to connect the gate electrode to the semiconductor substrate through the bottom of the trench.

Abstract: A termination structure for power trench MOS devices is disclosed. The MOS devices can be Schottky diode, IGBT or DMOS depending on what kinds of the semiconductor substrate are prepared. The termination structure comprises: a semiconductor substrate having a trench formed therein; a spacer-like MOS gate formed on a sidewall of the trench; a termination structure oxide layer formed in the trench to cover a portion of the spacer-like MOS gate and to cover a bottom of the trench; and a first electrode and a second electrode are, respectively, formed on a bottom surface and upper surface of the semiconductor substrate. The trench is formed from a boundary of the active region to an edge of the semiconductor substrate. The trench MOS devices are formed in the active region. In addition for IGBT and DMOS, the second electrode is isolated from MOS gate by an oxide layer; however, for Schottky diode, the second electrode is directed contact to the MOS gate.

Abstract: A drain region is formed along a horizontal charge transfer channel constituting a horizontal charge transfer element, and a barrier region for charges is formed between the horizontal charge transfer channel and drain region. A two-electrode element is formed by using the horizontal charge transfer channel, barrier region and drain region. A solid state image pickup device can be manufactured with high productivity, which device can drain charges in the horizontal charge transfer element at high speed.

Abstract: A thin film transistor and a fabrication method thereof in which a desired device characteristic is achieved by adjusting the lengths of a channel region and an offset region. The transistor includes a substrate in which a trench is formed, a gate electrode formed in one side in the interior of the trench, a gate insulation film formed in the substrate including the gate electrode, an active layer formed on the gate insulation film, and impurity regions formed on the active layer corresponding to the substrate. The length of the channel and offset regions are adjusted by adjusting the length and width of the trench within the substrate.

Abstract: A solid-state image sensing device includes photoelectric conversion portions, vertical charge transfer portions, a horizontal charge transfer portion, an unwanted charge removing portion, and a potential barrier portion. The photoelectric conversion portions are arranged on an n-type semiconductor substrate. The vertical charge transfer portions are respectively arranged adjacent to the photoelectric conversion portions, and have a first p-type well layer and a first n-type semiconductor region. The horizontal charge transfer portion is arranged adjacent to one end side of the vertical charge transfer portions, and has a second p-type well layer and a second n-type semiconductor region. The unwanted charge removing portion is arranged adjacent to the horizontal charge transfer portion to remove an unwanted charge overflowing from the horizontal charge transfer portion. The unwanted charge removing portion has a third p-type well layer and a third n-type semiconductor region.

Abstract: A method for utilizing fractal analysis in the design and manufacture of semiconductor structures including transistor devices such as power MOS devices. The method includes using fractal theory to determine optimum source perimeter values to increase aspect ratio. The method is implemented to allow for use of the theoretical values in conjunction with known photolithographic fabrication techniques. The resultant structure thus incorporates the theoretically derived values to approximate a fractal structure.

Abstract: A semiconductor device includes at least one device active region formed in a first surface of a semiconductor substrate, an electrical contact layer on a second surface of the semiconductor substrate, and at least one resistivity-lowering body positioned in a corresponding recess in the substrate and connected to the electrical contact layer. The body preferably comprises a material having an electrical resistivity lower than an electrical resistivity of the semiconductor substrate to thereby lower an effective electrical resistivity of the substrate. The device active region may be an active region of a power control device, such as a MOSFET or IGBT, for example. The body may preferably comprise an electrical conductor such as copper, aluminum, silver, solder, or doped polysilicon. The at least one recess and associated resistivity-lowering body preferably defines a proportion of the semiconductor substrate area adjacent the device active region greater than about 0.

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: In a current detecting cell of a MOS-type semiconductor device with a current detection function, the area of the contact portions of source regions which contact a current detecting electrode is greater than that of that contact portion of a base region which contacts the current detecting electrode. With this feature, a parasitic resistance does no sharply decrease even if a detected voltage increases, and therefore, current can be detected accurately.

Abstract: A method for manufacturing a light receiving portion for a solid state image pickup device includes the steps of forming a well of a second impurity type on a substrate of a first impurity type, forming a channel stop within an upper surface of the well, forming a vertical CCD portion within the upper surface of the well, forming a gate insulating layer on the upper surface of the well, channel stop and the vertical CCD portion, forming a charge carrying gate electrode above the vertical CCD portion, forming a light receiving photo diode by ion-implanting impurities of the first impurity type, forming a first impurity layer on the light receiving photo diode by ion-implanting impurities of the second impurity type into a surface of the light receiving photo diode, removing a portion of the gate insulating layer above the light receiving photo diode, depositing an insulating layer containing impurities of the first impurity type on the gate insulating layer, the charge carrying gate electrode and the first imp

Abstract: A method for forming a trench transistor structure begins by forming a buried layers (12 and 16) and a doped well (22) in a substrate (10) via epitaxial growth processing. A trench region (24) is then etched into the substrate (10) to expose a the layer (12). A conductive sidewall spacer (28) is formed within the trench (24) as a gate electrode. The spacer (28) gates a first transistor (12, 28, 32) located adjacent a first half of the trench (24) and a second transistor (12, 28, 34) located adjacent a second half of the trench (24). Region (12) is a common electrode wherein the channel regions of both the first and second transistor are coupled in a serial manner through the region (12).

Abstract: The lateral overflow drain for charge coupled devices includes: a semiconductor region 70 of a first conductivity type having a trench 92; a drain region 24 of a second conductivity type below the trench 92; a gate 20 in the trench 92 overlying and separated from a portion of the semiconductor region 70; and a virtual gate 30 of the first conductivity type in the semiconductor region 70 adjacent the trench 92.

Abstract: A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P.sup.+ semiconductor layers (45) having a higher impurity concentration than that N.sup.+ emitter layers (44) are disposed so that the P.sup.+ semiconductor layers (45) overlap adjacent edges of the N.sup.+ emitter layers (44) of a U-type IGBT and so that bottom portions of the P.sup.+ semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P.sup.+ semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N.sup.+ emitter region (4), a P base layer (3) and an N.sup.- layer (2) does not easily turn on.

Abstract: The present invention teaches how to maintain temporally the increased collection region (depletion depth) of detectors within a solid-state image sensor. A novel clocking method is used to control charge transfer within charge coupled devices to reduce cross talk with a resulting improvement in the MTF and quantum efficiency. Specifically, the present invention employs a pulsing type of clocking technique wherein the duty cycle is adjusted to maximize the depletion region. These pulses are spaced equally from phase to phase within the multiphase clocking scheme. The present invention is specifically designed for high speed CCD devices in which improvements in the MTF and QE are desired. Time Delay Integration (TDI) image sensors are such devices that have high speed characteristics as a common requirement and the application of the present invention to these devices is discussed.

Abstract: A number of electrode sets each respectively consisting of a number of gate electrodes disposed at each of matrix-addressed charge-coupled device ("CCD") registers are separately arranged in a column direction of the registers, the gate electrodes in each of the electrode sets being separately arranged in a different direction from the column direction, and a combination of interconnections is provided among conductors for selectively applying a number of pulse voltages different in phase to the gate electrodes in each of the electrode sets. The pulse voltages are applied with a combination of different phases to the gate electrodes in each of the electrode sets, and the combination of the different phases are changed, thereby controlling the position of a sensitivity barycenter of each of the electrode sets to raise the resolution of an image sensor.

Abstract: In a CCD solid state image sensing device in which a photosensitive section is constructed by a photodiode formed by a PN junction between a first P-type well region and an N-type impurity diffusion region formed on an N-type silicon substrate, the N-type impurity diffusion region is formed by the ion implantation of single substance of arsenic (As). According to this CCD solid state image sensing device, a bright flaw on an image sensing screen, which is one of the defects encountered with an image sensing screen, can be reduced. Also, the n-type impurity diffusion region constructing the PN Junction can be reduced in size and the CCD solid state image sensing device itself can be made compact in size. Further, a method of manufacturing a CCD solid state image sensing device also is provided.

Abstract: A multiple output, vertical MOSFET device (11) with improved electrical performance and thermal dissipation is integrated with an additional semiconductor device or semiconductor circuit (18) on a single semiconductor substrate (34). The method of making the vertical MOSFET device (11) involves thinning the semiconductor substrate (34) after fabricating the vertical MOSFET device (11) and the semiconductor circuit (18) to reduce the vertical component of electrical and thermal resistance and to increase the thermal dissipation efficiency. Electrical performance is improved by thinning the semiconductor substrate (34) and by providing a low resistivity, patterned metal buried layer. Thermal management is enhanced by using flip chip bumps (24) to dissipate heat from a top surface (31) of the semiconductor substrate (34) and by using the patterned buried metal layer (26) to dissipate heat from a bottom surface (32) of the semiconductor substrate (34).

Abstract: A solid-state CCD image pick-up device includes optoelectric transducing elements corresponding to pixels vertically and horizontally arrayed in a matrix forming column linear arrays defining a column direction and at least one vertical charge transfer path associated with a corresponding adjacent column linear array. Pixel signals are vertically transferred from the column linear arrays to the vertical charge transfer paths such that gate signals occurring at predetermined times are applied to gate electrodes of the vertical charge transfer paths to permit the pixel signals to be scan read by a horizontal charge transfer path. Switching elements are provided for transfer gate electrodes and a drive circuit sequentially generates drive signals for groups of gate electrodes during periods in which the switching elements are rendered conductive to allow a full frame scan read to be performed by supplying a predetermined number of timing signals to the gate electrodes.

Abstract: In a CCD device, on a semiconductor substrate, and in the insulation films, plural first semiconductor regions and plural second semiconductor regions are formed buried in the insulation films, intermediating a tunneling insulation film therebetween in a manner to spatially isolate them from each other.

Abstract: An infrared or x-ray imaging CCD array, including deep trench isolation (56) for capturing electron carriers formed deep in the substrate (46) as a result of long wavelength radiation or high energy particles. In virtual phase CCD circuits, the trench has formed on the sidewalls thereof a diffusion (58, 60) defining a vertical conductor for allowing hole carrier conduction between the substrate (46) and the virtual phase electrode (38).

Abstract: An output circuit for sequentially receiving and converting charge collected in the photoelements of an image sensor and converting such charge into an output voltage. The output circuit includes a buried-channel LDD transistor having gate, source and drain electrodes. The source electrode provides a floating diffusion. When the transistor is turned off, a potential well is provided in the floating diffusion which collects charge. An output source-follower amplifier also employing buried-channel LDD transistors is connected to the floating diffusion and produces the output voltage.

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: In CCD arrangements, such as bidimensional image sensors, it is usual to provide the output register in the form of two (or more) horizontal registers. Via transverse connections between the horizontal registers, charge packets are transported from one horizontal register to the other horizontal register. In order to avoid delays during this transverse transport due to narrow channel effects, the clock electrodes of the first horizontal register adjoining the transverse connections are widened at the expense of adjacent clock electrodes. These widened electrodes may be in the trapezoidal form, as a result of which additional drift fields are induced below these electrodes.