Junction Gate Region Free Of Direct Electrical Connection (e.g., Floating Junction Gate Memory Cell Structure) Patents (Class 257/261)
  • Patent number: 10276097
    Abstract: The present disclosure relates to the OLED display technology. There are provided a pixel circuit, a driving circuit, an array substrate and a display device, which are supplied with the voltage by the light emitting operation voltage when the pixel circuit enters the light emitting stage, by inputting an inverse signal synchronized with the pre-charging control voltage at the input terminal of the light emitting operation voltage to ensure a stable output of the current by the circuit at the light emitting stage. Also, it does not require an arrangement of an external voltage input terminal which will affect the aperture ratio, thereby increasing the aperture ratio of the OLED employing the current-driven pixel circuit while ensuring the stable output of the current by the current-driven circuit, and thus increasing the lifetime of the OLED employing the current-driven pixel circuit.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: April 30, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Liye Duan, Lirong Wang, Zhongyuan Wu
  • Patent number: 10236283
    Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 19, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10230047
    Abstract: An RRAM device is provided, which includes a bottom electrode in an oxide layer, a plurality of dielectric protrusions on the oxide layer, wherein the bottom electrode is disposed between the two adjacent dielectric protrusions. A resistive switching layer is conformally disposed on the dielectric protrusions, the oxide layer, and the bottom electrode. A conductive oxygen reservoir layer is disposed on the resistive switching layer, and an oxygen diffusion barrier layer is disposed on the conductive oxygen reservoir layer.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: March 12, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventor: Frederick Chen
  • Patent number: 10083745
    Abstract: Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 25, 2018
    Assignee: MICRON TECHNOLOGY, INC
    Inventors: Jeremy Miles Hirst, Hernan A. Castro, Stephen Tang
  • Patent number: 10083969
    Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Yan Chen, Jui-Yao Lai, Sai-Hooi Yeong, Yen-Ming Chen
  • Patent number: 10056493
    Abstract: A semiconductor device is provided in the present invention, which includes a substrate, an oxide-semiconductor layer, source/drain regions, a first dielectric layer covering on the oxide-semiconductor layer and the source/drain regions, a second gate between the two source/drain regions and partially covering the oxide-semiconductor layer, and a charge storage structure between the first gate electrode and the oxide-semiconductor layer.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: August 21, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Chen-Bin Lin, Sanpo Wang, Chung-Yuan Lee, Chi-Fa Ku
  • Patent number: 9812327
    Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: November 7, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Huang Yu, Shih-Yin Hsiao
  • Patent number: 9685114
    Abstract: A system for controlling a display in which each pixel circuit comprises a light-emitting device, a drive transistor, a storage capacitor, a reference voltage source, and a programming voltage source. The storage capacitor stores a voltage equal to the difference between the reference voltage and the programming voltage, and a controller supplies a programming voltage that is a calibrated voltage for a known target current, reads the actual current passing through the drive transistor to a monitor line, turns off the light emitting device while modifying the calibrated voltage to make the current supplied through the drive transistor substantially the same as the target current, modifies the calibrated voltage to make the current supplied through the drive transistor substantially the same as the target current, and determines a current corresponding to the modified calibrated voltage based on predetermined current-voltage characteristics of the drive transistor.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 20, 2017
    Assignee: Ignis Innovation Inc.
    Inventor: Gholamreza Chaji
  • Patent number: 9415442
    Abstract: The present invention discloses stable, non-agglomerated, ultra-small metal/alloy clusters encapsulated in silica with the metal/alloy cluster size of less than 5 nm. The invention further discloses a simple, cost effective process for the preparation of metal/alloy clusters encapsulated in silica which is thermally stable and without agglomeration.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: August 16, 2016
    Assignee: COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH
    Inventors: Nandini R. Devi, Anupam Samanta
  • Patent number: 9331197
    Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 3, 2016
    Assignee: Cree, Inc.
    Inventors: Vipindas Pala, Anant Kumar Agarwal, Lin Cheng, Daniel Jenner Lichtenwalner, John Williams Palmour
  • Patent number: 9041092
    Abstract: A semiconductor device includes a pillar-shaped silicon layer including a first diffusion layer, a channel region, and a second diffusion layer formed in that order from the silicon substrate side, floating gates respectively disposed in two symmetrical directions so as to sandwich the pillar-shaped silicon layer, and a control gate line disposed in two symmetrical directions other than the two directions so as to sandwich the pillar-shaped silicon layer. A tunnel insulating film is formed between the pillar-shaped silicon layer and each of the floating gates. The control gate line is disposed so as to surround the floating gates and the pillar-shaped silicon layer with an inter-polysilicon insulating film interposed therebetween.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 26, 2015
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9035311
    Abstract: An organic light emitting diode (OLED) display device and a method of fabricating the same are provided. The OLED display device includes a substrate having a thin film transistor region and a capacitor region, a buffer layer disposed on the substrate, a gate insulating layer disposed on the substrate, a lower capacitor electrode disposed on the gate insulating layer in the capacitor region, an interlayer insulating layer disposed on the substrate, and an upper capacitor electrode disposed on the interlayer insulating layer and facing the lower capacitor electrode, wherein regions of each of the buffer layer, the gate insulating layer, the interlayer insulating layer, the lower capacitor electrode, and the upper capacitor electrode have surfaces in which protrusions having the same shape as grain boundaries of the semiconductor layer are formed. The resultant capacitor has an increased surface area, and therefore, an increased capacitance.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 19, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Tae-Hoon Yang, Jin-Wook Seo, Soo-Beom Jo, Dong-Hyun Lee, Kil-Won Lee, Maxim Lisachenko, Yun-Mo Chung, Bo-Kyung Choi, Jong-Ryuk Park, Ki-Yong Lee
  • Patent number: 9012973
    Abstract: According to one embodiment, a semiconductor memory device includes an insulating film with a recess formed in an upper surface, and a conductive film provided on the insulating film and containing silicon, carbon and an impurity serving as an acceptor or donor for silicon. Carbon concentration of a first portion of the conductive film in contact with the insulating film is lower than carbon concentration of a second portion of the conductive film located in the recess and being equidistant from the insulating film placed on both sides thereof.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuo Ohashi, Fumiki Aiso
  • Patent number: 8969947
    Abstract: A memory device includes a substrate, a semiconductor column extending perpendicularly from the substrate and a plurality of spaced-apart charge storage cells disposed along a sidewall of the semiconductor column. Each of the storage cells includes a tunneling insulating layer disposed on the sidewall of the semiconductor column, a polymer layer disposed on the tunneling insulating layer, a plurality of quantum dots disposed on or in the polymer layer and a blocking insulating layer disposed on the polymer layer.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-goo Lee, Jung-dal Choi, Young-woo Park
  • Patent number: 8872239
    Abstract: An image pickup device according to the present invention is an image pickup device in which a plurality of pixel are arranged in a semiconductor substrate. Each of the plurality of pixels includes a photoelectric conversion element, a floating diffusion (FD) region, a transfer gate that transfers charges in the first semiconductor region to the FD region, and an amplification transistor whose gate is electrically connected to the FD region. The photoelectric conversion element has an outer edge which has a recessed portion in plan view, a source region and a drain region of the amplification transistor are located in the recessed portion, and the FD region is surrounded by the photoelectric conversion region or is located in the recessed portion in plan view.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuaki Tashiro, Shin Kikuchi
  • Patent number: 8872247
    Abstract: Memory arrays having folded architectures and methods of making the same. Specifically, memory arrays having a portion of the transistors in a row that are reciprocated and shifted with respect to other transistors in the same row. Trenches formed between the rows may form a weave pattern throughout the array, in a direction of the row. Trenches formed between legs of the transistors may also form a weave pattern throughout the array in a direction of the row.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shigeki Tomishima
  • Patent number: 8803243
    Abstract: A complementary metal oxide semiconductor (CMOS) device including a substrate including a first active region and a second active region, wherein each of the first active region and second active region of the substrate are separated by from one another by an isolation region. A n-type semiconductor device is present on the first active region of the substrate, in which the n-type semiconductor device includes a first portion of a gate structure. A p-type semiconductor device is present on the second active region of the substrate, in which the p-type semiconductor device includes a second portion of the gate structure. A connecting gate portion provides electrical connectivity between the first portion of the gate structure and the second portion of the gate structure. Electrical contact to the connecting gate portion is over the isolation region, and is not over the first active region and/or the second active region.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon, Shreesh Narasimha, Xiaojun Yu
  • Patent number: 8785987
    Abstract: An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 22, 2014
    Assignee: Acco
    Inventor: Denis Masliah
  • Patent number: 8772852
    Abstract: Provided is a nonvolatile memory device including a common source. The device includes a first active region crossing a second active region, a common source disposed in the second active region, and a source conductive line disposed on the common source in parallel to the common source. The source conductive line is electrically connected to the common source.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 8, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Soo Kim, Keon-Soo Kim
  • Patent number: 8772841
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 8723249
    Abstract: A non-volatile memory includes a substrate, a gate dielectric layer, a gate conductive layer, a nitride layer, a spacer, a first oxide layer, and a second oxide layer. The gate conductive layer, substrate and gate dielectric layer cooperatively constitute a symmetrical opening thereamong. The nitride layer has an L-shape and formed with a vertical part extending along a sidewall of the gate conductive layer and a horizontal part extending into the opening, wherein the vertical part and the horizontal part are formed as an integral structure and a height of the vertical part is below a top surface of the gate conductive layer. The spacer is disposed on the substrate and the nitride layer. The first oxide layer is disposed among the gate conductive layer, the nitride layer and the gate dielectric layer. The second oxide layer is disposed among the gate dielectric layer, the nitride layer and the substrate.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: May 13, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Hung Chen, Tzu-Ping Chen, Yu-Jen Chang
  • Patent number: 8692300
    Abstract: An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: April 8, 2014
    Inventors: Ming-Kun Yang, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 8675386
    Abstract: A memory device includes a memory unit including a plurality of first conductive lines and a plurality of second conductive lines that cross the first conductive lines, and a driving unit module coupled with the plurality of the first conductive lines through respective ones of a plurality of contacts and coupled with and the plurality of the second conductive lines through respective ones of the plurality of contacts, wherein as the first conductive lines become farther from the driving unit module along a direction that the second conductive lines extend, the respective contacts of the first conductive lines have lower resistance values.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seok-Pyo Song
  • Patent number: 8587036
    Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 19, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Shih-Chen Wang, Wen-Hao Ching
  • Patent number: 8581298
    Abstract: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8569172
    Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: October 29, 2013
    Assignee: Crossbar, Inc.
    Inventors: Sung Hyun Jo, Kuk-Hwan Kim, Tanmay Kumar
  • Patent number: 8536637
    Abstract: A method for manufacturing Flash memory devices includes forming a well region in a substrate, depositing a gate dielectric layer overlying the well region, and depositing a first polysilicon layer overlying the gate dielectric layer. The method also includes depositing a dielectric layer overlying the first polysilicon layer and depositing a second polysilicon layer overlying the dielectric layer to form a stack layer. The method simultaneously patterns the stack layer to form a first flash memory cell, which includes a first portion of the second polysilicon layer overlying a first portion of the dielectric layer overlying a first portion of first polysilicon layer and to form a select device, which includes a second portion of second polysilicon layer overlying a second portion of dielectric layer overlying a second portion of first polysilicon layer. The method further includes forming source/drain regions using ion implant.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: September 17, 2013
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Daniel Xu, Roger Lee
  • Patent number: 8519451
    Abstract: According to one embodiment, a semiconductor device includes a source region having p-type conductivity, a drain region having p-type conductivity, a channel region provided between the source region and the drain region and having n-type conductivity, a lower gate insulating film provided on the channel region, a lower gate electrode provided on the lower gate insulating film, an upper gate insulating film provided on the lower gate electrode, an upper gate electrode provided on the upper gate insulating film, and a switching element connected between the lower gate electrode and the source region.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 27, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Osamu Takata
  • Patent number: 8513712
    Abstract: The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: August 20, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Liang Chu, Fei-Yuh Chen, Chih-Wen Yao
  • Patent number: 8314756
    Abstract: This invention relates to pixel driver circuits for active matrix optoelectronic devices, in particular OLED (organic light emitting diodes) displays. We describe an active matrix optoelectronic device having a plurality of active matrix pixels each said pixel including a pixel circuit comprising a thin film transistor (TFT) for driving the pixel and a pixel capacitor for storing a pixel value, wherein said TFT comprises a TFT with a floating gate.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: November 20, 2012
    Assignee: Cambridge Display Technology Limited
    Inventors: Aleksandra Rankov, Euan C. Smith
  • Patent number: 8298890
    Abstract: A semiconductor memory element is described, including a substrate including a source region, a drain region, and a channel region, a tunnel oxide over the channel region of the substrate, a charge storage layer over the tunnel oxide, a charge blocking layer over the charge storage layer, and a control gate over the charge blocking layer. The charge blocking layer further includes a first layer including a transition metal oxide, a second layer including a metal silicate, a third layer including the transition metal oxide of the first layer.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: October 30, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Ronald John Kuse, Monica Sawkar Mathur, Wen Wu
  • Patent number: 8288800
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
    Type: Grant
    Filed: January 4, 2010
    Date of Patent: October 16, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ming Zhu, Chun Shan Yin, Elgin Quek, Shyue Seng Tan
  • Patent number: 8242553
    Abstract: A thin film transistor (TFT) substrate includes first and second TFTs on the same substrate. The first TFT has a feature that a lower conductive layer or a bottom gate electrode layer is provided between the substrate and a first insulating layer while an upper conductive layer or a top gate electrode layer is disposed on a second insulating layer formed on a semiconductor layer which is formed on the first insulating layer. The first conductive layer has first and second areas such that the first area overlaps with the first conductive layer without overlapping with the semiconductor layer while the second area overlaps with the semiconductor layer, and the first area is larger than the second area while the second insulating layer is thinner than the first insulating layer. The second TFT has the same configuration as the first TFT except that the gate electrode layer is eliminated.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: August 14, 2012
    Assignee: NLT Technologies, Ltd.
    Inventors: Takahiro Korenari, Hiroshi Tanabe
  • Patent number: 8168469
    Abstract: A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: May 1, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hyun Lee, Sung-kyu Choi, Kyu-sik Kim
  • Patent number: 8159013
    Abstract: There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: April 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Hidetoshi Nishimura, Hiroyuki Shimbo, Tetsurou Toubou, Hiroki Taniguchi, Hisako Yoneda
  • Patent number: 8115243
    Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8093631
    Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a gate structure on a substrate, the gate structure including a first insulation layer, a first electrode layer for a floating gate and a second insulation layer; forming a third insulation layer on the gate structure covering predetermined regions of the substrate adjacent to the gate structure; and forming a second electrode layer for a control gate on the third insulation layer disposed on sidewalls of the gate structure and the predetermined regions of the substrate.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: January 10, 2012
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Yong-Sik Jeong
  • Patent number: 8089801
    Abstract: The present invention discloses a semiconductor memory device comprising a source, a drain, a floating gate, a control gate, a recess channel and a gated p-n diode. The said p-n diode connects said floating gate and said drain. The said floating gate is for charge storage purpose, it can be electrically charged or discharged by current flowing through the gated p-n diode. An array of memory cells formed by the disclosed semiconductor memory device is proposed. Furthermore, an operating method and a method for producing the disclosed semiconductor memory device and array are described.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: January 3, 2012
    Assignee: Suzhou Oriental Semiconductor Co., Ltd.
    Inventors: Peng-Fei Wang, Yi Gong
  • Patent number: 8058118
    Abstract: Methods of forming and operating a back-side trap non-volatile memory cell. Method of forming a back-side trap non-volatile memory cell include forming a trapping material, forming two or more sub-layers of dielectric material on the trapping material, wherein a conduction band offset of each sub-layer of dielectric material is less than the conduction band offset of the material upon which it is formed, and forming a channel region on the two or more sub-layers of dielectric material. Methods of operating a back-side trap non-volatile memory cell include programming the memory cell via direct tunneling of carriers through an asymmetric band-gap tunnel insulator layer having two or more sub-layers formed beneath a channel region and having layers of material of increasing conduction band offset, and trapping the carriers in a trapping layer formed under the tunnel insulator layer.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 15, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 8035150
    Abstract: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: October 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiromasa Fujimoto
  • Patent number: 8035154
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of memory cells, a plurality of bit lines, and a plurality of source lines. The memory cells are located in the semiconductor substrate. Each of the memory cells includes a trench provided in the semiconductor substrate, an oxide layer disposed on a sidewall of the trench, a tunnel oxide layer disposed at a bottom portion of the trench, a floating gate disposed in the trench so as to be surrounded by the oxide layer and the tunnel oxide layer, and an erasing electrode disposed on an opposing side of the tunnel oxide layer from the floating gate. The bit lines and the source lines are alternately arranged on the memory cells in parallel with each other.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: October 11, 2011
    Assignee: DENSO CORPORATION
    Inventors: Takayoshi Naruse, Mitsutaka Katada, Tetsuo Fujii
  • Patent number: 8022489
    Abstract: An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.
    Type: Grant
    Filed: May 20, 2005
    Date of Patent: September 20, 2011
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Erh-Kun Lai, Kuang Yeu Hsieh
  • Patent number: 8022443
    Abstract: An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: September 20, 2011
    Assignee: Marvell International Ltd.
    Inventors: Qiang Tang, Min She, Ken Liao
  • Patent number: 8008731
    Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: August 30, 2011
    Assignee: Acco
    Inventor: Denis Masliah
  • Patent number: 7982249
    Abstract: A magnetic tunnel junction transistor. In a particular embodiment, the magnetic tunnel junction transistor includes a tunnel barrier having a high resistance when in a non-ferromagnetic, state and a low resistance when in a ferromagnetic state. The tunnel barrier is switchable between the non-ferromagnetic and the ferromagnetic states.
    Type: Grant
    Filed: June 26, 2010
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventor: Daniel C. Worledge
  • Patent number: 7968927
    Abstract: A memory array having a plurality of resistance variable memory units and method for forming the same are provided. Each memory unit includes a first electrode, a resistance variable material over the first electrode, and a first second-electrode over the resistance variable material. The first second-electrode is associated with the first electrode to define a first memory element. Each memory unit further includes a second second-electrode over the resistance variable material. The second-second electrode is associated with the first electrode to define a second memory element.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Jon Daley
  • Publication number: 20110147806
    Abstract: Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
    Type: Application
    Filed: February 28, 2011
    Publication date: June 23, 2011
    Applicant: AMERICAN SEMICONDUCTOR, INC.
    Inventors: Dale G. Wilson, Douglas R. Hackler, SR.
  • Patent number: 7956403
    Abstract: A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: June 7, 2011
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Wei-Ming Liao, Jer-Chyi Wang, Yi-Feng Chang
  • Patent number: 7919772
    Abstract: A nonvolatile memory has a problem in that applied voltage is high. This is because a carrier needs to be injected into a floating gate through an insulating film by a tunneling effect. In addition, there is concern about deterioration of the insulating film by performing such carrier injection. An object of the present invention is to provide a memory in which applied voltage is lowered and deterioration of an insulating film is prevented. One feature is to use a layer in which an inorganic compound having a charge-transfer complex is mixed with an organic compound as a layer functioning as a floating gate of a memory. A specific example is an element having a transistor structure where a layer in which an inorganic compound having a charge-transfer complex is mixed with an organic compound and which is sandwiched between insulating layers is used as a floating gate.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: April 5, 2011
    Assignee: Semiconductor Energy laboratory Co., Ltd.
    Inventors: Shinobu Furukawa, Ryota Imahayashi
  • Patent number: 7851827
    Abstract: Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: December 14, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya