Abstract: A semiconductor device, by which a base in which gates are buried can be formed by the junction of semiconductor substrates to each other at a lower temperature, and a fabrication process thereof are provided. Recesses are defined in the top of an N.sup.- substrate. A P.sup.+ layer is formed on the underside of the N.sup.- substrate. P.sup.+ -Gate regions are each formed in an area ranging from the bottom to lower side portions of the recesses. A metal layer composed of an Au-Sb alloy is formed on the underside of the N.sup.+ substrate. The N.sup.- substrate and the N.sup.+ substrate are subjected to a treatment for removing impurities thereon with an aqueous solution of sulfuric acid and hydrogen peroxide, washed with purified water and dried by a spin dryer. The N.sup.- substrate and the N.sup.+ substrate are heated at about 350.degree. C.

Abstract: A field effect transistor has the property that the product of its series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of the transistor, the series resistance being the sum of the resistance from source to channel and the resistance of this channel. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in response to a small increase in the reverse gate voltage applied. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Abstract: A field effect transistor has the property that the product of its active total series resistance and its true transconductance is less than one throughout the entire range of drain voltage in the operative state of this transistor, the active total series resistance being the sum of the active resistance from source to channel, the active resistance of this channel and the active resistance from channel to drain. In order to prevent an excessive increase in the active resistance of the channel, the channel is made to have an impurity concentration as low as less than 10.sup.15 atoms/cm.sup.3, preferably less than 10.sup.14 atoms/cm.sup.3, so that the depletion layers extending from the gates grow extensively to become contiguous in such fashion in response to a small increase in the reverse gate voltage applied, that no narrow lengthy path is formed between the depletion layers. As a result, the field effect transistor of this invention has an unsaturated drain current versus drain voltage characteristic.

Abstract: The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main electrode forms an ohmic contact with the higher impurity density region and also forms a Schottky contact with a Static Induction Schottky shorted region of the lower impurity density region surrounded by tile higher impurity density region, and it is excellent in turn-off performance and easy to use, by substantially reducing tile minority carrier storage time, the fall time and the quantity of gate pull-out charges in order that charges may easily be pulled out from the cathode or source electrode as well as from the gate electrode at turn-off.

Abstract: An electronic component especially a p-channel or n-channel permeable base transistor (PBT) is provided as a plurality of layers, fabricated in a laminated composite, and with at least one laterally structured layer provided for controlling a space charge zone, especially a base of the electronic component.

Abstract: Operating characteristics of an electronics device in which alternating currents flow are improved by reducing positive electromagnetic coupling between currents. This is accomplished by altering the direction of a current flow to obtain negative coupling through current flow in the same direction, or by minimizing electromagnetic coupling through perpendicular current flow, or by increasing the spacing between two electromagnetically coupled currents. In a bipolar transistor structure a feed structure for emitter and base current includes wire bonding pads aligned so that emitter current and base current flow to wire bonding pads perpendicular to the direction of collector current flow and with adjacent emitter currents and base currents flowing in the same direction. Each feed structure includes a plurality of interdigitated fingers for contacting emitter and base regions, all emitter and base currents in said interdigitated fingers of all feed structures flowing in the same direction as the collector.

Abstract: A double diamond mesa vertical field effect transistor includes a diamond layer, a first diamond mesa on a diamond layer, and a second diamond mesa on the first diamond mesa, opposite the diamond layer. A source contact is formed on the second diamond mesa, opposite the first diamond mesa, and a gate is formed on the first diamond mesa opposite the diamond layer. The drain contact may be formed on the diamond layer adjacent the first diamond mesa, or the diamond layer itself may be formed on a nondiamond substrate and a drain contact may be provided on the nondiamond substrate. An integrated array of field effect transistors may be formed, including a plurality of second mesas on the first mesa, with a plurality of gates formed on the first mesa between the second mesas and a source formed on each second mesa, opposite the first mesa. The second mesas may also extend over the multiple gate contacts on the first mesa to form a common source region with a common source contact.

Abstract: A semiconductor device allowing control of its threshold voltage without requiring change in the materials of its gate electrodes and suitable for high density integration is disclosed. The semiconductor device includes a p type monocrystalline silicon substrate 1 having a cylindrical portion with inner and outer surfaces and extending in a vertical direction. A first gate electrode 8 and a second gate electrode 10 are disposed at the inner surface and the outer surface of the cylindrical portion 2, respectively. A source/drain region 5 is formed on the top end of the cylindrical portion 2, while a source/drain region 3 is formed on the inner bottom surface of the cylindrical portion 2. Therefore, the cylindrical portion 2 can be utilized as a channel region of an MIS field effect transistor. The threshold voltage of the transistor can easily be controlled by applying separate voltages to the two gate electrodes, the first electrode and the second electrode.

Abstract: A method for producing a vacuum microelectronics device ( 10 ) on a substrate ( 12 ) and insulating dielectric (14) first forms an electrode base (16) on the insulating dielectric (14). Next, electrode base (16) is covered with a first organic spacer (42) having an aperture (44) for exposing a portion of electrode base (16). Next, a metal layer (46) is applied over organic spacer (42) to form emitter (18) within aperture (44). After removal of organic spacer (42) and metal layer (46), a second organic spacer (44) and a grid material (20) are applied over emitter (18) and electrode base (16). Next, a third organic spacer (50) and an anode metal (22) with access apertures ( 34 ) and ( 36 ) are placed over the structure. After removing organic spacers (48) and (50), anode metal (22) is sealed with metal (26) to close off access apertures ( 34 ) and ( 36 ). The result is a vacuum microelectronics device (10) usable is a triode or diode.

Abstract: The feeds to the emitter, base, and collector of an RF power transistor (source, drain, gate feeds of an RF FET) are configured so that negative mutual coupling therebetween is enhanced and positive mutual coupling therebetween is reduced. The emitter and base feeds include elongated portions which are generally parallel to each other with bonding pads provided on the elongated portions so that emitter and base currents flow in the same direction in the elongated portions and in the same direction as collector currents below. Interdigitated contact fingers extend from the elongated portions and contact the emitter region and the base region, respectively. When positive coupling of collector current and emitter current to the controlling base current is reduced or eliminated, the major thermal imbalance problem of operating RF transistors is also reduced or eliminated. Performance, linearity, efficiency, gain, and ruggedness are all enhanced in devices designed to utilize this invention.

Abstract: A vertical diamond field effect transistor includes a nondiamond substrate, preferably a heavily doped silicon substrate, having a diamond layer on one face thereof, a source contact on the diamond layer, a gate contact on the diamond layer adjacent the source contact, and a drain contact on the back face of the substrate. The diamond layer is preferably a single layer of large polycrystalline diamond grains, having a heavily doped region adjacent the silicon substrate. The gate and source contacts may extend across many polycrystalline diamond grains in the single layer of polycrystalline diamond grains. Alternatively, the source and gate contacts may be narrower than the average grain size of the polycrystalline diamond grains. Interdigitated source and gate fingers, narrower than the average polycrystalline diamond grain size, may also be provided. The single layer of polycrystalline grains may be formed on the silicon substrate.

Abstract: A dynamic random access memory includes a memory cell including a junction field effect transistor and a capacitor. A first conductivity-type semiconductor layer is formed on a main surface of a semiconductor substrate. The semiconductor layer includes a columnar part extending from the main surface of the semiconductor substrate and having a top surface and a sidewall surface. The junction field effect transistor is formed in the columnar part, and the capacitor is formed on the top surface of the columnar part. The junction field effect transistor includes a second conductivity-type impurity region and a gate electrode. The second conductivity-type impurity region is formed on the sidewall surface of the columnar part. The gate electrode is formed to surround the sidewall surface of the columnar part to be electrically in contact with the second conductivity-type impurity, region. The capacitor includes a storage node, a dielectric film, and a cell plate electrode.

Abstract: A semiconductor power device wherein the reverse voltage across the p.sup.+ -regions(s) and the n.sup.+ -regions(s) is sustained by a composite buffer layer, shortly as CB-layer. The CB-layer contains two kinds of semiconductor regions with opposite types of conduction. These two kinds of regions are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n.sup.+ (or p.sup.+)-region. Whereas the hitherto-used voltage sustaining layer contains only one kind of semiconductor with single type of conduction in the same sectional view. Design guidelines are also provided in this invention. The relation between the on-resistance in unit area Ron and the breakdown voltage V.sub.B of the CB-layer invented is Ron ocV.sub.B.sup.113 which represents a breakthrough to the conventional voltage sustaining layer, whereas the other performances of the power devices remain almost unchanged.

Abstract: A semiconductor device comprises a substrate having a stepped upper major surface, an emitter layer of a semiconductor material provided on the stepped upper major surface of the substrate and having a corresponding stepped upper major surface, a base layer provided on stepped upper major surface of the emitter layer and comprising a plurality of channels of carriers and a plurality of control regions for controlling the passage of carriers through the control regions, and a collector layer of a semiconductor material provided on the base layer for collecting the carriers that have passed through the channels. Each channel extends from the emitter layer to the collector layer, and at least one channel and one control region are provided adjacent with each other in correspondence to each step of the upper major surface of the emitter layer.

Abstract: A static induction transistor has a gate region formed with a protrusion extending toward a drain region. The protrusion is located toward one side of the gate region such that a shallower gate region lies between the protrusion and the nearest source region. When a reverse voltage higher than the withstand voltage is applied between the gate and drain, avalanche breakdown occurs only in a region immediately below the protrusion, and no hot carriers are allowed to flow into a source region. Deterioration of the voltage-withstanding property and destruction of the device is thereby prevented. Another embodiment has a semiconductor region of a first conductivity type formed in a peripheral portion of a semiconductor layer of the first conductivity type in which a plurality of gate regions are disposed and adjacent a first major surface thereof.