Vertical Controlled Current Path Patents (Class 257/263)
  • Patent number: 10867995
    Abstract: A device integrated with a depletion-mode junction field-effect transistor and a method for manufacturing the device. The device includes: a well region, which is of a second conduction type and formed within a first conduction region (214); a JFET source (210), which is of a first conduction type and formed within the well region; a metal electrode (212) of the JFET sources formed on the JFET sources (210), which is in contact with the JFET sources (210); a lateral channel region (208), which is of the first conduction type and formed between two adjacent JFET sources (210), while two ends thereof are in contact with the two adjacent JFET sources (210); and a JFET metal gate (213) formed on the well region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: December 15, 2020
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Yan Gu, Shikang Cheng, Sen Zhang
  • Patent number: 10833175
    Abstract: A semiconductor device that includes a fin structure having a porous core, and a relaxed semiconductor layer present on the porous core. The semiconductor device may further include a strained semiconductor layer that is substantially free of defects that is present on the strained semiconductor layer. A gate structure may be present on a channel region of the fin structure, and source and drain regions may be present on opposing sides of the gate structure.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kangguo Cheng, Jeehwan Kim, Alexander Reznicek, Devendra K. Sadana
  • Patent number: 10825733
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 3, 2020
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 10770541
    Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans Weber
  • Patent number: 10002964
    Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 19, 2018
    Assignee: Northwestern University
    Inventors: Joseph S. Friedman, Alan V. Sahakian, Andrey Godkin, Alex Henning, Yossi Rosenwaks
  • Patent number: 9991170
    Abstract: One embodiment provides a method of integrating a planar field-effect transistor (FET) with a vertical FET. The method comprises masking and etching a semiconductor of the vertical FET to form a fin, and providing additional masking, additional etching, doping and depositions to isolate a bottom source/drain (S/D) region. A dielectric is formed on the bottom S/D region to form a spacer. The method further comprises depositing gate metals, etching a vertical gate for the vertical FET and a planar gate for the planar FET using a shared gate mask, depositing dielectric, etching the dielectric to expose one or more portions of the fin, growing epitaxy on a top S/D region, masking and etching S/D contact openings for the bottom S/D region, forming silicide regions in S/D regions, depositing contact metal in the silicide regions to form contacts, and planarizing the contacts.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 9960159
    Abstract: A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor having a first drain formed over a first channel layer that overlays a substrate, and a second transistor that includes a second drain formed over a second channel layer that overlays the substrate. The substrate forms a common source for both the first transistor and the second transistor.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: May 1, 2018
    Assignee: Northrop Grumman Systems Corporation
    Inventor: John V. Veliadis
  • Patent number: 9954069
    Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Li-Ting Wang, Chien-Hsun Wang, Huan-Just Lin, Yung-Cheng Lu, Tze-Liang Lee
  • Patent number: 9887287
    Abstract: Semiconductor devices include a semiconductor layer structure having a wide band-gap semiconductor drift region having a first conductivity type. A gate trench is provided in an upper portion of the semiconductor layer structure, the gate trench having first and second opposed sidewalls that extend in a first direction in the upper portion of the semiconductor layer structure. These devices further include a deep shielding pattern having a second conductivity type that is opposite the first conductivity type in the semiconductor layer structure underneath a bottom surface of the gate trench, and a deep shielding connection pattern that has the second conductivity type in the first sidewall of the gate trench. The devices include a semiconductor channel region that has the first conductivity type in the second sidewall of the gate trench.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: Cree, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull, Alexander V. Suvorov, Craig Capell
  • Patent number: 9837395
    Abstract: A semiconductor device includes a normally-on junction FET having a gate electrode, a source electrode and a drain electrode and a normally-off MOSFET having a gate electrode, a source electrode and a drain electrode. The source electrode of the junction FET is electrically connected to the drain electrode of the MOSFET, and the junction FET is thus connected to the MOSFET in series. The gate electrode of the junction FET is electrically connected to the gate electrode of the MOSFET.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: December 5, 2017
    Assignee: Renesas Electrics Corporation
    Inventors: Hisashi Toyoda, Koichi Yamazaki, Koichi Arai, Tatsuhiro Seki
  • Patent number: 9780098
    Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 3, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Marc Battista, François Tailliet
  • Patent number: 9768298
    Abstract: A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active region of the substrate and includes a plurality of memory cells, each of which includes a transistor. The transistor has a nano-scaled pillar that extends substantially vertically from the continuous active region of the substrate.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jhon-Jhy Liaw
  • Patent number: 9748342
    Abstract: A semiconductor device according to an embodiment includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC layer provided on the SiC substrate, having a first surface, and having a lower first-conductivity-type impurity concentration than the SiC substrate, first second-conductivity-type SiC regions provided in the first surface of the SiC layer, second second-conductivity-type SiC regions provided in the first SiC regions and having a higher second-conductivity-type impurity concentration than the first SiC region, silicide layers provided on the second SiC regions and having a second surface, a difference between a distance from the SiC substrate to the second surface and a distance from the SiC substrate to the first surface being equal to or less than 0.2 ?m, a first electrode provided to contact with the SiC layer and the silicide layers, and a second electrode provided to contact with the SiC substrate.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: August 29, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Oota, Yoichi Hori, Atsuko Yamashita
  • Patent number: 9728655
    Abstract: A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: August 8, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-Se Ho
  • Patent number: 9728248
    Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: August 8, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Marc Battista
  • Patent number: 9711648
    Abstract: A semiconductor structure is provided that includes a channel material portion composed of a III-V compound semiconductor located on a mesa portion of a substrate. A dielectric spacer structure is located on each sidewall surface of the channel material portion and each sidewall surface of the mesa portion of the substrate. The dielectric spacer structure has a height that is greater than a height of the channel material portion. An isolation structure is located on each dielectric spacer structure, wherein a sidewall edge of the isolation structure is located between an innermost sidewall surface and an outermost sidewall surface of the dielectric spacer structure.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: July 18, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Effendi Leobandung, Chung-Hsun Lin, Amlan Majumdar, Yanning Sun
  • Patent number: 9660030
    Abstract: A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shom Ponoth, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Chih-Chao Yang
  • Patent number: 9633840
    Abstract: A step of preparing a silicon carbide substrate (S11), a step of forming a first silicon carbide semiconductor layer on the silicon carbide substrate using a first source material gas (S12), and a step of forming a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer using a second source material gas (S13) are provided. In the step of forming a first silicon carbide semiconductor layer (S12) and the step of forming a second silicon carbide semiconductor layer (S13), ammonia gas is used as a dopant gas, and the first source material gas has a C/Si ratio of not less than 1.6 and not more than 2.2, the C/Si ratio being the number of carbon atoms to the number of silicon atoms.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 25, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Jun Genba
  • Patent number: 9601604
    Abstract: An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: March 21, 2017
    Assignee: PST Sensors (Proprietary) Limited
    Inventors: David Thomas Britton, Margit Haerting, Stanley Douglas Walton
  • Patent number: 9543453
    Abstract: An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 10, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Koichi Arai
  • Patent number: 9524875
    Abstract: A method of etching trenches into silicon of a semiconductor substrate includes forming a mask over silicon of a semiconductor substrate, with the mask comprising trenches formed there-through. Plasma etching is conducted to form trenches into the silicon of the semiconductor substrate using the mask. In one embodiment, the plasma etching includes forming an etching plasma using precursor gases which include SF6, an oxygen-containing compound, and a nitrogen-containing compound. In one embodiment, the plasma etching includes an etching plasma which includes a sulfur-containing component, an oxygen-containing component, and NFx.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: December 20, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Krupakar M. Subramanian
  • Patent number: 9412808
    Abstract: A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 9, 2016
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Christian Hecht, Roland Rupp, Rudolf Elpelt
  • Patent number: 9276135
    Abstract: An embodiment relates to a JFET with a channel region and a gate region forming a pn junction. Between a source region and a drain region in a semiconductor portion, the pn junction extends along a vertical direction perpendicular to a first surface of the semiconductor portion. The source, channel and drain regions have a first conductivity type and are arranged along the vertical direction. The gate region and a shielding region between the gate and drain regions have a second, complementary conductivity type. An auxiliary region separates the gate and shielding regions in the semiconductor portion.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: March 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Siemieniec, Cedric Ouvrard
  • Patent number: 9105850
    Abstract: A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and the carbon based semiconductor layer; a doping agent precursor source; and environmental chemical controls, configured such that light from the ultraviolet light source irradiates a doping agent precursor and the first carbon layer.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: August 11, 2015
    Assignee: SCHILMASS CO. L.L.C.
    Inventors: Daniel N. Carothers, Rick L. Thompson
  • Patent number: 9093420
    Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: July 28, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Kevin Wesley Kobayashi, Haldane S. Henry, Andrew P. Ritenour
  • Publication number: 20150137143
    Abstract: A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction. A pinch-off voltage of the junction field effect transistor cell does not depend, or only to a low degree depends, on a vertical extension of the lateral channel region.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Publication number: 20150137142
    Abstract: A semiconductor device includes a junction field effect transistor cell with a top gate region, a lateral channel region and a buried gate region. The lateral channel region is arranged between the top gate region and the buried gate region along a vertical direction with respect to a first surface of a semiconductor body. The lateral channel region comprises at least two first zones of a first conductivity type and at least one second zone of a second conductivity type, wherein the first and second zones alternate along the vertical direction. The embodiments provide well-defined channel widths and facilitate the adjustment of pinch-off voltages as well as the manufacture of normally-off junction field effect transistor cells.
    Type: Application
    Filed: November 18, 2013
    Publication date: May 21, 2015
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Patent number: 9018062
    Abstract: In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 28, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Zhongping Liao
  • Patent number: 9006800
    Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 14, 2015
    Assignee: Avogy, Inc.
    Inventors: Linda Romano, Andrew Edwards, Dave P. Bour, Isik C. Kizilyalli
  • Publication number: 20150076568
    Abstract: An embodiment relates to a JFET with a channel region and a gate region forming a pn junction. Between a source region and a drain region in a semiconductor portion, the pn junction extends along a vertical direction perpendicular to a first surface of the semiconductor portion. The source, channel and drain regions have a first conductivity type and are arranged along the vertical direction. The gate region and a shielding region between the gate and drain regions have a second, complementary conductivity type. An auxiliary region separates the gate and shielding regions in the semiconductor portion.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 19, 2015
    Inventors: Ralf Siemieniec, Cedric Ouvrard
  • Patent number: 8969912
    Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8969925
    Abstract: A semiconductor device includes a substrate, a body region adjoining the substrate surface, a source contact region within the body region, a drain contact region adjoining the substrate surface and being separated from the body region, a dual JFET gate region located between the body region and the drain contact region, and a lateral JFET channel region adjoining the surface of the substrate and located between the body and the drain contact regions. A vertical JFET gate region is arranged essentially enclosed by the body region, a vertical JFET channel region being arranged between the enclosed vertical JFET gate and the dual JFET gate regions, a reduced drain resistance region being arranged between the dual JFET gate and the drain contact regions, and a buried pocket located under part of the body region, under the dual JFET gate region and under the vertical JFET channel and reduced drain resistance regions.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 3, 2015
    Assignee: K.Eklund Innovation
    Inventors: Klas-Hakan Eklund, Lars Vestling
  • Patent number: 8963218
    Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Harmeet Sobti, Timothy K. McGuire, David L. Snyder, Scott J. Alberhasky
  • Patent number: 8963217
    Abstract: In one embodiment, a wafer structure configured for a power device can include: (i) a first doping layer having a high doping concentration; (ii) a second doping layer on the first doping layer, where a doping concentration of the second doping layer is less than the high doping concentration; and (iii) a third doping layer on the second doping layer, where a doping concentration of the third doping layer is greater than the doping concentration of the second doping layer. For example, the power device can be part of a switching voltage regulator.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: February 24, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd
    Inventor: Zhongping Liao
  • Publication number: 20150035015
    Abstract: To provide a semiconductor device having a vertical JFET excellent in off-state performance without reducing a production yield. A gate region quadrangular in the cross-section along a channel width direction is formed below a source region by impurity ion implantation. By first etching, the source region over the upper surface of the gate region is removed to separate therebetween. Then, the upper surface of the gate region is processed by second etching having an etching rate lower at the side surface than at the center of the gate region. The resulting gate region has a lower surface parallel to the substrate surface and an upper surface below a boundary between the source region and the channel formation region and having, in the cross-section along the channel width direction, a downward slope from the side surface to the center. As a result, a channel length with reduced variations can be obtained.
    Type: Application
    Filed: July 8, 2014
    Publication date: February 5, 2015
    Inventors: Koichi ARAI, Yasuaki KAGOTOSHI, Kenichi HISADA
  • Patent number: 8946788
    Abstract: A method of growing a III-nitride-based epitaxial structure includes providing a substrate in an epitaxial growth reactor and heating the substrate to a predetermined temperature. The method also includes flowing a gallium-containing gas into the epitaxial growth reactor and flowing a nitrogen-containing gas into the epitaxial growth reactor. The method further includes flowing a gettering gas into the epitaxial growth reactor. The predetermined temperature is greater than 1000° C.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: February 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8929090
    Abstract: An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: January 6, 2015
    Assignee: NEC Corporation
    Inventors: Yoshiki Nakashima, Shintaro Yamamichi, Katsumi Kikuchi, Kentaro Mori, Hideya Murai
  • Publication number: 20140361349
    Abstract: A shielded junction field effect transistor (JFET) is described having gate trenches and shield trenches, the shield trenches being deeper and narrower than the gate trenches. The gate trenches may be fully aligned, partially aligned, or separated from the shield trenches.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventors: Peter Alexandrov, Anup Bhalla
  • Publication number: 20140353667
    Abstract: A field-effect semiconductor device having a semiconductor body with a main surface is provided. The semiconductor body includes, in a vertical cross-section substantially orthogonal to the main surface, a drift layer of a first conductivity type, a semiconductor mesa of the first conductivity type adjoining the drift layer, substantially extending to the main surface and having two side walls, and two second semiconductor regions of a second conductivity type arranged next to the semiconductor mesa. Each of the two second semiconductor regions forms a pn-junction at least with the drift layer. A rectifying junction is formed at least at one of the two side walls of the mesa. Further, a method for producing a heterojunction semiconductor device is provided.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Jens Konrath, Hans-Joachim Schulze, Roland Rupp, Wolfgang Werner, Frank Pfirsch
  • Patent number: 8895370
    Abstract: A vertical conduction power device includes respective gate, source and drain areas formed in an epitaxial layer on a semiconductor substrate. The respective gate, source and drain metallizations are formed by a first metallization level. The gate, source and drain terminals are formed by a second metallization level. The device is configured as a set of modular areas extending parallel to each other. Each modular area has a rectangular elongate source area perimetrically surrounded by a gate area, and a drain area defined by first and second regions. The first regions of the drain extend parallel to one another and separate adjacent modular areas. The second regions of the drain area extend parallel to one another and contact ends of the first regions of the drain area.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Angelo Magri′
  • Patent number: 8890279
    Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: November 18, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Mei-Ling Chen, Tse-Chuan Su, Hung-Hsin Kuo
  • Patent number: 8883576
    Abstract: Provided are methods of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, forming a mask layer on the mold layer, etching the mold layer using the mask layer as an etch mask to form a channel hole penetrating the mold layer, shrinking the mask layer to provide a reduced mask layer, forming a spacer layer to cover the reduced mask layer, and forming a vertical channel to fill the channel hole and be electrically connected to the substrate. As a result, the channel hole can have an enlarged entrance.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinkwan Lee, Yoochul Kong, Seongsoo Lee
  • Patent number: 8872242
    Abstract: A silicon carbide substrate has a first conductivity type. The silicon carbide substrate has a first surface provided with a first electrode and a second surface provided with first trenches arranged to be spaced from one another. A gate layer covers an inner surface of each of the first trenches. The gate layer has a second conductivity type different from the first conductivity type. A filling portion fills each of the first trenches covered with the gate layer. A second electrode is separated from the gate layer and provided on the second surface of the silicon carbide substrate. A gate electrode is electrically insulated from the silicon carbide substrate and electrically connected to the gate layer. Thereby, a silicon carbide semiconductor device capable of being easily manufactured can be provided.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hideki Hayashi, Takeyoshi Masuda
  • Patent number: 8860098
    Abstract: The present disclosure describes structures and processes to produce high voltage JFETs in wide-bandgap materials, most particularly in Silicon Carbide. The present disclosure also provides for products produced by the methods of the present disclosure and for apparatuses used to perform the methods of the present disclosure.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 14, 2014
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Peter Alexandrov
  • Patent number: 8847290
    Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Shinichi Ishizawa
  • Patent number: 8841708
    Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: September 23, 2014
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Richard J. Brown, Hui Nie
  • Publication number: 20140264477
    Abstract: The present disclosure describes structures and processes to produce high voltage JFETs in wide-bandgap materials, most particularly in Silicon Carbide. The present disclosure also provides for products produced by the methods of the present disclosure and for apparatuses used to perform the methods of the present disclosure.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Peter Alexandrov
  • Patent number: 8829574
    Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: September 9, 2014
    Assignee: Avogy, Inc.
    Inventors: Donald R. Disney, Isik C. Kizilyalli, Hui Nie, Linda Romano, Richard J. Brown, Madhan Raj
  • Patent number: 8791510
    Abstract: A semiconductor device includes a gate structure on a semiconductor substrate, an impurity region at a side of the gate structure and the impurity region is within the semiconductor substrate, an interlayer insulating layer covering the gate structure and the impurity region, a contact structure extending through the interlayer insulating layer and connected to the impurity region, and an insulating region. The contact structure includes a first contact structure that has a side surface surrounded by the interlayer insulating layer and a second contact structure that has a side surface surrounded by the impurity region. The insulating region is under the second contact structure.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Kyu Lee
  • Patent number: 8772109
    Abstract: A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: July 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jean-Pierre Colinge