Abstract: A junction field effect transistor (JFET) with a reduced gate capacitance. A gate definition spacer is formed on the wall of an etched trench to establish the lateral extent of an implanted gate region for a JFET. After implant, the gate is annealed. In addition to controlling the final junction geometry and thereby reducing the junction capacitance by establishing the lateral extent of the implanted gate region, the gate definition spacer also limits the available diffusion paths for the implanted dopant species during anneal. Also, the gate definition spacer defines the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A semiconductor device includes: a gate electrode that is provided on a semiconductor layer; a source electrode and a drain electrode that are provided on the semiconductor layer so as to interpose the gate electrode; a source wall that extends from the source electrode to a point between the gate electrode and the drain electrode through the region above the gate electrode, the source wall having a joining portion in the extending region; and an electrode portion that is joined to the joining portion and has a region extending closer to the drain electrode than the joining portion.

Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

Abstract: A silicon carbide semiconductor device that includes J-FETs has a drift layer of epitaxially grown silicon carbide having a lower impurity concentration level than a substrate on which the drift layer is formed. Trenches are formed in the surface of the drift layer, and first gate areas are formed on inner walls of the trenches. Second gate areas are formed in isolation from the first gate areas. A source area is formed on channel areas, which are located between the first and second gate areas in the drift layer. A method of manufacturing the device ensures uniform channel layer quality, which allows the device to have a normally-off characteristic, small size, and a low likelihood of defects.

Abstract: A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.

Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

Abstract: In a field effect transistor having an active region defined by a device isolation region, and a gate electrode formed over the active region, in the lateral direction of the gate electrode, the source and drain formed in the active region is narrower than the active region at least at the parts proximate to each other to create a rounding region for allowing an additional current to flow through the rounding region. This increases the on-current, with almost no increase in the off-current. The operation speed is thereby increased, without increase in the power consumption during stand-by.

Abstract: A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain.

Abstract: A high-breakdown-voltage semiconductor device comprises a high-resistance semiconductor layer, trenches formed on the surface thereof in a longitudinal plane shape and in parallel, first regions formed on the semiconductor layer to be sandwiched between adjacent ones of the trenches and having an impurity concentration higher than that of the semiconductor layer, a second region having opposite conductivity to the first regions and continuously disposed in a trench sidewall and bottom portion, a sidewall insulating film disposed on the second region of the trench sidewall, a third region disposed on the second region of the trench bottom portion and having the same conductivity as and the higher impurity concentration than the second region, a fourth region disposed on the back surface of the semiconductor layer, a first electrode formed on each first region, a second electrode connected to the third region, and a third electrode formed on the fourth region.

Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.

Abstract: A MOSgated device has spaced vertical trenches lined with a gate oxide and filled with a P type polysilicon gate. The gate oxide extends along a vertical N− channel region disposed between an N+ source region and an N− drift region. A Schottky barrier of aluminum is disposed adjacent the accumulation region extending along the trench to collect holes which are otherwise injected into the source region during voltage blocking. A common source or drain contact is connected to the N+ region and to the Schottky contact. A two gate embodiment is disclosed in which separately energized gates are connected to alternatively located gate polysilicon volumes.

Abstract: Semiconductor memory devices are provided that comprise unit memory cells. The unit memory cells include a first planar transistor in a semiconductor substrate, a vertical transistor disposed on the first planar transistor and a second planar transistor in series with the first planar transistor. The first planar transistor and the second planar transistor may have different threshold voltages. The semiconductor memory device may further include word lines. One of these word lines may form the gate of the second planar transistor a unit memory cell.

Abstract: The semiconductor device according to the present invention has a semiconductor layer having not smaller than two types of crystal grains different in size within a semiconductor circuit on a same substrate.

Abstract: Described is a method for fabricating a semiconductor device having an FET of a trench-gate structure obtained by disposing a conductive layer, which will be a gate, in a trench extended in the main surface of a semiconductor substrate, wherein the upper surface of the trench-gate conductive layer is formed equal to or higher than the main surface of the semiconductor substrate. In addition, the conductive layer of the trench gate is formed to have a substantially flat or concave upper surface and the upper surface is formed equal to or higher than the main surface of the semiconductor substrate. Moreover, after etching of the semiconductor substrate to form the upper surface of the conductive layer of the trench gate equal to or higher than the main surface of the semiconductor substrate, a channel region and a source region are formed by ion implantation. The semiconductor device thus fabricated according to the present invention is free from occurrence of a source offset.

Abstract: FLASH memory circuitry includes an array area and peripheral circuitry area. Multiple series of spaced isolation trenches are provided. At least one of the series of spaced trench isolation regions is formed in a semiconductor substrate within the FLASH peripheral circuitry area. At least some of the FLASH peripheral circuitry area spaced trench isolation regions have maximum depths which are greater than first and second maximum depths of trench isolation regions formed within array area.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: An enhancement mode RF device and method of fabrication includes a stack of compound semiconductor layers, including a central layer defining a device channel, a doped cap layer, and a buffer epitaxially grown on a substrate. Source and drain implant areas, extending at least into the buffer, are formed to define an implant free area in the device channel between the source and drain. Source and drain metal contacts are positioned on an upper surface of the central layer. Several layers of insulation and dielectric are positioned over the device and a gate opening is formed and filled with gate metal. During epitaxial growth, the doped cap layer is tailored with a thickness and a doping to optimize channel performance including gate-drain breakdown voltage and channel resistance.

Abstract: An enhancement mode semiconductor device has a barrier layer disposed between the gate electrode of the device and the semiconductor substrate underlying the gate electrode. The barrier layer increases the Schottky barrier height of the gate electrode-barrier layer-substrate interface so that the portion of the substrate underlying the gate electrode operates in an enhancement mode. The barrier layer is particularly useful ill compound semiconductor field effect transistors, and preferred materials for the barrier layer include aluminum gallium arsenide and indium gallium arsenide.

Abstract: A field effect transistor device has a semiconductor substrate having a predetermined impurity concentration of a first conductivity type. Inpurity layers of a second conductivity type are formed spaced apart at the main surface of the semiconductor substrate. The impurity layers make up source/drain regions. A region between the impurity layers defines a channel region. A notch-shaped conductive layer is formed on the channel region. The notch-shaped conductive layer has an upper layer section longer than a lower layer section. The upper and lower layer sections are formed of at least two different materials, one being silicon-germanium layer with varying germanium content. The material of the lower layer section can be etched at a greater rate than the material of the upper layer section during a common etching process.

Abstract: An epi-channel of a uniform shape is formed by adjusting the temperature and pressure of H2 bake process to prevent the etching of a separation oxide at an interface of an active region and a field region thereby ensuring that an epi-channel is formed having a uniform shape.

Abstract: A semiconductor device having an NMOSFET and a PMOSFET. Each MOSFET comprises first and second impurity diffusion layers for forming a source region and a drain region which are formed in a silicon layer of an SOI substrate or the like; a channel region formed between the first and second impurity diffusion layers; a gate insulating layer formed at least on the channel region; and a gate electrode formed on the gate insulating layer. The gate electrode includes a tantalum nitride layer formed in a region in contact with at least the gate insulating layer and a tantalum layer formed over the tantalum nitride layer. The tantalum layer may have a body-centered cubic crystal structure. The semiconductor device exhibits high current drive capability and can be fabricated at high yield.

Abstract: Junction Field Effect Transistor (JFET) offers fast switching speed than bipolar transistor since JFET is a majority carrier device. This invention comprises two normally “off” JFETs, one in N-channel and one in P-channel to form Complementary Junction Field Effect Transistors for high speed, low voltage and/or high current applications. The discrete device structure is disclosed in this invention. The integrated Complementary Junction Field Effect Transistors structure processed in standard CMOS process is disclosed in this invention. A vertical gate structure of Complementary Junction Field Effect Transistors is disclosed. Complementary Junction Field Effect Transistors structure is also disclosed in SOI substrate.

Abstract: The invention concerns a controllable semiconductor structure comprising a base region (101, 201, 301, 401), a source region (106, 212, 312, 412) and a drain region (107, 213, 313, 413) a conductive duct being provided in the base region between the source and drain. According to the invention, the duct can be constricted by regions lying parallel thereto, an active control region (102, 202, 302, 402) and an opposite passive control region (103, 203, 303, 403) which each form a blockable passage with the base region (101, 201, 301, 401). Further provided is a conductive connection (108, 209, 309, 409) between the passive control region (103, 203, 303, 403) and the source region (106, 212, 312, 412), the semiconductor material of the base region (101, 201, 301, 401) having an energy gap of more than 1.2 eV.

Abstract: An MOS device and the method of making the device which includes a semiconductor substrate having a well therein of predetermined conductivity type. A tank having a surface is disposed within the well. The tank has a highly doped region of opposite conductivity type and a lightly doped region of opposite conductivity type between the highly doped region and the surface of tank. The lightly doped region in the tank is doped both the predetermined conductivity type and the opposite conductivity type with a resulting net lightly opposite conductivity type doping. A drain region of opposite conductivity type is disposed in the region of the tank between the highly doped region and the surface and disposed at the surface and a source region of opposite conductivity type is disposed in the well and spaced from the tank.

Abstract: An analog circuit starter current source device with automatic shut-down capability. The device includes a semiconductor substrate (typically p-type) with a deep well region (typically n-type) below its surface, a first surface well region (typically n-type) on the surface of the substrate that circumscribes the deep well region, and a narrow channel region (typically p-type) separating the deep well region from the first surface well region. The device also includes a first contact region for connecting the first surface well region to the analog circuit, and a second contact region for connecting a substrate region above the deep well to the analog circuit. The configuration provides a variable-width vertical resistor current path capable of starting an analog circuit and then being automatically shut-down by application of a potential to the first contact region sufficient to produce a depletion region that pinches-off the narrow channel region.

Abstract: A carrier transfer layer of compound semiconductor material is disposed on or over a support substrate, and a gate electrode of conductive material is disposed on or over the carrier transfer layer at a partial region thereof. A cap layer of non-doped compound semiconductor material is disposed on or over the carrier transfer layer at both sides of the gate electrode. The thickness of the cap layer is 100 nm or thicker. two current electrodes are formed in ohmic contact with the carrier transfer layer. An enhancement mode MESFET is provided whose gain and output power are suppressed from being lowered.

Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut.

Abstract: A static induction transistor fabricated of silicon carbide, preferably 6H polytype, although any silicon carbide polytype may be used. The preferred static induction transistor is the recessed Schottky barrier gate type. Thus, a silicon carbide substrate is provided. Then, a silicon carbide drift layer is provided upon the substrate, wherein the drift layer has two spaced-apart protrusions or fingers which extend away from the substrate. Each protrusion of the drift layer has a source region of silicon carbide provided thereon. A gate material is then provided along the drift layer between the two protrusions. A conductive gate contact is provided upon the gate material and a conductive source contact is provided upon each source region. A conductive drain contact is provided along the substrate. Other gate types for the static induction transistor are contemplated. For example, a planar Schottky barrier gate may be employed.

Abstract: The present invention is to provide a Static Induction semiconductor device with a Static Induction Schottky shorted structure where the main electrode region is composed of regions of higher and lower impurity densities relative to each other, the main electrode forms an ohmic contact with the higher impurity density region and also forms a Schottky contact with a Static Induction Schottky shorted region of the lower impurity density region surrounded by tile higher impurity density region, and it is excellent in turn-off performance and easy to use, by substantially reducing tile minority carrier storage time, the fall time and the quantity of gate pull-out charges in order that charges may easily be pulled out from the cathode or source electrode as well as from the gate electrode at turn-off.

Abstract: A semiconductor device includes a substrate crystal of a type for epitaxial growth thereon. The substrate crystal has a (111)A face and a (111)B face. Also provided are at least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition, thereby providing a structure having a source and a drain. A gate side includes the (111)B face of the substrate crystal. A gate insulating layer is deposited by way of epitaxial growth on the gate side according to molecular layer epitaxy. Alternatively, the at least two semiconductor regions may be deposited on the (111)B face of the substrate crystal according to molecular layer epitaxy, and the gate insulating layer may be deposited on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition.

Abstract: A lateral static induction transistor suited for use as a picture element of a solid state imaging device. The lateral static induction transistor includes a semiconductor substrate of a first conduction type of P type or N type, a first epitaxial layer of the same conduction type as the first conduction type which is formed on the semiconductor substrate, a second epitaxial layer of a second conduction type opposite to the first conduction type which is formed on the first epitaxial layer, a source zone and a plurality of drain zones which are formed in the second epitaxial layer near the surface thereof, and a plurality of gates each thereof being formed so as to partially lie over the source zone and one of the drain zones on the second epitaxial layer through an insulating layer.

Abstract: A self-cascoding transconductance circuit has cascoding and current sink/source FETs, serially connected with their gates tied together to receive an input voltage, wherein the cascoding FET has a threshold voltage having an absolute value at least 0.1 volts less than that of the current sink/source FET to ensure that the current sink/source FET operates in its saturated region. A CMOS structure implementing the self-cascoding transconductance circuit has two doped threshold adjust regions formed beneath a gate electrode such that the two doped threshold adjust regions respectively effectuate the cascode and current sink/source FETs which then share the gate electrode. A method of forming the CMOS structure includes forming two self-cascoding transconductance circuits electrically connected in parallel such that they share a common drain region between their respective gate electrodes, and each has one source region.

Abstract: A Fermi-FET includes a Fermi-tub region at a semiconductor substrate surface, wherein the Fermi-tub depth is bounded between a maximum tub depth and a minimum tub depth. The Fermi-tub depth is sufficiently deep to completely deplete the Fermi-tub region by the substrate tub junction at the threshold voltage of the field effect transistor, and is also sufficiently shallow to produce a closed inversion injection barrier between the source region and the drain region below the threshold voltage of the Fermi-FET. High saturation current and low leakage current are thereby produced simultaneously. Source and drain injector regions and a gate sidewall spacer may also be provided.

Abstract: A JFET configuration is obtained whose pinch-off voltage can be set by means of mask dimensions, without process changes, and which is at the same time suitable for operation at very low and very high voltages by cascoding of a first JFET with a diffused or implanted channel which is pinched off in lateral direction, parallel to the surface of the semiconductor body, with a second JFET with a high breakdown voltage and a higher pinch-off voltage than the first JFET. To increase the breakdown voltage still further, the combination of the first and second JFET may be further cascoded, without process changes, with a third JFET which has a channel of the conductivity type opposite to that of the first and second JFET.

Abstract: A static induction type semiconductor device of a surface gate type, includes a source region, gate region and drain region. A channel region is formed between the drain region and the source region, such that when a bias potential is applied between the gate region and the source region, carriers flow to the drain region from the source region via the channel region. A source electrode is provided on the semiconductor layer. A source contact region is provided between the source electrode and the source region to establish electrical connection therebetween. The source contact region is segmented into a plurality of smaller regions or sections whose total area is smaller than the area of the corresponding portion of the source region, for improving the current gain, and for preventing or significantly reducing local current concentration.

Abstract: An improved Fermi FET structure with low gate and diffusion capacity allows conduction carriers to flow within the channel at a predetermined depth in the substrate below the gate, without requiring an inversion layer to be created at the surface of the semiconductor. The low capacity Fermi FET is preferably implemented using a Fermi Tub having a predetermined depth, and with a conductivity type opposite the substrate conductivity type and the same conductivity type as the drain and source diffusions.