With Bipolar Device Patents (Class 257/273)
  • Patent number: 12068484
    Abstract: A method for producing an electrode material for a lithium-ion secondary battery. The method includes the following steps: (a) mixing components of a basic ingredient or active substance of electrode material and a conductive carbon material to obtain a conductive carbon material-composited material; (b) mixing the conductive carbon material-composited material and a surface layer-forming material; an (c) burning the mixture obtained at step (b) to obtain the electrode material. Also, a lithium-ion secondary battery including an electrode which includes the material.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: August 20, 2024
    Assignee: HYDRO-QUÉBEC
    Inventors: Vincent Gariepy, Abdelbast Guerfi, Kazuma Hanai, Pierre Hovington, Shinji Saito, Takehiko Sawai, Kazunori Urao, Karim Zaghib
  • Patent number: 11934081
    Abstract: An electro-optic device, and its method of manufacturing, is disclosed comprises a first substrate layer, a conductive film comprising a first adhesive layer and a first electrode layer, an electro-optic material layer, and a second electrode layer. The first electrode layer, which is on contact with the electro-optic material layer, comprises a conductive material, such as conductive particles, a metallic material or a conductive polymer. The first adhesive layer has high storage modulus and does not exhibit plastic flow under the conditions of manufacturing, storage, and operation of the electro-optic device. The conductive film does not conform to the surface roughness of the first surface of the electro-optic material layer. The conductive film may be designed to be thin, flexible and transparent. The resulting electro-optic device exhibit excellent electro-optic performance even where the electro-optic material layer has imperfections in the form of gaps.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 19, 2024
    Assignee: E Ink Corporation
    Inventors: Nishit Murari, Jay William Anseth
  • Patent number: 10817043
    Abstract: A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 27, 2020
    Assignee: NVIDIA Corporation
    Inventors: Rajeev Jayavant, Thomas E. Dewey, David Wyatt
  • Patent number: 10784372
    Abstract: Described is a semiconductor device including a first N-type well region disposed in a substrate and a second N-type well region in contact with the first N-type well region, a source region disposed in the first N-type well region, a drain region disposed in the second N-type well region, and a first gate electrode and a second gate electrode disposed spaced apart from the drain region. A maximum vertical length of the source region in a direction vertical to the first or second gate electrode is greater than a maximum vertical length of the drain region in the direction in a plan view.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 22, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Young Bae Kim
  • Patent number: 10438843
    Abstract: A structure of semiconductor device includes a substrate. A first dielectric layer is disposed over the substrate, wherein the first dielectric layer has an air trench. A plurality of trench metal layers is disposed in the first dielectric layer, wherein the air trench is between adjacent two of the trench metal layers and without contacting to the trench metal layers. A liner layer is disposed on the first dielectric layer to cover the trench metal layers and a profile of the air trench. An etching stop layer is disposed on the liner layer, wherein the etching stop layer seals the air trench to form an air gap between the adjacent two of the trench metal layers.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 8, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Tzu-Hao Fu, Ci-Dong Chu, Tsung-Yin Hsieh, Chih-Sheng Chang
  • Patent number: 10209215
    Abstract: A semiconductor based integrated sensor device includes: a lateral insulating-gate field effect transistor (MOSFET) connected in series to the base of a vertical bipolar junction transistor (BJT) wherein the drain-drift-region of the MOSFET is part of the base-region of the BJT within the semiconductor substrate thus making electrical contact to the base of the BJT and the distance of the drain-drift-region of the MOSFET to the emitter of the BJT exceeds the vertical distance between the emitter and any buried layer, serving as collector, and the breakdown voltage of the device being determined by the BVCEO of the vertical BJT.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: February 19, 2019
    Assignee: K.EKLUND INNOVATION
    Inventors: Klas-Hakan Eklund, Shili Zhang, Ulf Smith, Hans Erik Norstrom
  • Patent number: 10096707
    Abstract: The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 9, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim
  • Patent number: 9991367
    Abstract: A bipolar junction transistor (BJT) includes an emitter region, a base region surrounding the emitter region, and a collector region surrounding the base region. The emitter region includes a fin structures extending along a first direction, a first metal gate extending across the fin structure along a second direction, and a second metal gate disposed in parallel with the first metal gate. A spacing between the first metal gate and the second metal gate ranges between 0.2 micrometers and 0.4 micrometers.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 5, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chen-Wei Pan
  • Patent number: 9954074
    Abstract: An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: April 24, 2018
    Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventors: Shengrong Zhong, Xiaoshe Deng, Genyi Wang, Dongfei Zhou
  • Patent number: 9947786
    Abstract: The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 17, 2018
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim
  • Patent number: 9905679
    Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. The bipolar transistor includes a collector having a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a reduced surface field (RESURF) gate located above an upper surface of the laterally extending drift region for shaping an electric field within the collector. The bipolar transistor further includes a gap located between the reduced surface field gate and an extrinsic region of the base of the device, for electrically isolating the reduced surface field gate from the base. A lateral dimension Lgap of the gap is in the range 0.1 ?m?Lgap?1.0 ?m.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 27, 2018
    Assignee: NXP B.V.
    Inventors: Petrus Hubertus Cornelis Magnee, Joost Melai, Viet Thanh Dinh, Tony Vanhoucke
  • Patent number: 9666586
    Abstract: A memory cell and a process for production thereof, the memory cell having a CMOS substrate having two adjacent wells of opposite conductivity types, having trench isolation between the wells, wherein one of the wells is connected to a ground voltage level and the other one to a constant voltage level; a shallow lightly doped n layer in a first one of the wells; a shallow lightly doped p layer in a second one of the wells; at least a first and second deep heavily doped p regions in the first well; at least a first and second deep heavily doped n regions in the second well; and a conductor to connect the first and second deep p regions, the shallow n region, the first and second deep n regions and the shallow p region to the same input voltage level relative to the ground voltage level.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 30, 2017
    Inventor: Gil Asa
  • Patent number: 9653455
    Abstract: A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off. This can reduce transient drive current flows that may perturb other components.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: May 16, 2017
    Assignee: Analog Devices Global
    Inventor: Edward John Coyne
  • Patent number: 9472661
    Abstract: A semiconductor structure suitable for operating under a high voltage condition is provided. According to one aspect of the disclosure, the semiconductor structure includes a substrate, a gate, a source region, a drain region and a field-adjusting structure. The gate is disposed on the substrate. The source region and the drain region are disposed in the substrate and at opposite sides of the gate. The field-adjusting structure is disposed on the substrate at an outer side of one of the source region and the drain region. The field-adjusting structure comprises a first portion and a second portion. The second portion is disposed at an outer side of the first portion. The first portion is connected to the gate. The second portion is connected to the one of the source region and the drain region.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: October 18, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Chang-Po Hsiung
  • Patent number: 9455319
    Abstract: A semiconductor device and an operating method of the same are disclosed. The semiconductor device includes a substrate, a source region, a drain region, a gate structure, a first lightly-doped region, and a first isolation region. The source region and the drain region are formed in the substrate. The gate structure is formed on the substrate and between the source region and the drain region. The first lightly-doped region is formed below the source region. The first isolation region is formed in the substrate and surrounding the source region, the drain region, and the first lightly-doped region. The source region and the drain region have a first-polarity, and the first lightly-doped region and the first isolation region have a second-polarity.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Wei-Shan Liao
  • Patent number: 9331097
    Abstract: High speed bipolar junction transistor switches for high voltage operations. An example switch includes a bipolar junction transistor including a collector region positioned over a buried insulator region. The collector region includes dopants of a first conductivity type. A field effect transistor includes a source region also positioned over a buried insulator region. The source region electrically is coupled to the collector region such that all current passing the collector region enters the source region.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 3, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Jeng-bang Yau
  • Patent number: 9263438
    Abstract: In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: February 16, 2016
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Sunglyong Kim, Jongjib Kim
  • Patent number: 9130027
    Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm?3 and 1×1020 cm?3, and/or the oxygen concentration within 5×1018 cm?3 and 1×1020 cm?3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: September 8, 2015
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Yu-Chung Chin, Chao-Hsing Huang
  • Patent number: 9024365
    Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Patent number: 8963253
    Abstract: A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Hsin-Liang Chen, Shuo-Lun Tu
  • Publication number: 20150001590
    Abstract: A semiconductor device that is equipped with an ESD protection element, which has a size increase thereof suppressed, does not require extra process, and can be formed without inducing deterioration of characteristics of the semiconductor device. This semiconductor device includes a semiconductor substrate, a circuit element, that includes a PN junction formed of a region, which is formed on the semiconductor substrate, and which has a conductivity type different from that of the substrate and a protection element for the circuit element. The protection element is a transistor formed of the region, another region having the conductivity type same as that of the region, and the semiconductor substrate. The emitter for the transistor and the semiconductor substrate are connected to each other.
    Type: Application
    Filed: February 28, 2012
    Publication date: January 1, 2015
    Applicant: NEW JAPAN RADIO CO., LTD.
    Inventors: Hideaki Matsumoto, Jun Yamashita, Kenji Esashika, Takao Sugino
  • Publication number: 20140361303
    Abstract: Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level.
    Type: Application
    Filed: June 5, 2013
    Publication date: December 11, 2014
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoar-Tabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Publication number: 20140361350
    Abstract: Complementary circuits based on junction (or heterojunction) field effect transistor devices and bipolar junction (or heterojunction) transistor devices comprised of thin crystalline semiconductor-on-insulator substrates are provided which are compatible with low-cost and/or flexible substrates. Only one substrate doping type (i.e., n-type or p-type) is required for providing the complementary circuits and thus the number of masks (typically three or four) remains the same as that required for either n-channel or p-channel devices in the TFT level.
    Type: Application
    Filed: July 19, 2013
    Publication date: December 11, 2014
    Applicant: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Bahman Hekmatshoar-Tabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8878594
    Abstract: An embodiment of an IGBT device is integrated in a chip of semiconductor material including a substrate of a first type of conductivity, an active layer of a second type of conductivity formed on an inner surface of the substrate, a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the inner surface, a source region of the second type of conductivity extending within the body region from the front surface, a channel region being defined within the body region between the source region and the active layer, a gate element insulated from the front surface extending over the channel region, a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface, an emitter terminal contacting the source region and the body region on the front surface, and a gate terminal contacting the gate element.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: November 4, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventor: Davide Giuseppe Patti
  • Patent number: 8866194
    Abstract: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shinya Naito, Hideaki Fujiwara, Toru Dan
  • Patent number: 8859361
    Abstract: A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: October 14, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 8817435
    Abstract: A method for making a semiconductor device includes providing a substrate of a first conductivity type and having a surface region, forming a well region of a second conductivity type and having a first depth in the substrate, adding a gate dielectric layer overlying the surface region, adding a gate layer overlying the gate dielectric layer, forming a first LDD region of the first conductivity type and having a second depth within the well region, forming an emitter region of the second conductivity type within the first LDD region, and forming a second LDD region of the first conductivity type with the well region, a channel region separates the first and second LDD regions. The method further includes forming a source region being of the first conductivity type within the second LDD region and adding an output pad coupled to both the drain and emitter regions.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corp.
    Inventors: Chi Kang Liu, Ta Lee Yu, Quan Li
  • Patent number: 8786024
    Abstract: A combined switching device includes a MOSFET disposed in a MOSFET area and IGBTs disposed in IGBT areas of a SiC substrate. The MOSFET and the IGBTs have gate electrodes respectively connected, a source electrode and emitter electrodes respectively connected, and a drain electrode and a collector electrode respectively connected. The MOSFET and the IGBTs are disposed with a common n-buffer layer. A top surface element structure of the MOSFET and top surface element structures of the IGBTs are disposed on the first principal surface side of the SiC substrate. Concave portions and convex portions are disposed on the second principal surface side of the SiC substrate. The MOSFET is disposed at a position corresponding to the convex portion of the SiC substrate. The IGBTs are disposed at positions corresponding to the concave portions of the SiC substrate.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 22, 2014
    Assignees: Yoshitaka Sugawara, Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8779473
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device that includes a substrate; a buried oxide layer near a bottom of the substrate; a collector region above and in contact with the buried oxide layer; a field oxide region on each side of the collector region; a pseudo buried layer under each field oxide region and in contact with the collector region; and a through region under and in contact with the buried oxide layer. A method for manufacturing a SiGe HBT device is also disclosed. The SiGe HBT device can isolate noise from the bottom portion of the substrate and hence can improve the intrinsic noise performance of the device at high frequencies.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: July 15, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Jing Shi, Wenting Duan, Wensheng Qian, Jun Hu
  • Patent number: 8766331
    Abstract: In a semiconductor module according to certain aspects the invention, a U-terminal and an M-terminal overlap each other in a manner to reduce inductance and to further to reduce the size of snubber capacitor. In certain aspects of the invention, a P-terminal, M-terminal, N-terminal, and U-terminal are arranged such that the U-terminal, through which currents flow in and out, is arranged farthest away from control electrodes to reduce the noises superposed to control electrodes, and the P-terminal, M-terminal, N-terminal, and U-terminal are aligned to facilitate attaching external connection bars thereto. A power semiconductor module according to aspects of the invention can facilitate reducing the wiring inductance inside and outside the module, reducing the electromagnetic noises introduced into the control terminals, and attaching the external wirings to the terminals thereof simply and easily.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: July 1, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Souichi Okita
  • Publication number: 20140138749
    Abstract: One or more techniques or systems for forming an integrated circuit (IC) or associated IC structure are provided herein. In some embodiments, the IC includes a junction gate field effect transistor (JFET) and a lateral vertical bipolar junction transistor (LVBJT). For example, the JFET and the LVBJT are formed in a same region, such as a substrate. In some embodiments, the JFET and the LVBJT are at least one of adjacent or share one or more features. In this manner, a reliable IC is provided, thus enabling power amplification, for example.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Patent number: 8653556
    Abstract: A vertical semiconductor device includes a semiconductor body, and first and second contacts on opposite sides of the semiconductor body. A plurality of regions are formed in the semiconductor body including, in a direction from the first contact to the second contact, a first region of a first conductivity type, a second region of a second conductivity type; and a third region of the first conductivity type. The third region is electrically connected to the second contact. A semiconductor zone of the second conductivity type and increased doping density is arranged in the second region. The semiconductor zone separates a first part of the second region from a second part of the second region. The semiconductor zone has a maximum doping density exceeding about 1016 cm?3 and a thickness along the direction from the first contact to the second contact of less than about 3 ?m.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: February 18, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Josef Niedernostheide, Hans-Joachim Schulze
  • Patent number: 8648391
    Abstract: The product of the breakdown voltage (BVCEO) and the cutoff frequency (fT) of a SiGe heterojunction bipolar transistor (HBT) is increased beyond the Johnson limit by utilizing a doped region with a hollow core that extends down from the base to the heavily-doped buried collector region. The doped region and the buried collector region have opposite dopant types.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Patent number: 8618584
    Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 31, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Seiji Otake, Yasuhiro Takeda, Yuta Miyamoto
  • Patent number: 8470685
    Abstract: The present invention provides an improved method of forming air cavities to overcome IC via-misalignment issues. The method of forming air cavity trenches in-between metal lines of an integrated circuit includes the steps of partially removing (42) an intertrack dielectric deposited on an interconnect structure surface to control the height between the top surface of a metal line of the interconnect surface and the surface of the intertrack dielectric; depositing (44) a dielectric liner on the interconnect surface; removing (46) at least part of the dielectric liner on the interconnect surface; successively repeating (48) the deposition of the dielectric liner and the removal of the dielectric liner on the interconnect surface in so far as the interconnect surface is sufficiently protected by a remaining dielectric liner for forming of the plurality of air cavity trenches; and forming (50) at least one air cavity trench in-between the metal lines by etching the intertrack dielectric material.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: June 25, 2013
    Assignees: STMicroelectronics (Crolles 2) SAS, Koninklijke Philips Electronics N.V.
    Inventors: Joaquin Torres, Laurent-Georges Gosset
  • Patent number: 8421127
    Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: April 16, 2013
    Assignee: Windbond Electronics Corp.
    Inventor: Wen-Yueh Jang
  • Publication number: 20130087836
    Abstract: A channel region having a first conductivity type is disposed in a surface portion of a semiconductor substrate. A gate region having a second conductivity type is disposed in a surface portion of the channel region. A first semiconductor region having the second conductivity type is disposed under the channel region. Source/drain regions having the first conductivity type are disposed in parts of the surface portion of the channel region on both sides of the gate region in a channel length direction. Second semiconductor regions each having a high impurity concentration and the second conductivity type are disposed in parts of the semiconductor substrate on both sides of the channel region in a channel width direction.
    Type: Application
    Filed: November 30, 2012
    Publication date: April 11, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Panasonic Corporation
  • Patent number: 8390065
    Abstract: An object is to reduce the resistance of each member included in a transistor, to improve ON current of the transistor, and to improve performance of an integrated circuit. A semiconductor device including an n-channel FET and a p-channel FET which are provided over a single crystal semiconductor substrate with an insulating layer provided therebetween and are isolated by an element isolation insulating layer. In the semiconductor device, each FET includes a channel formation region including a semiconductor material, a conductive region which is in contact with the channel formation region and includes the semiconductor material, a metal region in contact with the conductive region, a gate insulating layer in contact with the channel formation region, a gate electrode in contact with the gate insulating layer, and a source or drain electrode partly including the metal region.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8319273
    Abstract: Devices and methods for forming self-aligned charge storage regions are disclosed. In one embodiment, a method for manufacturing a semiconductor device comprises forming a layer of a nitride film stacked between two oxide films on a semiconductor substrate, and forming a gate electrode on the layer of the nitride film stacked between the two oxide films. In addition, the method comprises removing side portions of the nitride film such that a central portion of the nitride film below a center portion of the gate electrode remains, oxidizing the central portion of the nitride film, and forming charge storage layers in the side portions of the nitride film, where the charge storage layers are separated by the central portion of the nitride film.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: November 27, 2012
    Assignee: Spansion LLC
    Inventor: Fumihiko Inoue
  • Patent number: 8305803
    Abstract: The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 6, 2012
    Assignee: Soitec
    Inventors: Carlos Mazure, Richard Ferrant
  • Patent number: 8107644
    Abstract: An amplifier integrated circuit element or J-FET is used for impedance conversion and amplification of ECM. The amplifier integrated circuit element has advantages of allowing an appropriate gain to be set by adjusting a circuit constant, and of producing a higher gain than the J-FET; but also has a problem of having a complicated circuit configuration and requiring high costs. Using only the J-FET has also problems of outputting a voltage insufficiently amplified and producing a low gain. Against this background, provided is a discrete element in which: a J-FET and a bipolar transistor are integrated on one chip; a source region of the J-FET is connected to a base region of the bipolar transistor; and a drain region of the J-FET is connected to a collector region of the bipolar transistor. Accordingly, an ECM amplifying element with high input impedance and low output impedance can be achieved.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: January 31, 2012
    Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLC
    Inventor: Eio Onodera
  • Patent number: 8072007
    Abstract: A backside-illuminated imaging device is provided and includes: a plurality of charge accumulating areas in the semiconductor substrate which accumulate the electric charges; and a plurality of filters above a backside surface of the semiconductor substrate corresponding to the respective charge accumulating areas. The plurality of filters includes different color filters which transmit different color components of the light from one another and luminance filters each having a spectral characteristic correlated with a luminance component of the light, the plurality of charge accumulating areas includes first charge accumulating areas corresponding to the respective color filters, and second charge accumulating areas corresponding to the respective luminance filters, and the second charge accumulating areas includes a third charge accumulating area having a size larger than those of the first accumulating areas.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: December 6, 2011
    Assignee: Fujifilm Corporation
    Inventor: Masaaki Koshiba
  • Patent number: 8053843
    Abstract: A semiconductor device for ESD protection includes a semiconductor substrate of a first conductivity type and a well region of a second conductivity type formed within the substrate. The well region is characterized by a first depth. The device includes an MOS transistor, a first bipolar transistor, and a second bipolar transistor. The MOS transistor includes a first lightly doped drain (LDD) region of a second depth within the well region, and a drain region and an emitter region within in the first LDD region. The emitter region is characterized by a second conductivity type. The first bipolar transistor is associated with the emitter region, the first LDD region, and the well region, and is characterized by a first trigger voltage. The second bipolar transistor is associated with the first LDD region, the well region, and the substrate, and is characterized by a second trigger voltage.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Chi Kang Liu, Ta Lee Yu, Quan Li
  • Patent number: 8049223
    Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.
    Type: Grant
    Filed: May 25, 2008
    Date of Patent: November 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Haruka Shimizu, Hidekatsu Onose
  • Patent number: 8039879
    Abstract: A semiconductor has an IGBT active section and a control circuit section for detecting an IGBT abnormal state. A collector region is formed on the back surface side (i.e., on the IGBT collector side) in a selective manner, namely right under the IGBT active section.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: October 18, 2011
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 8026146
    Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 27, 2011
    Assignee: NXP B.V.
    Inventors: Johannes J. T. M. Donkers, Sebastien Nuttinck, Guillaume L. R. Boccardi, Francois Neuilly
  • Patent number: 8018006
    Abstract: A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, an emitter region formed in the base, a buried collector in the thin semiconductor layer to contact the insulating layer, a collector contacting the buried collector, and emitter, collector and base contacts. The active transistor area is configured to operate at an emitter current at least in the order of mA (milli-ampere). An isolation trench extends through the semiconductor layer to the insulating layer and surrounds the active transistor area with a distance in the order of ?m (micron) from the active transistor area and with a space area of more than 50 ?m2 between the active transistor area and the isolation trench.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 13, 2011
    Assignees: Hitachi ULSI Systems Co., Ltd., Hitachi, Ltd.
    Inventors: Mitsuru Arai, Shinichiro Wada, Hideaki Nonami
  • Patent number: 8017974
    Abstract: A semiconductor device having the present high withstand voltage power device IGBT has at a back surface a p collector layer with boron injected in an amount of approximately 3×1013/cm2 with an energy of approximately 50 KeV to a depth of approximately 0.5 ?m, and an n+ buffer layer with phosphorus injected in an amount of approximately 3×1012/cm2 with an energy of 120 KeV to a depth of approximately 20 ?m. To control lifetime, a semiconductor substrate is exposed to protons at the back surface. Optimally, it is exposed to protons at a dose of approximately 1×1011/cm2 to a depth of approximately 32 ?m as measured from the back surface. Thus snapback phenomenon can be eliminated and an improved low saturation voltage (Vce (sat))-offset voltage (Eoff) tradeoff can be achieved.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: September 13, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Yoshiaki Hisamoto
  • Patent number: 8014412
    Abstract: A power supply system for providing power to a powered device over a communication link includes a power supply device capable of supporting an AC disconnect-detect function. The power supply device has a controller, an output port coupled to the communication link, and a bipolar junction transistor (BJT) controlled by the controller to provide power to the output port. The BJT may be turned off to present a high impedance required to support the AC disconnect-detection function.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: September 6, 2011
    Assignee: Linear Technology Corporation
    Inventor: Jacob Herbold
  • Patent number: 8008731
    Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: August 30, 2011
    Assignee: Acco
    Inventor: Denis Masliah