Junction Field Effect Transistor In Integrated Circuit Patents (Class 257/272)
  • Patent number: 10062710
    Abstract: Integrated circuits and methods of producing the same are provided herein. In accordance with an exemplary embodiment, an integrated circuit includes an SOI substrate with an active layer overlying a buried insulator layer that in turn overlies a handle layer. A source is defined within the active layer, and a gate well is also defined within the active layer. A first ultra shallow trench isolation extends into the active layer, where a first portion of the active layer is positioned between the first ultra shallow trench isolation and the buried insulator layer. The first ultra shallow trench isolation is positioned between the source and the gate well.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Guan Huei See, Rui Tze Toh, Shaoqiang Zhang, Purakh Raj Verma
  • Patent number: 9893057
    Abstract: A monolithically integrated semiconductor switch, particularly a circuit breaker, has regenerative turn-off behavior. The semiconductor switch has two monolithically integrated field effect transistors, for example a p-JFET and a n-JFET. The source electrodes of both JFETs and the well region of the n-JFET are short circuited. In addition, the gate electrodes of both JFETs and the drain electrode of the p-JFET are short-circuited via the cathode. In contrast, the well region of the p-JFET is short-circuited to the anode. In this way, a monolithically integrated semiconductor switch is created which turns off automatically when a certain anode voltage level or a certain anode current level is exceeded. The threshold values for the anode voltage and the anode current can be set by appropriate dimensioning of the elements. In this way, it is possible to achieve blocking strengths of up to 200 kV with fast response behavior.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: February 13, 2018
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Andreas Huerner, Tobias Erlbacher
  • Patent number: 9893209
    Abstract: A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: February 13, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Hideaki Tsuchiko
  • Patent number: 9673340
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack over the semiconductor substrate. The gate stack includes a first insulating layer, a first layer, a second layer, a second insulating layer, and a gate electrode. The first insulating layer separates the semiconductor substrate from the first layer. The second layer is between the first layer and the second insulating layer. The gate electrode is over the second insulating layer. There is a P-N junction between the first layer and the second layer. The semiconductor device structure includes a first doped region and a second doped region in the semiconductor substrate. The first layer, the first doped region, and the second doped region have a first type conductivity, which is opposite to a second type conductivity of the second layer.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Chen Huang, Kuang-Hsin Chen, Yung-Hsien Wu, Wen-Chao Shen
  • Patent number: 9552997
    Abstract: Methods of forming a p-channel MOS device in silicon carbide include forming an n-type well in a silicon carbide layer, and implanting p-type dopant ions to form a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region. A threshold adjustment region is formed in the channel region. The implanted ions are annealed in an inert atmosphere at a temperature greater than 1650° C. A gate oxide layer is formed on the channel region, and a gate is formed on the gate oxide layer. A silicon carbide-based transistor includes a silicon carbide layer, an n-type well in the silicon carbide layer, and a p-type region in the n-type well at a surface of the silicon carbide layer and at least partially defining a channel region in the n-type well adjacent the p-type region.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: January 24, 2017
    Assignee: Cree, Inc.
    Inventors: Mrinal Kanti Das, Qingchun Zhang, Sei-Hyung Ryu
  • Patent number: 9460926
    Abstract: A power integrated circuit includes a junction field effect transistor (JFET) device formed in a first portion of a semiconductor layer with a gate region being formed using a first body region, and a double-diffused metal-oxide-semiconductor (LDMOS) transistor formed in a second portion of the semiconductor layer with a channel being formed in a second body region. The power integrated circuit includes a first deep diffusion region formed under the first body region and in electrical contact with the first body region where the first deep diffusion region together with the firs body region establish a pinch off voltage of the JFET device; and a second deep diffusion region formed under the second body region and in electrical contact with the second body region where the second deep diffusion region forms a reduced surface field (RESURF) structure in the LDMOS transistor.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 4, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 9153958
    Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: October 6, 2015
    Assignee: NXP B.V.
    Inventors: Gijs de Raad, Paul Cappon, Albert Jan Huitsing
  • Patent number: 9054704
    Abstract: A method, system, and apparatus for driving a Silicon Carbide (SiC) Junction Field Effect Transistor (JFET) are provided. A boosting capacitor is used in combination with two drivers to efficiently provide a boosting current to the SiC JFET and then a holding current to the SiC JFET. The boosting capacitor, upon discharge, creates the boosting current and once discharged the holding current is provided by one of the first and second drivers.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: June 9, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Yunfeng Liang
  • Patent number: 9024365
    Abstract: A high voltage junction field effect transistor and a manufacturing method thereof are provided. The high voltage junction field effect transistor includes a base, a drain, a source and a P type top layer. The drain and the source are disposed above the base. A channel is formed between the source and the drain. The P type top layer is disposed above the channel.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 5, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Li-Fan Chen, Wing-Chor Chan, Jeng Gong
  • Patent number: 8975670
    Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.
    Type: Grant
    Filed: July 22, 2012
    Date of Patent: March 10, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Publication number: 20150043116
    Abstract: A high voltage semiconductor switch includes a first field-effect transistor having a source, a drain and a gate, and being adapted for switching a voltage at a rated high-voltage level, the first field-effect transistor being a normally-off enhancement-mode transistor, a second field-effect transistor having a source, a drain and a gate, connected in series to the first field-effect transistor, the second field-effect transistor being a normally-on depletion-mode transistor; and a control unit connected to the drain of the first field-effect transistor and to the gate of the second field-effect transistor and being operable for blocking the second field-effect transistor if a drain-source voltage across the first field-effect transistor exceeds the rated high-voltage level.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: Infineon Technologies Austria AG
    Inventors: Joachim Weyers, Franz Hirler, Anton Mauder
  • Publication number: 20150035014
    Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.
    Type: Application
    Filed: August 5, 2013
    Publication date: February 5, 2015
    Applicant: Raytheon Company
    Inventors: John J. Drab, Justin Gordon Adams Wehner, Christian M. Boemler
  • Patent number: 8928043
    Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 6, 2015
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Joseph Urienza
  • Patent number: 8921903
    Abstract: On a p? epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p? epitaxial layer a voltage that causes a reverse biased state of the p? epitaxial layer and the n-type epitaxial layer in an OFF operation.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: December 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Yasuo Namikawa
  • Patent number: 8901625
    Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a PIN gate stack. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8895980
    Abstract: The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: November 25, 2014
    Assignee: Peking University
    Inventors: Ru Huang, Zhan Zhan, Qianqian Huang, Yangyuan Wang
  • Patent number: 8866194
    Abstract: A semiconductor device (npn bipolar transistor) includes an n-type collector layer, a base layer constituted by a p+ diffusion layer, a SiGe layer and a p-type silicon film, an n-type emitter layer and a charge transport prevention film formed between the n-type collector layer and the n-type emitter layer and having an effect as a potential barrier with respect to either electrons or holes.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 21, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shinya Naito, Hideaki Fujiwara, Toru Dan
  • Patent number: 8866201
    Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Vijay Parthasarathy
  • Patent number: 8860098
    Abstract: The present disclosure describes structures and processes to produce high voltage JFETs in wide-bandgap materials, most particularly in Silicon Carbide. The present disclosure also provides for products produced by the methods of the present disclosure and for apparatuses used to perform the methods of the present disclosure.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: October 14, 2014
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Peter Alexandrov
  • Patent number: 8847401
    Abstract: Disclosed is a semiconductor structure incorporating a contact sidewall spacer with a self-aligned airgap and a method of forming the semiconductor structure. The structure comprises a semiconductor device (e.g., a two-terminal device, such as a PN junction diode or Schottky diode, or a three-terminal device, such as a field effect transistor (FET), a bipolar junction transistor (BJT), etc.) and a dielectric layer that covers the semiconductor device. A contact extends vertically through the dielectric layer to a terminal of the semiconductor device (e.g., in the case of a FET, to a source/drain region of the FET). A contact sidewall spacer is positioned on the contact sidewall and incorporates an airgap. Since air has a lower dielectric constant than other typically used dielectric spacer or interlayer dielectric materials, the contact size can be increased for reduced parasitic resistance while minimizing corresponding increases in parasitic capacitance or the probability of shorts.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Xin Wang, Yanfeng Wang
  • Patent number: 8847290
    Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: September 30, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeru Kusunoki, Shinichi Ishizawa
  • Patent number: 8835339
    Abstract: A framework for developing high quality factor (Q) material for electronic applications in the radio frequency range is provided. In one implementation, ceramic materials having a tungsten bronze crystal structure is modified by substituting one or more elements at one or more lattice sites on the crystal structure. The substitute elements are selected based on the ionic radius and other factors. In other implementations, the modified ceramic material is prepared in combination with compositions such as rutile or a perovskite to form a orthorhombic hybrid of perovskite and tetragonal tungsten bronze.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: September 16, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventor: Michael D. Hill
  • Patent number: 8823130
    Abstract: A silicon epitaxial wafer having a silicon epitaxial layer grown by vapor phase epitaxy on a main surface of a silicon single crystal substrate, wherein the main surface of the silicon single crystal substrate is tilted with respect to a [100] axis at an angle ? in a [011] direction or a [0-1-1] direction from a (100) plane and at an angle ? in a [01-1] direction or a [0-11] direction from the (100) plane, the angle ? and the angle ? are less than ten minutes, and a dopant concentration of the silicon epitaxial layer is equal to or more than 1×1019/cm3. Even when an epitaxial layer having a dopant concentration of 1×1019/cm3 or more is formed on the main surface of the silicon single crystal substrate, stripe-shaped surface irregularities on the epitaxial layer are inhibited.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 2, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masahiro Kato, Satoshi Oka, Norihiro Kobayashi, Tohru Ishizuka, Nobuhiko Noto
  • Patent number: 8816388
    Abstract: Disclosed is a semiconductor device including: a semiconductor substrate; a field effect transistor formed on the semiconductor substrate; and a diode forming area adjacent to a forming area of the field effect transistor, wherein the diode forming area is insulated from the forming area of the field effect transistor on the semiconductor substrate, the diode forming area includes an anode electrode and a cathode electrode arranged side by side in a multi-finger shape, and the anode electrode and the cathode electrode are formed in a direction different from directions of a gate electrode, a source electrode, and a drain electrode of the field effect transistor arranged side by side in a multi-finger shape.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Publication number: 20140197467
    Abstract: A JFET structure includes a first JFET having a first terminal and a second JFET neighboring with the first JFET. Both JFETs commonly share the first terminal and the first terminal is between the gate of each JFET. The JFET also provides at least one tuning knob to adjust the pinch-off voltage and a tuning knob to adjust the breakdown voltage of the JFET structure. Moreover, the JFET has a buried layer as another tuning knob to adjust the pinch-off voltage of the JFET structure.
    Type: Application
    Filed: January 14, 2013
    Publication date: July 17, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: WEI-HSUN HSU, SHUO-LUN TU, SHIH-CHIN LIEN, SHYI-YUAN WU
  • Publication number: 20140167060
    Abstract: An electronic power component including a normally on high-voltage transistor and a normally off low-voltage transistor. The normally on transistor and the normally off transistor are coupled in cascode configuration and are housed in a single package. The normally off transistor is of the bottom-source type.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonello Santangelo, Marcello Francesco Salvatore Giuffrida
  • Patent number: 8735950
    Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: May 27, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 8723234
    Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a field-effect transistor formed on the semiconductor substrate; and a diode forming area which is adjacent to a forming area of the field-effect transistor, wherein the diode forming area is insulated from the forming area of the transistor on the semiconductor substrate, and includes a first diode electrode in which a gate electrode of the field-effect transistor is placed in Schottky barrier junction and/or ohmic contact with the semiconductor substrate through a bus wiring or a pad; and a second diode electrode in which a source electrode of the field-effect transistor is placed in ohmic contact and/or Schottky barrier junction with the semiconductor substrate through a bus interconnection or a pad to form a diode between the gate electrode and the source electrode.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiharu Takada, Kentaro Ikeda
  • Publication number: 20140104888
    Abstract: A semiconductor device having a JFET and diode, includes a substrate, a second well region, and a second doped region that are of a first conductivity type. The JFET also includes a first well region, a first doped region, and a shared region that are of the second conductivity type. The second well region is disposed in the substrate adjacent to the first well region. A source of the JFET includes the first doped region disposed in the first well region. An anode of the diode includes the second doped region disposed in the second well region. Both a drain of the JFET and a cathode of the diode include the shared region disposed in the first well region. A diode current flows along a first lateral axis of the device while a JFET current flows along a second lateral axis of the device.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: POWER INTEGRATIONS, INC.
    Inventor: Sujit Banerjee
  • Patent number: 8685812
    Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Min-Hwa Chi
  • Patent number: 8680582
    Abstract: Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: March 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jacob Robert Anderson, William Jones
  • Patent number: 8674455
    Abstract: A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 18, 2014
    Inventors: Kensuke Okonogi, Kazuhiro Nojima, Kiyonori Oyu
  • Publication number: 20140061731
    Abstract: A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Patent number: 8643065
    Abstract: A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: February 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Hideto Tamaso, Shin Harada, Yasuo Namikawa
  • Patent number: 8637908
    Abstract: A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Su Chen Fan, David V. Horak, Sivananda K. Kanakasabapathy
  • Publication number: 20140015591
    Abstract: Providing gate protection to a group III-semiconductor device by delivering gate overdrive immunity is described herein. The gate protection can be achieved by embedding a gate-voltage-controlling second transistor to the gate electrode of a first transistor. In other words, a first gate electrode of the first semiconductor device is in series with a second source electrode of the second semiconductor device, and a second gate electrode of the second semiconductor device is connected to the second source electrode and the first gate electrode.
    Type: Application
    Filed: July 8, 2013
    Publication date: January 16, 2014
    Inventors: Jing CHEN, Man Ho KWAN
  • Patent number: 8624302
    Abstract: A method of fabricating an LFCC device includes forming a first trench in a substrate that extends vertically from an upper surface to a depth within the substrate, the first trench having first sidewalls, a first bottom, and a pattern formed on the first sidewalls near the first bottom of the trench, and forming an oxide layer on the first sidewalls and first bottom of the first trench that leaves a second trench located within the first trench and is separated from the first trench by the oxide layer. The second trench has second sidewalls that are substantially vertical without showing the pattern and a second bottom that is substantially flat. The pattern compensates for the difference in oxidation rates between the bottom of the first trench and the first sidewalls. The LFCC structure includes a first trench with the pattern.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: January 7, 2014
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Matthew A. Ring, Henry G. Prosack, Jr.
  • Patent number: 8610183
    Abstract: An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: December 17, 2013
    Assignee: Texas Instruments Incorporated
    Inventor: Akram A. Salman
  • Publication number: 20130328619
    Abstract: An integrated circuit in which a voltage divider circuit is integrated comprises a first resistor, second resistor, control portion, switch, and switching portion. The first resistor and second resistor form a resistive voltage divider element for dividing a voltage obtained by rectifying an alternating-current voltage, or a direct-current voltage, supplied to a control portion. The switch is provided in series with the resistive voltage divider element, and passes or cuts off current passing through the resistive voltage divider element. The switching portion switches the switch so as to pass current during driving of the control portion, and cut off current during standby of the control portion.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Taichi KARINO, Akio KITAMURA, Takato SUGAWARA
  • Patent number: 8598637
    Abstract: In one embodiment, a junction field effect transistor having a substrate, wherein formed on the substrate is a graded n-doped region having a high doping concentration in an inner region and a low doping concentration in an outer region, with a p-doped buried region adjacent to the graded n-doped region near the outer region, and a spiral resistor connected to the graded n-doped region at its inner region and at its outer region. An ohmic contact at the inner region provides the drain, an ohmic contact at the outer region provides the source, and an ohmic contact at the substrate provides the gate.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: December 3, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Michael R. Hsing, Martin E. Garnett, Ognjen Milic
  • Patent number: 8587059
    Abstract: A semiconductor arrangement includes a MOSFET having a source region, a drift region and a drain region of a first conductivity type, a body region of a second conductivity type arranged between the source region and the drift region, a gate electrode arranged adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a source electrode contacting the source region and the body region. The semiconductor arrangement further includes a normally-off JFET having a channel region of the first conductivity type that is coupled between the source electrode and the drift region and extends adjacent the body region so that a p-n junction is formed between the body region and the channel region.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Hans-Joachim Schulze
  • Patent number: 8569842
    Abstract: A semiconductor device arrangement includes a first semiconductor device having a load path, and a number of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor. Each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors. One of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: October 29, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Rolf Weis, Franz Hirler, Matthias Stecher, Armin Willmeroth, Gerald Deboy, Martin Feldtkeller
  • Patent number: 8557653
    Abstract: A method of manufacturing a junction-field-effect-transistor (JFET) device, the method includes the steps of providing a substrate of a first-type impurity; forming a first well region of a second-type impurity in the substrate; forming a second well region and a third well region of the first-type impurity separated from each other in the first well region; forming a fourth well region of the first-type impurity between the second well region and the third well region; forming a first diffused region of the second-type impurity between the second well region and the fourth well region; forming a second diffused region of the second-type impurity between the third well region and the fourth well region; forming a pair of first doped regions of the second-type impurity in the first well region, and a pair of second doped regions of the first-type impurity in the second well region and the third well region respectively; forming a third doped region of the second-type impurity in the first well region between t
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 15, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Min Hu, Chung Yu Hung, Wing Chor Chan, Jeng Gong
  • Publication number: 20130248947
    Abstract: In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.
    Type: Application
    Filed: March 22, 2012
    Publication date: September 26, 2013
    Inventors: Sunglyong Kim, Jongjib Kim
  • Patent number: 8513675
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 20, 2013
    Assignee: Power Integrations, Inc.
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Publication number: 20130193491
    Abstract: An integrated circuit containing a field controlled diode which includes a p-type channel region between an upper gate and a lower n-type depletion gate, a p-type anode in a p-type anode well abutting the channel region, and an n-type cathode in a p-type anode well abutting the channel region opposite from the anode well. An n-type lower gate link connects the lower gate to the surface of the substrate. A surface control element is located at the surface of the channel region between the cathode and the upper gate. A process of forming the integrated circuit containing the field controlled diode is described.
    Type: Application
    Filed: August 1, 2012
    Publication date: August 1, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Akram A. Salman
  • Patent number: 8481410
    Abstract: Disclosed herein are various methods for better height control of the finFET patterned fins. In one example, this invention begins by depositing or growing an oxide material, for example, silicon dioxide. This oxide material is then patterned and etched to open windows or trenches to the substrate where fins will be grown. If a common channel material is desired, it is epitaxially grown in the windows. Then, some windows are covered and one pole of fins (for example nFET) are epitaxially grown in the exposed windows. The previously masked windows are opened and the newly formed fins are masked. The alternate channel material is then grown. The masked fins are then un-masked and the oxide is recessed to allow the fins to protrude from the oxide. This invention also allows for different channel materials for NMOS and PMOS.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 9, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Nicholas LiCausi, Jeremy Wahl
  • Patent number: 8481372
    Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: July 9, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 8455948
    Abstract: A transistor arrangement includes a first transistor having a drift region and a number of second transistors, each having a source region, a drain region and a gate electrode. The second transistors are coupled in series to form a series circuit that is coupled in parallel with the drift region of the first transistor.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: June 4, 2013
    Assignee: Infineon Technologies Austria AG
    Inventor: Rolf Weis
  • Patent number: 8436399
    Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Akiyoshi Tamura