Abstract: Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

Abstract: Semiconductor devices including a first region having a first three Nitride (III-N) layer and a second III-N layer, the second III-N layer is over the first III-N. The second III-N layer has spontaneous polarization less than the first III-N layer, such that a two-dimensional hole gas (2-DHG) will be formed at a junction of the first III-N layer to the second III-N layer. An Anode forms an ohmic contact to the 2-DHG. A second region includes a third III-N layer and a forth III-N layer, such that the fourth III-N layer is over the third III-N. The forth III-N layer has spontaneous polarization greater than the third III-N layer, such that two-dimensional electron gas (2-DEG) will be formed at a junction of the third III-N layer to the forth III-N layer. A Cathode forms an ohmic contact to the 2-DEG. The first and second regions are connected at an interface.

Abstract: The present disclosure relates to a filling body for reducing a volume of a pressure measurement chamber, which is to be filled with a pressure transmitting fluid, surrounding a pressure sensor. The filling body includes a recess for receiving the pressure sensor and has a free-standing base projecting into the recess on which the pressure sensor can be mounted. A filling body base supporting the filling body is provided on a side of the filling body facing away from the recess. The filling body can be mounted in an application location in such a way that the filling body base supports the otherwise free-standing filling body. The filling body base has a base surface that is smaller than a base surface of a filling body region that is adjacent to the filling body base and surrounding the recess.

Abstract: A decoupling capacitor includes a first p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library, a first n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in the standard cell library, a second PMOS transistor connected between the first NMOS transistor and the power rail, and a second NMOS transistor connected between the first PMOS transistor and the ground rail, wherein a gate of the second PMOS transistor is connected to a gate of the second NMOS transistor.

Abstract: A method of fabricating an SRAM semiconductor device includes forming first and second FinFETs on an upper surface of a bulk substrate. The first FinFET includes a first source/drain region containing first dopants, and the second FinFET includes a second source/drain region containing second dopants. The method further includes selectively controlling a temperature of the second FinFET with respect to a temperature of the first FinFET during an anneal process to activate the first and second dopants such that the second source/drain region is formed having a different electrical resistance with respect to the first source/drain region.

Abstract: Embodiments of the present disclosure provide a circuit structure including: a switching transistor including a gate terminal, a back-gate terminal, a source terminal, and a drain terminal; a biasing node coupled to the back-gate terminal of the switching transistor, the biasing node being alternately selectable between an on state and an off state; a first capacitor source-coupled to the switching transistor; a second capacitor drain-coupled to the switching capacitor; and a first enabling node source-coupled to the switching transistor, the first enabling node being alternately selectable between an on state and an off state.

Abstract: A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.

Abstract: A method of fabricating a semiconductor device includes forming a dummy gate on a substrate, forming a dummy gate mask on the dummy gate, forming a gate spacer on the substrate, the gate spacer covering at least one sidewall surface of the dummy gate and the dummy gate mask, forming a recess on at least one side of the dummy gate by etching the substrate, and forming an epitaxial layer in the recess using an epitaxial growth process. The forming of the dummy gate mask includes forming an oxide layer and a dummy gate mask layer on the dummy gate.

Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.

Abstract: An output circuit adapted for an integrated circuit is provided. The output circuit includes a driver, a pre-driver and a buffer circuit. The driver is electrically connected to two output nodes outside the integrated circuit to output signals. The pre-driver controls the driver, and includes a load and an input transistor connected in series. Between the load and the input transistor is a connection node for controlling the driver. The buffer circuit controls the load and the input transistor according to an internal signal. Before turning off the input transistor, the buffer circuit pre charges the connection node through the load.

Abstract: The methods may include forming a first material layer on a substrate, increasing electric resistance of the first material layer, and forming a source pattern and a drain pattern, which are spaced apart from each other, on the first material layer, a band gap of the source and drain patterns greater than a band gap of a first material layer.

Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells (105-109, 113-115) on a first flash cell substrate area (111) which are encapsulated in one or more planar dielectric layers (116) prior to forming an elevated substrate (117) on a second CMOS transistor area (112) on which high-k metal gate electrodes (119-120, 122-126, 132, 134) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Abstract: A semiconductor device, including: a semiconductor substrate with a first layer including first transistors; a shield layer overlaying the first layer; a second layer overlaying the shield layer, the second layer including second transistors; wherein the shield layer is a mostly continuous layer with a plurality of regions for connections between the first transistors and the second transistors, and where the second transistors include monocrystalline regions.

Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: A semiconductor device with an n-type transistor and a p-type transistor having an active region is provided. The active region further includes two adjacent gate structures. A portion of a dielectric layer between the two adjacent gate structures is selectively removed to form a contact opening having a bottom and sidewalls over the active region. A bilayer liner is selectively provided within the contact opening in the n-type transistor and a monolayer liner is provided within the contact opening in the p-type transistor. The contact opening in the n-type transistor and p-type transistor is filled with contact material. The monolayer liner is treated to form a silicide lacking nickel in the p-type transistor.

Abstract: A semiconductor device comprises a semiconductor substrate; a channel layer of at least a first III-V semiconductor compound above the semiconductor substrate; a gate stack structure above a first portion of the channel layer; a source region and a drain region comprising at least a second III-V semiconductor compound above a second portion of the channel layer; and a first metal contact structure above the S/D regions comprising a first metallic contact layer contacting the S/D regions. The first metallic contact layer comprises at least one metal-III-V semiconductor compound.

Abstract: An IGFET device includes: —a semiconductor body having a major surface, —a source region of first conductivity type abutting the surface, —a drain region of the first conductivity-type abutting the surface and spaced from the source region with a channel therefrom, —an active gate overlying the channel and insulated from the channel by a first dielectric material forming the gate oxide of the IGFET device, —a dummy gate positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

Abstract: A SiC semiconductor device includes: a SiC substrate made of intrinsic SiC having semi-insulating property; first and second conductive type SiC layers disposed in the substrate; an insulation separation layer made of intrinsic SiC for isolating the first conductive type SiC layer from the second conductive type SiC layer; first and second conductive type channel JFETs disposed in the first and second conductive type SiC layers, respectively. The first and second conductive type channel JFETs provide a complementary junction field effect transistor. Since an electric element is formed on a flat surface, a manufacturing method is simplified. Further, noise propagation at high frequency and current leakage at high temperature are restricted.

Abstract: The present invention relates to fabrication of enhancement mode and depletion mode High Electron Mobility Field Effect Transistors on the same die separated by as little as 10 nm. The fabrication method uses selective decomposition and selective regrowth of the Barrier layer and the Cap layer to engineer the bandgap of a region on a die to form an enhancement mode region. In these regions zero or more devices may be fabricated.

Abstract: In one aspect of the present invention, a field effect transistor (FET) device includes a first FET including a dielectric layer disposed on a substrate, a first portion of a first metal layer disposed on the dielectric layer, and a second metal layer disposed on the first metal layer, a second FET including a second portion of the first metal layer disposed on the dielectric layer, and a boundary region separating the first FET from the second FET.

Abstract: Provided is a method of fabricating a semiconductor device. Gate patterns are formed on a substrate including an NMOS transistor region and a PMOS transistor region. A spacer structure is formed on sidewalls of the gate patterns. The substrate in the PMOS transistor region is etched using the gate patterns and the spacer structure as etching masks, and thereby a recessed region is formed. A compressive stress pattern is formed in the recessed region, and a sidewall of the compressive stress pattern protrudes upwardly from an upper surface of the substrate. A mask oxide layer is formed on a sidewall of the spacer structure. The mask oxide layer is formed to cover a portion of the sidewall of the compressive stress pattern that protrudes upwardly from the upper surface of the substrate.

Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.

Abstract: A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Abstract: A lateral stack-type super junction power semiconductor device includes a semiconductor substrate; an epitaxial stack structure on the semiconductor substrate, having a first epitaxial layer and a second epitaxial layer; a drain structure embedded in the epitaxial stack structure and extending along a first direction; a plurality of gate structures embedded in the epitaxial stack structure and arranged in a segmental manner along the first direction; a source structure between the plurality of gate structures; and an ion well encompassing the source structure.

Abstract: An object is to provide an n-channel transistor and a p-channel transistor having a preferred structure using an oxide semiconductor. A first source or drain electrode which is electrically connected to a first oxide semiconductor layer and is formed using a stacked-layer structure including a first conductive layer containing a first material and a second conductive layer containing a second material, and a second source or drain electrode which is electrically connected to a second oxide semiconductor layer and is formed using a stacked-layer structure including a third conductive layer containing the first material and a fourth conductive layer containing the second material are included. The first oxide semiconductor layer is in contact with the first conductive layer of the first source or drain electrode, and the second oxide semiconductor layer is in contact with the third and the fourth conductive layers of the second source or drain electrode.

Abstract: A method of manufacturing a semiconductor device begins by fabricating an n-type metal oxide semiconductor (NMOS) transistor structure on a semiconductor wafer. The method continues by forming an optically reflective layer overlying the NMOS transistor structure, forming a layer of tensile stress inducing material overlying the optically reflective layer, and curing the layer of tensile stress inducing material by applying ultraviolet radiation. Some of the ultraviolet radiation directly radiates the layer of tensile stress inducing material and some of the ultraviolet radiation radiates the layer of tensile stress inducing material by reflecting from the optically reflective layer.

Abstract: A vertical junction field-effect transistor in a CMOS base-technology. The vertical junction field-effect transistor includes a semiconductor substrate having a source region and a drain region, a main-channel region formed between the source region and the drain region, a well region formed on the main-channel region between the source region and the drain region, vertical pinch-off regions formed at both source and drain ends or only on the source-end of the well region on the main-channel region in the source region and the drain region respectively, a source contact on the vertical pinch-off region in the source region, a drain contact on the vertical pinch-off region in the drain region, a gate contact on the well region between the source contact and the drain contact and shallow trench isolations formed on the well region.

Abstract: A method includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface spaced from the first surface by less than the step height, forming a gate structure, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface spaced from the first surface by less than the step height, a gate structure, and a contact engaging the gate structure over the recess.

Abstract: In one embodiment of the present invention, a field effect transistor device is provided. The field effect transistor device comprises an active area, including a first semiconductor material of a first conductivity type. A channel region is included within the active area. A gate region overlays the channel region, and the first source/drain region and the second source/drain region are embedded in the active area and spaced from each other by the channel region. The first source/drain region and the second source/drain region each include a second semiconductor material of a second conductivity type opposite of the first conductivity type. A well-tap region is embedded in the active area and spaced from the first source/drain region by the channel region and the second source/drain region. The well-tap region includes the second semiconductor material of the first conductivity type. The first source/drain region and the second source/drain region and the well-tap region are epitaxial deposits.

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract: A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack.

Abstract: A method for producing VDMOS transistors in which a specific layer arrangement and a specific method sequence allow setting up an improved gate contact when simultaneously producing source and gate contacts using a single contact hole mask (photo mask).

Abstract: Methods for removing a photoresist from a metal-comprising material are provided. In accordance with an exemplary embodiment of the present invention, the method comprises applying to the photoresist a substantially non-aqueous-based solvent having a pH no less than about 9 or no pH and subsequently applying to the metal-comprising material an aqueous-based fluid having a pH no less than about 9.

Abstract: By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating layer of an SOI transistor. Furthermore, the spacer structure maintains a significant amount of a strained semiconductor alloy with its original thickness, thereby providing an efficient strain-inducing mechanism. By using sophisticated anneal techniques, undue lateral diffusion may be avoided, thereby allowing a reduction of the lateral width of the respective spacers and thus a reduction of the length of the transistor devices. Hence, enhanced charge carrier mobility in combination with reduced junction capacitance may be accomplished on the basis of reduced lateral dimensions.

Abstract: A CMOS device with transistors having different gate dielectric materials and a method of manufacture thereof. A CMOS device is formed on a workpiece having a first region and a second region. A first gate dielectric material is deposited over the second region. A first gate material is deposited over the first gate dielectric material. A second gate dielectric material comprising a different material than the first gate dielectric material is deposited over the first region of the workpiece. A second gate material is deposited over the second gate dielectric material. The first gate material, the first gate dielectric material, the second gate material, and the second gate dielectric material are then patterned to form a CMOS device having a symmetric Vt for the PMOS and NMOS FETs.

Abstract: A molecular device includes a gold electrode, cytochrome c552 or a derivative or variant thereof immobilized on the gold electrode, and an electron transfer protein coupled to the cytochrome c552 or the derivative or variant thereof. Electrons or holes, or both, are transferred through the electron transfer protein by transition of electrons between molecular orbitals of the electron transfer protein.

Abstract: Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.

Abstract: The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

Abstract: The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS transistor that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion is shorter than the length of a protruding part of a gate electrode of the n-type MIS transistor that protrudes from the n-type MIS transistor's active region toward the n-type MIS transistor's substrate contact portion. Alternatively, a part of the p-type MIS transistor's substrate contact portion that is located opposite the p-type MIS transistor's gate electrode has a lower impurity concentration than the other part thereof.

Abstract: An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the source region with a channel (5) therefrom, —an active gate (8) overlying the channel and insulated from the channel by a first dielectric material (9) forming the gate oxide of the IGFET device, —a dummy gate (10) positioned between the active gate and the drain and insulated from the active gate by a second dielectric material so that a capacitance is formed between the active gate and the dummy gate, and insulated from the drain region by the gate oxide, wherein the active gate and the dummy gate are forming the electrodes of the capacitance substantially perpendicular to the surface.

Abstract: A semiconductor device is the semiconductor device which includes more than one field effect transistor having a gate electrode to which an electrical interconnect wire is connected and a gate insulation film with a thickness of 6.0 nm or less and which comprises a first transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film, a second transistor group made up of a plurality of field effect transistors that are the same in thickness of gate insulation film with the thickness of gate insulation film being less than the thickness of the gate insulation film of the first transistor group, and a semiconductor substrate on which the first and second transistor groups are mounted together in a mixed manner, wherein an antenna ratio which is a ratio of the area of a wire to the gate area of a gate electrode is such that the maximum value of the second transistor group is greater than the maximum value of the first transistor group.