With Non-uniform Channel Thickness Or Width Patents (Class 257/286)
  • Patent number: 10770555
    Abstract: The present disclosure relates to a semiconductor device. The semiconductor device includes a gate structure disposed on a semiconductor substrate, a sidewall spacer disposed on sidewalls of the gate structure, a lightly-doped source/drain region formed in the semiconductor substrate on opposite sides of the gate structure, a source/drain region formed in the semiconductor substrate on opposite sides of the sidewall spacer, a halo implant region formed in the semiconductor substrate below the gate structure and adjacent to the lightly-doped source/drain region, and a counter-doping region formed in the semiconductor substrate below the gate structure and between the lightly-doped source/drain region and the halo implant region. The dopant concentration of the counter-doping region is lower than the dopant concentration of the halo implant region.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: September 8, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Hsuan Wang, Kan-Sen Chen, Sing-Lin Wu, Yung-Lung Chou, Yun-Chou Wei, Chia-Hao Lee, Chih-Cherng Liao
  • Patent number: 10741688
    Abstract: The present disclosure provides many different embodiments of an IC device. The IC device includes a gate stack disposed over a surface of a substrate and a spacer disposed along a sidewall of the gate stack. The spacer has a tapered edge that faces the surface of the substrate while tapering toward the gate stack. Therefore the tapered edge has an angle with respect to the surface of the substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shin-Jiun Kuang, Tsung-Hsing Yu, Yi-Ming Sheu
  • Patent number: 10403755
    Abstract: Related to is the technical field of display panels, and in particular to a thin film transistor and a method for manufacturing the same. The thin film transistor provided on a substrate includes a drain, a source, a gate, and an active layer. The drain and the source are in a comb-like shape and are connected with the active layer through a first via hole and a second via hole, respectively. Such arrangement enables a width of a channel formed between the drain and the source to be increased and a layout scale of the thin film transistor to be reduced at the same time, whereby space is saved. When used in a GOA circuit or other circuits, the thin film transistor is helpful to achievement of a narrow-bezel design of a display panel.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: September 3, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Mian Zeng, Shu Jhih Chen
  • Patent number: 10312153
    Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Ah-Young Cheon, Kwang-Yong Yang, Myungil Kang, Dohyoung Kim, YoonHae Kim
  • Patent number: 9941174
    Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungin Choi, Ah-Young Cheon, Kwang-Yong Yang, Myungil Kang, Dohyoung Kim, YoonHae Kim
  • Patent number: 9905646
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a recess in a source/drain region of a semiconductor substrate, wherein the semiconductor substrate is formed of a first semiconductor material. The method further includes epitaxially growing a second semiconductor material within the recess to form a S/D feature in the recess, and removing a portion of the S/D feature to form a v-shaped valley extending into the S/D feature.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsz-Mei Kwok, Ming-Hua Yu, Chii-Horng Li
  • Patent number: 9899527
    Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 20, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Raj Verma Purakh, Shaoqiang Zhang, Rui Tze Toh
  • Patent number: 9608050
    Abstract: An organic light emitting diode (OLED) display including: a substrate; a semiconductor layer disposed on the substrate and including a switching semiconductor layer and a driving semiconductor layer connected to the switching semiconductor layer; a first gate insulating layer disposed on the semiconductor layer; a switching gate electrode and a driving gate electrode disposed on the first gate insulating layer and respectively overlapping with the switching semiconductor layer and the driving semiconductor layer; a second gate insulating layer disposed on the switching gate electrode and the driving gate electrode; a driving voltage line configured to transmit a driving voltage and disposed on the second gate insulating layer; an interlayer insulating layer disposed on the driving voltage line and the second gate insulating layer; and a data line configured to transmit a data signal and disposed on the interlayer insulating layer.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 28, 2017
    Assignee: Samsung Display Co., Ltd
    Inventor: Min-Hyun Jin
  • Patent number: 9117783
    Abstract: An organic light emitting diode (OLED) display including: a substrate; a semiconductor layer disposed on the substrate and including a switching semiconductor layer and a driving semiconductor layer connected to the switching semiconductor layer; a first gate insulating layer disposed on the semiconductor layer; a switching gate electrode and a driving gate electrode disposed on the first gate insulating layer and respectively overlapping with the switching semiconductor layer and the driving semiconductor layer; a second gate insulating layer disposed on the switching gate electrode and the driving gate electrode; a driving voltage line configured to transmit a driving voltage and disposed on the second gate insulating layer; an interlayer insulating layer disposed on the driving voltage line and the second gate insulating layer; and a data line configured to transmit a data signal and disposed on the interlayer insulating layer.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: August 25, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: Min-Hyun Jin
  • Patent number: 9000526
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • Patent number: 8975671
    Abstract: A semiconductor component is provided with a semiconductor substrate, in the upper face of which an active region made of a material of a first conductivity type is introduced by ion implantation. A semiconducting channel region having a defined length and width is designed within the active region. Each of the ends of the channel region located in the longitudinal extension is followed by a contacting region made of a semiconductor material of a second conductivity type. The channel region is covered by an ion implantation masking material, which comprises transverse edges defining the length of the channel region and longitudinal edges defining the width of the channel region and which comprises an edge recess at each of the opposing transverse edges aligned with the longitudinal extension ends of the channel region, the contacting regions that adjoin the channel region extending all the way into said edge recess.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: March 10, 2015
    Assignee: ELMOS Semiconductor AG
    Inventor: Arnd Ten Have
  • Patent number: 8928044
    Abstract: A this film transistor is provided. The thin film transistor includes a semiconductor layer including a source region, a drain region, and a channel region, wherein the channel region is provided between the source region and the drain region; and a gate electrode overlapping with the channel region, wherein the channel region includes at least a portion of a channel width that is configured to at least one of continuously decrease and continuously increase in a lengthwise direction.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: January 6, 2015
    Assignee: Japan Display West Inc.
    Inventors: Yoshitaka Ozeki, Yasuhito Kuwahara, Shigetaka Toriyama, Hiroyuki Ikeda
  • Patent number: 8847332
    Abstract: A high voltage semiconductor device is provided. The device includes a semiconductor substrate having a high voltage well with a first conductivity type therein. A gate structure is disposed on the semiconductor substrate of the high voltage well. A source doped region and a drain doped region are in the high voltage well on both sides of the gate structure, respectively. A lightly doped region with the first conductivity type is between the source and drain doped regions and relatively near to the source doped region. The disclosure also presents a method for fabricating a high voltage semiconductor device.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 30, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wei-Chun Chou, Yi-Hung Chiu, Chu-Feng Chen, Cheng-Yi Hsieh, Chung-Ren Lao
  • Patent number: 8803247
    Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 12, 2014
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Patent number: 8710549
    Abstract: A SOI MOS device for eliminating floating body effects and self-heating effects are disclosed. The device includes a connective layer coupling the active gate channel to the Si substrate. The connective layer provides electrical and thermal passages during device operation, which could eliminate floating body effects and self-heating effects. An example of a MOS device having a SiGe connector between a Si active channel and a Si substrate is disclosed in detail and a manufacturing process is provided.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 29, 2014
    Assignee: Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Science
    Inventors: Xiaolu Huang, Jing Chen, Xi Wang, Deyuan Xiao
  • Patent number: 8669617
    Abstract: Provided are devices having at least three and at least four different types of transistors wherein the transistors are distinguished at least by the thicknesses and or compositions of the gate dielectric regions. Methods for making devices having three and at least four different types of transistors that are distinguished at least by the thicknesses and or compositions of the gate dielectric regions are also provided.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 11, 2014
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Curtis Tsai, Joodong Park, Jeng-Ya D. Yeh, Walid M. Hafez
  • Patent number: 8415737
    Abstract: A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: April 9, 2013
    Assignee: Flextronics International USA, Inc.
    Inventors: Berinder P. S. Brar, Wonill Ha
  • Patent number: 8378421
    Abstract: A thin film transistor substrate. The thin film transistor substrate includes a substrate, an adhesive layer on the substrate, and a semiconductor layer having a first doped region, a second doped region and a channel region on the adhesive layer. The thin film transistor substrate further includes a first dielectric layer on the semiconductor layer, a gate electrode overlapping the channel region, a second dielectric layer on the first dielectric layer and the gate electrode, a source electrode disposed on the second insulating layer, and a drain electrode spaced apart from the source electrode on the source electrode. The channel region is disposed between the first doped region and the second doped region, and has a transmittance higher than those of the first doped region and the second doped region.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: February 19, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jae Bon Koo, In-Kyu You, Seongdeok Ahn, Kyoung Ik Cho
  • Patent number: 8338219
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: December 25, 2012
    Assignee: STMicroelectronics S.R.L.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8330280
    Abstract: A bump structure comprises a first polymer block, a second polymer block, a first groove, an under bump metallurgy layer and a connection metal layer, wherein the first polymer block and the second polymer block are individual blocks. The first polymer block and the second polymer block are located at two sides of the first groove, the first polymer block comprises a first connection slot, and the second polymer block comprises a second connection slot communicated with the first connection slot and the first groove. The under bump metallurgy layer covers the first polymer block and the second polymer block to form a second groove, a third connection slot and a fourth connection slot communicated with each other. The connection metal layer covers the under bump metallurgy layer to form a third groove, a fifth connection slot and a sixth connection slot communicated with each other.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 11, 2012
    Assignee: Chipbond Technology Corporation
    Inventors: Cheng-Hung Shih, Shyh-Jen Guo, Wen-Tung Chen
  • Patent number: 8264019
    Abstract: A detector array for an imaging system may exploit the different sensitivities of array pixels to an incident flux of low energy photons with a wavelength falling near the high end of the range of sensitivity of the semiconductor. The detector array may provide the de-multiplexable spatial information. The detector array may include a two-terminal multi-pixel array of Schottky photodiodes electrically connected in parallel.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: September 11, 2012
    Assignee: STMicroelectronics S.r.L.
    Inventor: Massimo Cataldo Mazzillo
  • Patent number: 8202772
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: June 19, 2012
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 8058655
    Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: November 15, 2011
    Assignee: SS SC IP, LLC
    Inventors: David C. Sheridan, Andrew P. Ritenour
  • Patent number: 7982247
    Abstract: A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: July 19, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Lionel J. Riviere-Cazaux
  • Patent number: 7968921
    Abstract: An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Patent number: 7948016
    Abstract: The present disclosure provides a method of making a thin film semiconductor device such as a transistor comprising the steps of: a) providing a substrate bearing first and second conductive zones which define a channel therebetween, where the channel does not border more than 75% of the perimeter of either conductive zone; and b) depositing a discrete aliquot of a solution comprising an organic semiconductor adjacent to or on the channel, where a majority of the solution is deposited to one side of the channel and not on the channel. In some embodiments of the present disclosure, the solution is deposited entirely to one side of the channel, not on the channel, and furthermore the solution is deposited in a band having a length that is less than the channel length. The present disclosure additionally provides thin film semiconductor devices such as a transistors.
    Type: Grant
    Filed: November 3, 2009
    Date of Patent: May 24, 2011
    Assignee: 3M Innovative Properties Company
    Inventors: Scott M. Schnobrich, Robert S. Clough, Dennis E. Vogel, Michael E. Griffin
  • Patent number: 7880202
    Abstract: A semiconductor field effect transistor can be used with RF signals in an amplifier circuit. The transistor includes a source region and a drain region with a channel region interposed in between the source and drain regions. The transistor is structured such that the threshold voltage for current flow through the channel region varies at different points along the width direction, e.g., to give an improvement in the distortion characteristics of the transistor.
    Type: Grant
    Filed: November 27, 2006
    Date of Patent: February 1, 2011
    Assignee: Infineon Technologies AG
    Inventor: Peter Baumgartner
  • Patent number: 7772622
    Abstract: A manufacturing method of a field effect transistor in which, a patterned gate electrode is provided on a substrate, and a gate insulator is provided on the substrate and the gate electrode, a source electrode and a drain electrode are spaced apart from each other on the gate insulator, a region to be a channel between the source electrode and the drain electrode is provided, a boundary between the region and either one of the source electrode and the drain electrode is linear, a boundary between the region and either one of the drain electrode and the source electrode is non-linear, the boundary has a continuous or discontinuous shape, and the boundary part has a plurality of recess parts, the surface of the region has hydrophilicity and a peripheral region of the region prepares a member having water-repellency, and a solution including semiconductor organic molecules is supplied to the region, and the solution is dried.
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: August 10, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Fujimori, Tomihiro Hashizume, Masahiko Ando
  • Patent number: 7709311
    Abstract: A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: May 4, 2010
    Assignee: SuVolta, Inc.
    Inventors: Samar K. Saha, Ashok K. Kapoor
  • Patent number: 7692217
    Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: April 6, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
  • Patent number: 7683420
    Abstract: A nonvolatile memory semiconductor device and a method for manufacturing thereof are provided to avoid deterioration of the tunnel insulating film to increase frequency of writing data on the nonvolatile memory semiconductor device and erasing thereof. Concentration of atomic nitrogen in a tunnel insulating film 151 of a nonvolatile memory semiconductor device 1 is 0.1 to 5 atomic %. In addition, larger amount of atomic nitrogen in the tunnel insulating film 151 is distributed primarily in the interface layer of the tunnel insulating film 151, and concentration of atomic nitrogen in the interface layer is 10 times or more higher than concentration of atomic nitrogen in other portion of the tunnel insulating film 151. Further, density per unit area of atomic nitrogen in the surface of the tunnel insulating film 151 contacting with the floating gate is equal to or lower than 4×1014 atoms/cm2.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: March 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Shien Cho
  • Patent number: 7671358
    Abstract: A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Nick Lindert, Mitchell C. Taylor
  • Patent number: 7646044
    Abstract: A thin film transistor is provided, which includes: a semiconductor layer including an intrinsic portion; a gate electrode overlapping the intrinsic portion; a gate insulating layer disposed between the semiconductor layer and the gate electrode; and source and drain electrodes that have edges opposing each other with respect to the intrinsic portion of the semiconductor layer and are connected to the semiconductor layer, wherein the intrinsic portion has a curved surface contacting the gate insulating layer.
    Type: Grant
    Filed: November 22, 2004
    Date of Patent: January 12, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Moo Huh, Joon-Hak Oh, Joon-Hoo Choi, In-Su Joo, Beohm-Rock Choi
  • Patent number: 7605413
    Abstract: High voltage devices capable of preventing leakage current caused by inversion layer. In the high voltage device, a substrate comprises an active area formed therein, a source region and a drain region formed in the substrate, and a gate structure is formed on the active area to define a channel region in the substrate between the drain region and the source region, wherein the active area has at least one side extending along a direction perpendicular to the channel direction of the channel region, such that the gate structure without completely covering the extension.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: October 20, 2009
    Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.
    Inventors: Jiann-Tyng Tzeng, Li-Huan Zhu
  • Patent number: 7525138
    Abstract: A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: April 28, 2009
    Assignee: DSM Solutions, Inc.
    Inventors: Samar K. Saha, Ashok K. Kapoor
  • Patent number: 7417270
    Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: August 26, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
  • Patent number: 7391087
    Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Robert S. Chau, Patrick Morrow
  • Patent number: 7365403
    Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: April 29, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventor: Krishnaswamy Ramkumar
  • Patent number: 7339242
    Abstract: In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interconnection contact plugs are formed of the same conductive layer through the same process. Also, metal interconnections including bit lines, a cell metal interconnection, a peripheral gate interconnection, and peripheral metal interconnections directly connected to the plugs may be formed of the same metal layer through the same process. Accordingly, the interconnection structure such as the plugs and the metal interconnections is simplified and thus the process of their formation is simplified.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: March 4, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Soon Cho, Keon-Soo Kim, Jeong-Hyuk Choi, Sang-Youn Jo
  • Patent number: 7312486
    Abstract: Dishing is known to be a problem after CMP of dielectric layers in which the distribution of embedded metal is non-uniform. This problem has been solved by populating those areas where the density of embedded metal is low with unconnected regions that, instead of being uniformly filled with metal, are made up of metallic patterns whose combined area within a given region is about half the total area of the region itself. Two examples of such patterns are a line stripe pattern (similar to a parquet flooring tile) and a checker board pattern. Data is presented comparing the parasitic capacitances resulting from the use of patterns of this type relative to conventional solid patterns. The effect of aligning the regions so as to reduce their degree of overlap with wiring channels is also discussed.
    Type: Grant
    Filed: July 5, 2002
    Date of Patent: December 25, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kang-Cheng Lin, Chin-Chiu Hsia
  • Patent number: 7301234
    Abstract: The stack type semiconductor package module includes a lower semiconductor package having a main substrate, a chip mounted on the main substrate and electrically connected to the main substrate through a wire. An epoxy molding compound (EMC) is provided on the main substrate to cover the chip and the wire. Contact holes are formed in the EMC. A sub-substrate having protrusions coated with solder is connected to the lower semiconductor package by inserting the solder coated protrusions into the contact holes. Heat is applied to the protrusions, and the molten solder solidifies inside the contact holes. An upper semiconductor package having substantially identical structure as the lower package is then stacked on the sub-substrate.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 27, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae Woong Lee
  • Patent number: 7202528
    Abstract: Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single-or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: April 10, 2007
    Assignee: Semisouth Laboratories, Inc.
    Inventors: Igor Sankin, Joseph N. Merrett
  • Patent number: 7170118
    Abstract: Within both a field effect transistor (FET) device and a method for fabricating the field effect transistor (FET) device there is provided: (1) a semiconductor substrate; (2) a gate electrode formed over the semiconductor substrate and covering a channel region within the semiconductor substrate; and (3) a pair of source/drain regions formed within the semiconductor substrate and separated by the channel region within the semiconductor substrate. Within both the field effect transistor (FET) device and the method for fabricating the field effect transistor (FET) device, at least one of: (1) an interface of the channel region covered by the gate electrode; and (2) an upper surface of the gate electrode, is corrugated.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: January 30, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Fu-Liang Yang
  • Patent number: 7091535
    Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: August 15, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hung-Chih Tsai, Chien-Chih Chou, Ying-Ting Chang, Che-Jung Chu, Kuo-Chio Liu
  • Patent number: 7061055
    Abstract: A double-gate field-effect transistor includes a substrate, an insulation film formed on the substrate, source, drain and channel regions formed on the insulation film from a semiconductor crystal layer, and two insulated gate electrodes electrically insulated from each other. The gate electrodes are formed opposite each other on the same principal surface as the channel region, with the channel region between the electrodes. The source, drain and channel regions are isolated from the surrounding part by a trench, forming an island. Gate insulation films are formed on the opposing side faces of the channel region exposed in the trench. The island region between the gate electrodes is given a width that is less than the length of the channel region to enhance the short channel effect suppressive property of structure.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: June 13, 2006
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Toshihiro Sekigawa, Kenichi Ishii, Eiichi Suzuki
  • Patent number: 7023033
    Abstract: A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: April 4, 2006
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Kenichi Hirotsu, Hiroyuki Matsunami, Tsunenobu Kimoto
  • Patent number: 6974333
    Abstract: A high-density connection of multiple circuit boards having overlapping ends arranged in a stack. The metal traces on the stacked circuit boards are electrically connected by contact of the ends of the traces, which ends may be pads. The stacked circuit boards can be clamped, soldered or bonded together. Multiple circuit boards may be connected to a single circuit board. In one embodiment, double-sided circuit boards are stacked so that a first circuit board connects to a second circuit board through a third circuit board disposed intermediate the first and second circuit boards. The circuit boards may be flexible or rigid.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: December 13, 2005
    Assignee: General Electric Company
    Inventors: Douglas Glenn Wildes, Robert Stephen Lewandowski, Geir Ultveit Haugen
  • Patent number: 6946378
    Abstract: A method for fabricating a protective structure for bond wires of a semiconductor device assembly which includes sequentially fabricating one or more layers of the protective structure. After a first layer is formed, each subsequent layer is superimposed upon, contiguous with, and mutually adhered to an underlying layer of the protective structure. Such structure may be used to protect the bond wires of a test apparatus, which connect the contact pads of a carrier substrate of the test apparatus to corresponding bond pads of a test substrate. In addition, a fence member may be assembled with or formed on the test substrate to align and receive a semiconductor device and, thereby, to facilitate assembly of the semiconductor device with the test substrate. The fence member can be formed integrally with the protective structures or secured over the protective structures. Stereolithographic processes may be used to fabricate the fence member.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: September 20, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6888182
    Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 3, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Mitani, Yasumori Fukushima
  • Patent number: 6815765
    Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: November 9, 2004
    Assignee: Exploitation of Next Generation Co., Ltd.
    Inventor: Yutaka Arima