Abstract: A thin film transistor of the present invention is provided with (i) a plurality of divided channel regions formed under a gate electrode, and (ii) divided source regions and divided drain regions between which each of the divided channel regions is sandwiched, the divided source regions being connected with one another, and the divided drain regions being connected with one another. Here, the divided channel regions are so arranged that a spacing between the divided channel regions is smaller than a channel divided width which is a width of one divided channel region, the channel divided width is not more than 50 ?m, and the spacing is not less than 3 ?m. With this arrangement, it is possible to provide a thin film transistor capable of obtaining reliability with reducing the variation in threshold voltage by reducing the self-heating at the channel regions, as well as capable of reducing the increase of a layout area.

Abstract: A semiconductor device has a structure in which an impurity diffusion region with an impurity concentration lower than an impurity concentration of a source and a drain is formed between the source and drain and a channel below the gate, having an asymmetric shape with respect to a center line along which the gate extends.

Abstract: A semiconductor device includes a channel layer, a gate electrode formed on the channel layer, a p-type source region formed on a first side of the channel layer, and a p-type drain region formed on a second side of the channel layer. A heavy-hole band and a light-hole band are separated by compressive strain applied isotropically in an in-plane direction in the channel layer. A channel direction connecting the p-type source and drain regions is set substantially to a direction to maximize hole mobility in the channel layer.

Abstract: Disclosed is an ISFET comprising a H+-sensing membrane consisting of RF-sputtering a-WO3. The a-WO3/SiO2-gate ISFET of the present invention is very sensitive in aqueous solution, and particularly in acidic aqueous solution. The sensitivity of the present ISFET ranges from 50 to 58 mV/pH. In addition, the disclosed ISFET has high linearity. Accordingly, the disclosed ISFET can be used to detect effluent.

Abstract: The present invention provides a narrow/short high performance MOS device structure that includes a rectangular-shaped semiconductor substrate region having a first conductivity type. A region of dielectric material is formed at the center of the substrate region. Four substrate diffusion regions, each having a second conductivity type opposite the first conductivity type, are formed in the substrate diffusion region in a respective comer of the substrate region. The four diffusion regions are spaced-apart such that a substrate channel region is defined between each adjacent pair of substrate diffusion regions. A common conductive gate electrode is formed to have four fingers, each one of the fingers extending over a corresponding substrate channel region. The fingers of the common conductive gate electrode are spaced-apart from the underlying substrate channel regions by dielectric material formed therebetween.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Abstract: In one implementation, first and second layers are formed over a substrate. One of the layers has a higher oxidation rate than the other when exposed to an oxidizing atmosphere. The layers respectively have an exposed outer edge spaced inside of the substrate periphery. Etching is conducted into the higher oxidation rate material at a faster rate than any etching which occurs into the lower oxidation rate material. Then, the substrate is exposed to the oxidizing atmosphere. In another implementation, a stack of at least two conductive layers for an electronic component is formed. The two conductive layers have different oxidation rates when exposed to an oxidizing atmosphere. The layer with the higher oxidation rate has an outer lateral edge which is recessed inwardly of a corresponding outer lateral edge of the layer with the lower oxidation rate. The stack is exposed to the oxidizing atmosphere effective to grow an oxide layer over the outer lateral edges of the first and second layers.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

Abstract: A semiconductor device has source and drain regions, a gate insulating film, a gate electrode, and a channel region. The channel region includes a region where carriers move between the source and drain regions. An impurity concentration of the channel region is higher at an end portion of a surface depletion layer than at an interface between the semiconductor layer and the gate insulating film. The impurity concentration varies along a direction in which the gate electrode, the gate insulating film and the channel region are successively provided, and it increases substantially linearly near the end portion of the surface depletion layer.

Abstract: A convergence device 10 for assembly an LCD imaging device 14 to a fixed housing 12. The convergence device 10 has a frame 25 with a plurality of retention arms 26 protruding therefrom. Each of the retention arms 26 has a retention barb 27 for hooking behind a retention land 28 on the imaging device 14. The imaging device 14 has a retainer 18 with a plurality of preload flexures 24 for providing some outward pressure on the frame 15 of the convergence device 10. After the imaging device 14 is positioned on the fixed housing 12, an adhesive 30 is applied to a housing adhesive gap 32 and to a plurality of imager fixing adhesive gaps 34 to hold the convergence device 10 in place relative to the fixed housing 12 and further to hold the imaging device 14 in place relative to the convergence device 10.

Abstract: In order to enable non-integer current ratios to be produced in current mirror circuits using small transistors the channel area is adjusted by changes in the channel length over part of the width of the channel. In further embodiments the transistor is formed as two or more sub-transistors, the channel length of one sub-transistor being unequal to that of the other(s).

Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.

Abstract: The invention is related to a method for fabricating a channel region of a transistor device by ion implantation with a large angle and the transistor device formed therefrom. The transistor device is formed on a substrate. Furthermore, the ion implantation with a large angle forms the channel of the transistor in order to prevent the punchthrough phenomenon between the source region and the drain region. In addition, the profile of the channel region is compact and non-uniform. Therefore the ion concentration is higher in the middle of the channel region than in the other regions. Thus, the parasitic capacitance and the junction leakage can be reduced. The carrier mobility is higher than that of the prior art. Moreover, the threshold voltage is more easily controlled than that of the prior art.

Abstract: A compound semiconductor field effect transistor having, between a gate electrode and a drain electrode, a non-gate region which is the channel region not covered by the gate electrode, wherein a plurality of isolation regions are formed in the non-gate region in such a way that they extend in the direction of channel current and contact with the gate electrode. This compound semiconductor field effect transistor is improved in breakdown voltage between drain and gate and yet retains the high-speed operability of transistor.

Abstract: The present invention relates to a method and device for interconnecting radio frequency power SiC field effect transistors. To improve the parasitic source inductance advantage is taken of the small size of the transistors, wherein the bonding pads are placed on both sides of the die in such a way that most of the source bonding wires (6) go perpendicularly to the gate and drain bonding wires (7, 8). Multiple bonding wires can be connected to the source bonding pads, reducing the source inductance. An additional advantage comes from such arrangement by reducing the mutual inductance between source/gate and between source/drain due to the orthogonal wire placement.

Abstract: An array of P-channel memory cells is separated into independently programmable memory segments by creating multiple, electrically isolated N-wells upon which the memory segments are fabricated. The methods for creating the multiple, electrically isolated N-wells include p-n junction isolation and dielectric isolation.

Abstract: A method of defining at least two different field effect transistor channel lengths includes forming a channel defining layer over a substrate, the semiconductor substrate having a mean global outer surface extending along a plane. First and second openings are etched into the channel defining layer. The first and second openings respectively have a pair of opposing sidewalls having substantially straight linear segments which are angled from the plane. The straight linear segments of the opposing sidewalls of the first opening are angled differently from the plane than the straight linear segments of the opposing sidewalls of the second opening and are thereby of different lengths. Integrated circuitry includes a first field effect transistor and a second field effect transistor. The first and second field effect transistors have respective channel lengths defined along their gate dielectric layers and respectively have at least some portion which is substantially straight linear.

Abstract: In a channel well of a semiconductive substrate, source, drain and gate electrodes are formed. Below the gate electrode region, a plurality of partial regions of the second conductive type are arranged next to each other in the direction of the extension of the gate electrode region and in a mutually spaced relationship, said partial regions bordering on the gate electrode region and extending through the channel well region into the region of the substrate bordering on the channel well region from below.

Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.

Abstract: A source region 3 and a back-gate region 4 are alternately arranged along one side of a gate electrode 2 in a power MOSFET. The back-gate region 4 is formed so as not to substantially include the region immediately below the gate electrode 2. Thereby, it is possible to prevent a parasitic bipolar transistor from operating while controlling the increase of a channel resistance and thus, the breakdown resistance is improved.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: Disclosed is a low threshold asymmetric MOS device having a pocket region with a graded concentration profile. The pocket region includes a relatively high dopant atom concentration (of the same conductivity type as the bulk region) abutting either the device's source or its drain along the side of the source or drain that faces the device's channel region. The pocket region's graded concentration profile provides a lower dopant concentration near the substrate surface and an increasing dopant concentration below that surface. This provides a relatively low resistance conduction path through the pocket region, while allowing the device's threshold voltage to be somewhat higher at the pocket region. The asymmetric device can also include a counter dopant region located beneath its substrate surface. This forces current to flow in the substrate but just above the region of high counter dopant concentration, where the resistance is relatively low.

Abstract: A thin film effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; (c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; (d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A field effect transistor includes a semiconductor substrate, a channel layer, a superlattice layer having a structure of at least one quantum barrier layer of which an electron affinity is smaller than that of the channel layer and at least one quantum well layer where a resonant level of electron is generated, and an un-doped semiconductor layer, wherein these layers are formed on the semiconductor substrate in order, wherein a source electrode and a drain electrode are formed on the channel layer to be electrically connected to the channel layer, and wherein a gate electrode is formed on the un-doped semiconductor layer to have a Schottky contact.

Abstract: An N.sup.- type epitaxial layer is formed on a P type semiconductor substrate, and a P.sup.+ type insulative isolating layer is so formed as to reach the semiconductor substrate from the surface of the N.sup.- type epitaxial layer to define a device forming region in the N.sup.- type epitaxial layer. An N.sup.+ type source diffusion layer and an N.sup.+ type drain diffusion layer are formed on the N.sup.- type epitaxial layer in the device forming region, apart from each other in one direction. A plurality of P.sup.+ type gate diffusion layers are formed between the N.sup.+ type source diffusion layer and N.sup.+ type drain diffusion layer, apart from one another in a direction perpendicular to the one direction. Channel regions for controlling the source-drain current are formed between the P.sup.+ type insulative isolating layer and the gate diffusion layer and between adjoining gate diffusion layers.

Abstract: A semiconductor memory device and a fabrication method thereof include formation of surplus gates connected to a cell node of a gate edge region, located at a cell node side of a SRAM access transistor, and to the gate of a driving transistor located at the opposite side thereof. The present invention prevents silicon loss of the substrate caused by the formation of a buried contact in the conventional device, secures an operational stability of the memory cell by controlling differently the current flow of an access transistor in accordance with the condition of the cell node (for example, low level or high level), and facilitates an interconnection in the cell since the gate of a side transistor is used as a substitute for another interconnection (for example, a wiring) when realizing a SRAM.

Abstract: A miniaturized light valve with a surface area on the order of several centimeters may be successfully formed using a composite substrate and an opposing substrate which has thereon an electrode and which is bonded to the composite substrate at a predetermined gap therefrom. An electro-optical material, such as a liquid crystal compound, is confined within the gap. The composite substrate includes a single crystal layer of a semiconductor material provided on a lower level insulation layer. The single crystal layer is formed with a source region, a drain region, and a channel region of a MOS transistor, and a gate insulation film is provided on the single crystal layer in alignment with the channel region. Further, a gate electrode is provided on the gate insulation film. The composite substrate further includes a pixel electrode on the upper major surface of an insulation layer deposited over the MOS transistor and in contact with the drain region. The single crystal semiconductor thin film is limited to 0.

Abstract: A semiconductor device is provided by forming an insulating film on a supporting substrate and a semiconductor layer on the insulating film, forming an MOS semiconductor component having a source, a drain and a gate on the semiconductor layer, forming at least one of the source region of the semiconductor layer provided with the source and the drain region thereof provided with the drain to have greater thickness than a channel region of the semiconductor layer provided with a gate oxide film and a gate on the gate oxide film, and forming at least one of the source and the drain to be separated from the insulating film by the semiconductor layer of opposite conductivity type therefrom. A bulk layer of the same conductivity type as the semiconductor layer is provided in a thick region of the semiconductor layer. An MNOS or MONOS semiconductor non-volatile memory cell can be formed by replacing the gate oxide film with a memory gate insulating film consisting of a silicon oxide film and a silicon nitride film.

Abstract: The present invention discloses a MOSFET transistor supported on a substrate. The MOSFET transistor includes an epitaxial-layer of a first conductivity type near a top surface of the substrate defining a drain region therein. The MOSFET transistor further includes an oxide block supported on a raised silicon terrace of the epitaxial layer disposed in a central portion of the transistor above a JFET reduction region of a first conductivity type of higher dopant concentration than the epitaxial layer. The MOSFET transistor further includes a lower-outer body region of a second conductivity type surrounding the JFET reduction region disposed near the top surface and defining a boundary of the MOSFET transistor. The MOSFET transistor further includes a source region of the first conductivity type enclosed in the lower-outer body region disposed near the top surface and extended to the transistor boundary.

Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.

Abstract: A process for producing a radiation resistant power MOSFET is disclosed. The gate oxide is formed toward the end of the processing and is not exposed to substantial thermal cycling. The gate oxide thickness is increased to more than 1250 .ANG. for a device with a reverse voltage rating of 250 volts and the channel concentration is reduced to maintain a low threshold voltage. The thicker oxide prevents single event damage under reverse bias voltage.

Abstract: The invention provides for a field effect transistor (FET) which includes a substrate and a buffer layer formed upon the substrate and an active layer formed upon the buffer layer. The active layer includes a gate region, drain region and source region. In addition, a channel region is formed in the active layer intermediate the source region and drain region. The channel region includes a first portion of reduced thickness adjacent the drain region. The active layer may include a recess adjacent the drain region to provide the thin channel region. Preferably, the thickness of the first portion of the channel region is equal to the undepleted channel thickness within the second portion of the channel region adjacent the first portion. The substrate, buffer layer, active layer, and degenerate layers are preferably fabricated of silicon carbide or gallium nitride. Further, the FET preferably includes a p type buffer, n type active layer, and n+ degenerate layers.

Abstract: A vertical IGFET configuration includes a stripe arrangement having a non-linear shape. In one example, a stripe arrangement (30) has contact cut-out portions (41) and elongated portions (42). The elongated portions (42) have a width (44) that less than the width (43) of the contact cut-out portions (41). The stripe arrangement (30) increases channel density compared to typical individual cell configurations (10) and straight stripe configurations (20) thereby lowering on-resistance.

Abstract: A monolithic-microwave-integrated-circuit (MMIC) metal-semiconductor-field-effect (MESFET) transistor (40) or other type of field-effect transistor has a double-recessed channel region (32,42) with a gate recess (42) formed in a channel recess (32). The channel recess (32) is offset toward the drain (16) as far as possible without shorting the channel recess (32) to the drain (16) to increase the transistor breakdown voltage. The gate recess (42) is offset toward the source (14) as far as possible without causing the gate-source capacitance to increase, thereby reducing the transistor source resistance.

Abstract: A compound semiconductor device includes a carrier supply layer supplying free charge carriers and having high dopant impurity concentration regions with a prescribed width, disposed in stripe shapes along a main current flow direction, parallel to each other, and spaced at an interval, and a carrier channel layer to which free charge carriers are supplied from the carrier supply layer including an electron channel having a high free carrier density at portions corresponding to respective high dopant impurity concentration regions of the carrier supply layer in the vicinity of a heterojunction interface. The heterojunction interface formed by the carrier channel layer and the carrier supply layer has a periodic undulating shape with convex portions and valley portions in stripe shapes extending parallel to the main current flow direction.

Abstract: A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.

Abstract: Silicon-germanium devices including MOSFETs, photogates and photodiodes, are produced by implanting the Si or polycrystalline silicon substrate with Ge.sup.+, to realize active SiGe regions within Si which are substantially free from defects, at an appropriate point in the fabrication by conventional techniques.

Abstract: A MESFET which includes a semi-insulating substrate, e.g., a GaAs substrate, an insulating layer formed on a portion of the upper surface of the substrate, a first semiconductor layer formed on the upper surface of the substrate adjacent to opposite sides of the insulating layer, the first semiconductor layer having sidewalls defining a void therein, a nitride layer formed on a portion of the upper surface of the insulating layer, an oxide layer formed on the nitride layer, a second semiconductor layer formed on the sidewalls of the first semiconductor layer and in covering relationship to the void, a gate electrode formed on at least a portion of the upper surface of the second semiconductor layer, and, source and drain electrodes formed on the upper surface of the first semiconductor layer, on opposite sides of the gate electrode.

Abstract: A method for producing a Schottky barrier gate type field effect transistor includes producing a low concentration active region at a desired position of a semi-insulating compound semiconductor substrate and producing a gate electrode comprising refractory metal on the active region, producing a first insulating film and etching the same thereby to produce first side wall assist films comprising the first insulating film at both side walls of the gate electrode, removing one of the first side wall assist films at the side where a source electrode is to be produced, depositing a second insulating film to the thickness less than that of the first insulating film, etching the second insulating film thereby to produce a second side wall assist film having narrower width than that of the first side wall assist film at the side wall of the gate electrode where the source electrode is to be produced, and conducting ion implantation using the first and second side wall assist films and the gate electrode as a mask t

Abstract: A semiconductor device includes a semiconductor substrate and channel and electron supply layers epitaxially grown on the semiconductor substrate. Source, drain, and gate electrodes are disposed on the electron supply layer. At least the gate electrode and the electron supply layer are structured such that an electron gas within the channel layer is one-dimensional to prevent scattering of electrons in the channel layer.

Abstract: A field-effect transistor including a first channel layer, formed in contacting relationship with a gate electrode, and a second channel layer, formed on one side or both sides of the first channel layer in non-contacting relationship with the gate electrode, the carrier concentration in the second channel layer being higher than that in the first channel layer but lower than that in high-impurity concentration active layers forming drain and source regions. The field-effect transistor employs an offset gate configuration in which the gate electrode is formed in contacting relationship with the first channel layer at a position nearer to the high-impurity concentration active layer forming the source region than to the high-impurity concentration active layer forming the drain region.

Abstract: A field effect transistor having a buried gate, and one or more gates disposed along the channel between the source and drain, which cooperate to cause the electric field within the channel along its length to be more uniform, and have a lower field maximum. The geometry and/or doping of the channel can be varied to selectively vary the channel resistivity along its length, which also makes the field more uniform. Because of the more uniform field, electrons are exposed to a higher field strength nearer the source, and are accelerated to higher velocities more quickly, reducing the response time and increasing the frequency range of the transistor. Because the peak field is reduced, the transistor can carry more power without reaching breakdown potential within the channel.

Abstract: A field effect transistor is disclosed in which a source region and a drain region are formed to be reverse mesa on a semi-insulating semiconductor substrate with an insulating layer thereon by using a crystal growth characteristic corresponding to the crystal orientation. A channel layer and a gate electrode are formed by self-alignment on the upper part of a void formed according to the reverse mesa of the source and the drain regions, so that the channel layer and the semiconductor substrate are electrically separated by the void. By such a construction, a leakage current and backgating effect are removed, and a fast field effect transistor is attained owing to the reduction of an effective channel length and a gate resistance.

Abstract: An apparatus for limiting the rotational travel of a shaft of a valve actuator. A shaft engaging element having detents disposed therewith is connected to the shaft. A stop element is coupled to the actuator. When the shaft engaging element rotates with the shaft, the detents cooperate with the stop such that after a predetermined degree of rotational travel of the shaft the detents limit the travel of the shaft such that the resultant force balance of the shaft engaging element and thus the shaft is substantially zero.

Abstract: An FET with multiple channels to provide a substantially linear transfer characteristic. The widths and carrier concentrations of the channels, and the depths of the channels below the gate of the FET, are adjusted such that a substantially linear gate voltage-to-output current (drain) transfer characteristic of the FET results. In addition, the electrical characteristics of the FET may be adjusted by changing the spacing of the drain and source diffusions from the gate.

Abstract: A charge transfer device is equipped with a junction type field effect transistor coupled with the final stage of a transfer shift register for modulating current flowing therethrough depending upon the amount of electric charge from the transfer shift register, and the junction type field effect transistor comprises an n-type looped gate region formed in a p-type well, a p-type source region surrounded by the looped gate region, a p-type drain region opposite to the source region with respect to the looped gate region, and a p-type channel region defined in the p-type well beneath the looped gate region, wherein the p-type channel region is shallower or smaller in dopant concentration than remaining portion of the p-type well so that the current is effectively modulated with the electric charge.

Abstract: A semiconductor device is provided of the type having a doped semiconductor region coupled to source and drain electrodes and an elongated control gate contacting the doped region along the length of the gate for forming a nonconducting depletion region across the doped region for preventing current flow therethrough with the gate having a minimized width to reduce contact area with the doped region, wherein the width of the gate is repeatedly reduced along the length thereof for further reducing contact area with the doped semiconductor region.