Structure Configured For Voltage Converter (e.g., Charge Pump, Substrate Bias Generator) Patents (Class 257/299)
  • Patent number: 10868020
    Abstract: An integrated circuit structure includes: a well region having a first conductivity type; a semiconductor structure extending away from the well region from a major surface of the well region, the semiconductor structure having the first conductivity type; a source/drain feature disposed on the semiconductor structure, the source/drain feature having a second conductivity type different from the first conductivity type; an isolation layer laterally surrounding at least a portion of the semiconductor structure; a dielectric layer disposed on the isolation layer, where at least a portion of the source/drain feature is disposed in the dielectric layer; and a conductive plug continuously extending through the dielectric layer and the isolation layer to physically contact the major surface of the well region, wherein the conductive plug is coupled to a power supply line to bias the well region.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10854718
    Abstract: In one embodiment, a method of forming a HEM diode may comprise forming the HEM diode with high forward voltage that is greater than one of a gate-to-source threshold voltage of a HEMT or a forward voltage of a P-N diode.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: December 1, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Woochul Jeon
  • Patent number: 10825715
    Abstract: Structures and processes for improving radiation hardness and eliminating latch-up in integrated circuits are provided. An example process includes forming a first doped buried layer, a first well, and a second well, and using a first mask, forming a second doped buried layer only in a first region above the first doped buried layer and between at least the first well and the second well, where the first mask is configured to control spacing between the wells and the doped buried layers. The process further includes using a second mask, forming a vertical conductor located only in a second region above the first region and between at least the first well and the second well, where the vertical conductor is doped to provide a low resistance link between the second doped buried layer and at least a top surface of the substrate.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: November 3, 2020
    Assignee: Silicon Space Technologies Corporation
    Inventors: David R. Gifford, Patrice M. Parris
  • Patent number: 10825825
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10818516
    Abstract: A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: October 27, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Moshe Agam, Johan Camiel Julia Janssens, Bruce Greenwood, Sallie Hose, Agajan Suwhanov
  • Patent number: 10430537
    Abstract: According to an example embodiment, an integrated circuit may include a plurality of cells and a plurality of paths that supply power to the plurality of cells, respectively. The plurality of cells and the plurality of paths may be arranged based on a plurality of propagation delays of the plurality of cells, which include a plurality of first delays of the plurality of cells generated by a plurality of power resistances of the plurality of paths and a plurality of second delays of the plurality of cells generated based on a plurality of arrival timing windows that overlap each other.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongyoon Jung, Andrew Paul Hoover
  • Patent number: 10348191
    Abstract: An apparatus comprises a charge pump packaged with a load that receives charge provided by the charge pump, the charge pump comprising a plurality of switches that, when connected to a plurality of capacitors, cause the plurality of capacitors to assume a selected configuration, wherein the switches are configured to cause transitions between configurations of the capacitors.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: July 9, 2019
    Assignee: pSemi Corporation
    Inventor: David Giuliano
  • Patent number: 10068971
    Abstract: A junctionless field-effect transistor is provided and has an ultra-thin low-crystalline silicon channel. A fabrication method thereof also is provided for enabling greatly improved economics by significantly reducing the process costs while having electrical characteristics similar to those of the one formed on an SOI substrate by source/channel/drain regions formed in a junctionless ultra-thin low-crystalline silicon layer that has lower crystallinity than that of single-crystal silicon and that has a thickness of 20 nm or less on a bulk silicon substrate instead of an expensive SOI substrate.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: September 4, 2018
    Assignee: GACHON UNIVERSITY OF INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Seongjae Cho, Youngmin Kim
  • Patent number: 10037914
    Abstract: A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a gate, a spacer on a sidewall of the gate, a doping region on one side of the gate, an insulating cap layer covering the gate, the spacer and the doping region, and a redistributed contact layer (RCL) on the insulating cap layer. The RCL extends from the active area to the trench isolation region. A contact plug is disposed above the trench isolation region and is electrically connected to the gate or the doping region through the RCL.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: July 31, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhibiao Zhou, Ding-Lung Chen, Xing Hua Zhang
  • Patent number: 9947646
    Abstract: A semiconductor device includes a substrate having first and second regions. The first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The semiconductor device further includes first and second gate stacks over the insulator; a third gate stack over the channel region; a first dielectric layer over the first, second, and third gate stacks; a second dielectric layer over the first dielectric layer; and a metal layer over the first and second gate stacks. The metal layer is in electrical communication with the second gate stack and is isolated from the first gate stack by at least the first and second dielectric layers.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Chien-Hua Huang, Hsiang-Ku Shen, Zhao-Cheng Chen
  • Patent number: 9773681
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: September 26, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Manoj Kumar, Tsung-Hsiung Lee, Pei-Heng Hung, Chia-Hao Lee, Jui-Chun Chang
  • Patent number: 9768172
    Abstract: The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters includes a p-channel transistor and an n-channel transistor, respectively. The number of projection semiconductor layers each as the active region of the p-channel and the transistors of the second inserter is smaller than the number of the projection semiconductor layers each as the active region of the p-channel and the n-channel transistors of the first inverter.
    Type: Grant
    Filed: February 21, 2016
    Date of Patent: September 19, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takeshi Okagaki
  • Patent number: 9660525
    Abstract: A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 23, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Leland Chang, Evan G. Colgan, John U. Knickerbocker, Bucknell C. Webb, Robert Wisnieff
  • Patent number: 9653601
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 16, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 9647537
    Abstract: A circuit for generating a negative voltage on the basis of a positive voltage, including: at least one first transistor between a first terminal for applying a potential greater than a reference potential and a first node; a first capacitive element between the first node and a second node, a control terminal of said first transistor being linked to the second node; a first switch between the first node and a second terminal for applying the reference potential; a second switch between the second node and a third terminal for providing said negative voltage; a third switch between the second node and the second terminal; and a second capacitive element between the third terminal and the second terminal.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: May 9, 2017
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventor: François Ayel
  • Patent number: 9647539
    Abstract: A charge pump includes chip, package substrate and circuit board. Chip includes transistor set including at least four transistors connected to first input end of input terminal set and two rows of odd number and even number second input ends of input terminal set. Except first transistor, the other transistors are arranged in two rows subject to odd number and even number and respectively electrically coupled to the two rows of at least three second input ends by traces. At least three second external pins of package substrate and at least three capacitors of circuit board are respectively arranged in two rows subject to odd number and even number, enabling first circuit with connected odd number second external pins and second circuit with connected even number second external pin to be kept apart without intersection. Traces in chip are arranged in staggered manner, reducing parasitic capacitance.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 9, 2017
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Po-Chuan Lin
  • Patent number: 9634562
    Abstract: A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: April 25, 2017
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Vikas Rana, Marco Pasotti, Fabio De Santis
  • Patent number: 9583477
    Abstract: According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Chuan Cheah, Andrew N. Sawle
  • Patent number: 9583479
    Abstract: A charge pump for an integrated circuit includes a substrate, first and second transistors and a capacitor. The first transistor includes first source and first drain regions disposed within the substrate and defining a first channel therebetween. The first source and first drain regions are implanted with one of an n-type and a p-type dopant. The second transistor includes second source and second drain regions disposed within the substrate and defining a second channel therebetween. The second source and second drain regions implanted with the same type dopant as the first source region. The capacitor includes a metal terminal and a substrate terminal with a dielectric therebetween. The substrate terminal is disposed within the substrate and implanted with the same type dopant as the first source region. The substrate terminal contacts the first drain region and second source region within the substrate to provide electrical continuity therebetween.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Min-hwa Chi
  • Patent number: 9509213
    Abstract: A charge pump device with NMOS transistor circuit is provided for low voltage operation. The charge pump stage, comprising four NMOS transistors and three capacitors, is configured to alleviate the substrate body effect and the charge transfer loss. The charge pump circuit can be constructed on a p-type semiconductor substrate directly without deep N well isolation. The circuit is driven by two non-overlapping complementary clock signals, which can be generated easily with an integrated fabrication. The charge pump device can be implemented with a multiple stage to provide a stable high voltage output.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: November 29, 2016
    Assignee: GIANTEC SEMICONDUCTOR, LTD. INC.
    Inventor: Qing Peng Yuan
  • Patent number: 9368618
    Abstract: A semiconductor structure comprising an improved ESD protection device is provided. The semiconductor structure comprises a substrate, a well formed in the substrate, a first heavily doped region formed in the well, a second heavily doped region formed in the well and separated apart from the first heavily doped region, a gate structure formed on the substrate between the first heavily doped region and the second heavily doped region, a field region formed in the well under the first heavily doped region and the gate structure, and a field oxide/shallow trench isolation structure formed adjacent to the first heavily doped region. The field region is not formed under the second heavily doped region. The well and the field region have a first type of doping. The first heavily doped region and the second heavily doped region have a second type of doping.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 14, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Wing-Chor Chan
  • Patent number: 9324725
    Abstract: The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: April 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kentaro Saito, Hiraku Chakihara
  • Patent number: 9214415
    Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: December 15, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Brian Ashley Carpenter, Osvaldo Jorge Lopez, Juan Alejandro Herbsommer, Jonathan Noquil
  • Patent number: 9159715
    Abstract: To realize further miniaturization of a semiconductor device. The semiconductor device 10 is provided with a switching element (FET 14) provided on a substrate 18, a first electrode (electrode 13) provided on an opposite side of the substrate 18 interposing the switching element, a diode 12 provided on an opposite side of the switching element interposing the first electrode, and a second electrode (electrode 11) provided on an opposite side of the first electrode interposing the diode 12.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 13, 2015
    Assignee: Micro Module Technology Co., Ltd.
    Inventor: Fumikazu Harazono
  • Patent number: 9059702
    Abstract: Radio-frequency (RF) switch circuits providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a source, drain, gate, and body. A compensation circuit is connected to the respective source of the at least one FET. The compensation circuit may be configured to compensate a non-linearity effect generated by the at least one FET.
    Type: Grant
    Filed: July 6, 2013
    Date of Patent: June 16, 2015
    Assignee: Skyworks Solutions, Inc.
    Inventors: Haki Cebi, Fikret Altunkilic
  • Patent number: 9024423
    Abstract: A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with a gate pad electrode of the lower semiconductor chip in a plan view. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other. Accordingly, the size of a semiconductor device can be reduced.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: May 5, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Muto, Yuichi Machida, Nobuya Koike, Atsushi Fujiki, Masaki Tamura
  • Patent number: 9018046
    Abstract: An area efficient distributed device for integrated voltage regulators comprising at least one filler cell coupled between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size portion of said device is coupled to said I/O rails for distributing portions of said device on the periphery of said chip. The device is coupled as small size portion on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics International N.V., STMicroelectronics S.r.l.
    Inventors: Joshipura Jwalant, Nitin Bansal, Amit Katyal, Massimiliano Picca
  • Patent number: 8912579
    Abstract: A solid-state image pickup device includes: a photoelectric conversion portion formed on a substrate and composed of a photodiode; an image pickup area in which plural pixels each including a reading-out electrode for reading out signal electric charges generated and accumulated in the photoelectric conversion portion are formed; and a light blocking film having an opening portion right above the photoelectric conversion portion in an effective pixel area of the image pickup area, and light-blocking said photoelectric conversion portion in an OB pixel area of the image pickup area, in which a film deposited between the light blocking film and the substrate right above the photoelectric conversion portion in the OB pixel area is composed of only a silicon oxide film.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: December 16, 2014
    Assignee: Sony Corporation
    Inventor: Kaori Takimoto
  • Patent number: 8890223
    Abstract: An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: November 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan
  • Publication number: 20140264519
    Abstract: A switching element unit comprising a switching element and a smoothing capacitor that suppresses variation in DC voltage to be supplied to the switching element. An element mounting surface may be formed in an outer surface of the smoothing capacitor and may be formed integrally with a dielectric portion interposed between electrodes of the smoothing capacitor. A capacitor connection electrode as an electrode may be electrically connected to a terminal of the smoothing capacitor formed on the element mounting surface, and the switching element is placed on the element mounting surface such that a terminal of the switching element is electrically connected to the capacitor connection electrode.
    Type: Application
    Filed: January 29, 2013
    Publication date: September 18, 2014
    Applicant: AISIN AW CO., LTD.
    Inventor: Hirohisa Totani
  • Patent number: 8816419
    Abstract: Provided is a semiconductor device having a high switching speed. A semiconductor device is provided with an n-type epitaxial layer having a plurality of trenches arranged at prescribed intervals; an embedded electrode formed on an inner surface of the trench through a silicon oxide film to embed each trench; and a metal layer, which is capacitively coupled with the embedded electrode by being arranged above the embedded electrode through a silicon oxide film. In the semiconductor device, a region between the adjacent trenches operates as a channel (current path). A current flowing in the channel is interrupted by covering the region with a depletion layer formed at the periphery of the trenches, and the current is permitted to flow through the channel by eliminating the depletion layer at the periphery of the trenches.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: August 26, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masaru Takaishi
  • Patent number: 8811920
    Abstract: A direct current (DC)-DC converter having a DC-DC converter semiconductor die and an alpha flying capacitive element is disclosed. The DC-DC converter semiconductor die includes a first series alpha switching element, a second series alpha switching element, a first alpha flying capacitor connection node, which is about over the second series alpha switching element, and a second alpha flying capacitor connection node, which is about over the first series alpha switching element. The alpha flying capacitive element is electrically coupled between the first alpha flying capacitor connection node and the second alpha flying capacitor connection node. By locating the first alpha flying capacitor connection node and the second alpha flying capacitor connection node about over the second series alpha switching element and the first series alpha switching element, respectively, lengths of transient current paths may be minimized, thereby reducing noise and potential interference.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: August 19, 2014
    Assignee: RF Micro Devices, Inc.
    Inventors: Robert Deuchars, Jean-Christophe Berchtold, Joseph Hubert Colles, David Zimlich, Chris Levesque, William David Southcombe, David E. Jones, Scott Yoder, Terry J. Stockert
  • Patent number: 8792060
    Abstract: A liquid crystal display device with a built-in touch screen, which uses a common electrode as a touch-sensing electrode including an intersection of a gate line and a data line to define a pixel region, a bridge line disposed in a central portion of the pixel, an insulating layer formed on the bridge line, a first contact hole disposed through the insulating layer to expose a predetermined portion of an upper surface of the bridge line, a contact metal on the insulating layer and inside the first contact hole, the contact metal electrically connected with the bridge line, a first passivation layer on the contact metal, a second contact hole disposed through the first passivation layer to expose a predetermined portion of an upper surface of the contact metal, a common electrode on the first passivation layer and inside the second contact hole, a conductive line electrically connected with the common electrode, and a second passivation layer on the first passivation layer and the conductive line, wherein the
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: July 29, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Kum Mi Oh, Jae Hoon Park, Han Seok Lee, Hee Sun Shin, Won Keun Park
  • Patent number: 8791517
    Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kutsukake, Yoshiko Kato, Yoshihisa Watanabe, Koichi Fukuda, Kazunori Masuda
  • Patent number: 8779844
    Abstract: A semiconductor integrated circuit according to an embodiment includes a transfer transistor including a first gate electrode, the first gate electrode and a diffusion layer being diode-connected with a first wiring, and a clock signal line to which a clock signal is supplied, at least a portion of a first partial clock signal line, which is a portion of the clock signal line, being formed above the first gate electrode.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mai Muramoto, Takatoshi Minamoto
  • Publication number: 20140191305
    Abstract: Various aspects of the technology include an integrated circuit device comprising a compound semiconductor layer and a plurality of input, switch, and ground ohmic metal fingers fabricated on the compound semiconductor layer in a repeating sequence. A control gate may be disposed between each input finger and adjacent switch finger, and a sync gate may be disposed between each ground finger and adjacent switch finger. A sync gate and a control gate may be disposed adjacent each switch finger. The device further includes a plurality of control gate pads, each control gate pad at an end of two control gates, and a control gate pad at opposite ends of each control gate, and a plurality of sync gate pads, each sync gate pad at an end of two sync gates, and a sync gate pad at opposite ends of each sync gate.
    Type: Application
    Filed: March 11, 2014
    Publication date: July 10, 2014
    Inventor: James L. Vorhaus
  • Publication number: 20140159130
    Abstract: An apparatus and method of forming the same including, in one embodiment, a printed circuit board and a semiconductor device coupled to the printed circuit board. The apparatus also includes a decoupling device coupled to the printed circuit board and positioned under the semiconductor device.
    Type: Application
    Filed: November 27, 2013
    Publication date: June 12, 2014
    Applicant: Enpirion, Inc.
    Inventors: Ashraf W. Lotfi, Jeffrey Demski, Anatoly Feygenson, Douglas Dean Lopata, Jay Norton, John D. Weld
  • Patent number: 8748960
    Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jens Ejury
  • Patent number: 8729618
    Abstract: A method for manufacturing a semiconductor device comprises forming a first layer on an impurity diffusion region in a semiconductor substrate by a selective epitaxial growth method, forming a second layer on the first layer by the selective epitaxial growth method, forming a contact hole penetrating an interlayer insulating film in a thickness direction thereof and reaching the second layer, and filling a conductive material into the contact hole to form a contact plug including the first and second layers and the conductive material.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: May 20, 2014
    Inventor: Keiji Kuroki
  • Publication number: 20140103415
    Abstract: A charge pump circuit includes a substrate and first well region formed in the substrate. A first transistor includes first and second conduction regions disposed in the first well region. A second well region is formed in the substrate. A third well region is formed within the second well region. A second transistor includes first and second conduction regions disposed in the third well region. The second well region and third well region are coupled to a common terminal. The common terminal receives a local potential and the first well region and second well region are commonly maintained at the local potential. The first transistor and second transistor operate within the charge pump cell. A plurality of charge pump cells can be cascaded together with an output of a first charge pump cell coupled to an input of a second charge pump cell.
    Type: Application
    Filed: September 13, 2013
    Publication date: April 17, 2014
    Applicant: Semtech Corporation
    Inventors: Daniel Aebischer, Michel Chevroulet
  • Patent number: 8674455
    Abstract: A semiconductor device is provided, which includes an N well having a peak concentration of 2E+17 atom/cm3 or more in the range of 0.2 to 1 ?m depth from the surface of a P-type semiconductor substrate, and a region provided below the N well, the region containing P-type impurities with higher concentration than concentration of electrons.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: March 18, 2014
    Inventors: Kensuke Okonogi, Kazuhiro Nojima, Kiyonori Oyu
  • Publication number: 20140063882
    Abstract: A circuit arrangement includes a first transistor device and a second transistor device. Each transistor device includes a first load terminal, a second load terminal, a gate terminal, and a control terminal. The first load terminals are electrically connected, and the control terminals are electrically connected. A capacitive storage element is connected between the first load terminals and the control terminals.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 6, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Anton Mauder
  • Patent number: 8659090
    Abstract: A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-En Huang, Wun-Jie Lin, Ling-Chang Hu, Hsiao-Lan Yang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, Fu-An Wu, Jung-Ping Yang, Cheng Hung Lee
  • Publication number: 20140021522
    Abstract: Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.
    Type: Application
    Filed: September 23, 2013
    Publication date: January 23, 2014
    Applicant: Megica Corporation
    Inventors: Mou-Shiung Lin, Jin-Yuan Lee
  • Patent number: 8633530
    Abstract: In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kota Funayama, Hiraku Chakihara, Yasushi Ishii
  • Patent number: 8614124
    Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: December 24, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Sagy Charel Levy
  • Patent number: 8614125
    Abstract: A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: December 24, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyung Yim, In-Gyu Baek, Jang-Eun Lee, Se-Chung Oh, Kyung-Tae Nam, Jin-Shi Zhao
  • Patent number: 8530996
    Abstract: A semiconductor device includes a high-side field-effect transistor including a high-side drain electrode, a high-side gate electrode, and a high-side source electrode; and a first low-side field-effect transistor including a first low-side drain electrode, a first low-side gate electrode and a first low-side source electrode, wherein the high-side source electrode and the first low-side drain electrode are shared as a single source and drain electrode, and the high-side drain electrode, the high-side gate electrode, the source and drain electrode, the first low-side gate electrode and the first low-side source electrode are arranged in this order while being interposed by gaps, respectively.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Ken Shono
  • Patent number: 8519520
    Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: August 27, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: YuPing Gong, Yan Xun Xue, Liang Zhao
  • Publication number: 20130187211
    Abstract: A multi-layer integrated circuit package includes a switched-mode power supply circuit including a plurality of transistors which form part of a main current loop of the switched-mode power supply circuit. The plurality of transistors are arranged in one or more layers of the integrated circuit package. The package further includes a conductive plate arranged in a different layer of the integrated circuit package than the plurality of transistors. The conductive plate is in close enough proximity to at least part of the main current loop so that a current can be electromagnetically induced in the conductive plate responsive to a change in current in the main current loop.
    Type: Application
    Filed: December 21, 2012
    Publication date: July 25, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: INFINEON TECHNOLOGIES AG