Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) Patents (Class 257/296)
  • Patent number: 11329053
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may include forming first and second line patterns. The first line pattern has a first side facing the second line pattern, and the second line pattern has a second side facing the first line pattern. The methods may also include forming a first spacer structure on the first side of the first line pattern and a second spacer structure on the second side of the second line pattern. The first and the second spacer structures may define an opening. The methods may further include forming a first conductor in a lower part of the opening, forming an expanded opening by etching upper portions of the first and second spacer structures, and forming a second conductor in the expanded opening. The expanded opening may have a width greater than a width of the lower part of the opening.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 10, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon Ho Son, Jae Uk Shin, Yong Sun Ko, Im Soo Park, Sung Yoon Chung
  • Patent number: 11322597
    Abstract: At least one of a capacitor or a resistor structure can be formed concurrently with formation of a field effect transistor by patterning a gate dielectric layer into gate dielectric and into a first node dielectric or a first resistor isolation dielectric, and by patterning a semiconductor layer into a gate electrode and into a second electrode of a capacitor or a resistor strip. Contacts are then formed to the capacitor or resistor structure. Sidewall spacers may be formed on the gate electrode prior to patterning the capacitor or resistor contacts to reduce damage to the underlying capacitor or resistor layers.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 3, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hokuto Kodate, Hiroyuki Ogawa, Dai Iwata, Mitsuhiro Togo
  • Patent number: 11316029
    Abstract: A method is presented for forming a self-aligned middle-of-the-line (MOL) contact. The method includes forming a fin structure over a substrate, depositing and etching a first set of dielectric layers over the fin structure, etching the fin structure to form a sacrificial fin and a plurality of active fins, depositing a work function metal layer over the plurality of active fins, depositing an inter-layer dielectric (ILD) and a second set of dielectric layers. The method further includes etching the second set of dielectric layers and the ILD to form a first via portion and to expose a top surface of the sacrificial fin, removing the sacrificial fin to form a second via portion, and filling the first and second via portions with a conductive material to form the MOL contact in the first via portion and a contact landing in the second via portion.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: April 26, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yann Mignot, Indira Seshadri, Su Chen Fan, Christopher J. Waskiewicz, Eric Miller
  • Patent number: 11309313
    Abstract: The present application discloses a semiconductor device with a landing pad of conductive polymer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a landing pad of conductive polymer disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a conductive polymer layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The landing pad of conductive polymer comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chia-Hsiang Hsu
  • Patent number: 11296193
    Abstract: A nitride semiconductor device 1 includes a first nitride semiconductor layer 4, constituting an electron transit layer, a second nitride semiconductor layer 5, formed on the first nitride semiconductor layer 4 and constituting an electron supply layer, a nitride semiconductor gate layer 6, disposed on the second nitride semiconductor layer 5 and containing an acceptor type impurity, a metal film 7, formed on the nitride semiconductor gate layer 6, and a gate pad 23, connected to the metal film 7 via a gate insulating film 8 having a first surface and a second surface, the first surface of the gate insulating film 8 is electrically connected directly or via a metal to the metal film 7, and the second surface of the gate insulating film 8 is electrically connected directly or via a metal to the gate pad 23.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: April 5, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Taketoshi Tanaka
  • Patent number: 11289372
    Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 29, 2022
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, Jr., Qin-Yi Tong
  • Patent number: 11282860
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: March 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 11276685
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: March 15, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Patent number: 11271042
    Abstract: One embodiment provides a method of making a memory device. The method includes forming a via in a bit line, an interlayer and a dielectric region. The bit line is formed on the interlayer. The interlayer is formed partially on the dielectric region and partially on a plurality of memory cells. The via has a first end included in, and in direct contact with, the bit line and a second end to couple to an electrical contact.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Anna Maria Conti, Cristina Casellato, Andrea Redaelli
  • Patent number: 11271116
    Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 11264490
    Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: March 1, 2022
    Assignees: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
  • Patent number: 11264389
    Abstract: The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: March 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Szu-Yao Chang
  • Patent number: 11264392
    Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: March 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjun Kim, Seokhyun Kim, Jinhyung Park, Hoju Song, Hyeran Lee, Bongsoo Kim, Sungwoo Kim
  • Patent number: 11264569
    Abstract: A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Injo Ok, Kevin W. Brew, Timothy M. Philip, Muthumanickam Sankarapandian, Sanjay C. Mehta, Nicole Saulnier, Steven M. Mcdermott
  • Patent number: 11264320
    Abstract: Some embodiments include an integrated assembly having a set of true digit-lines and a set of complementary digit-lines. Each of the complementary digit-lines is comparatively coupled with an associated one of the true digit-lines. A semiconductor substrate is under the true digit-lines. The semiconductor substrate includes semiconductor features which project upwardly from a semiconductor base and which extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source/drain regions are within the semiconductor features and second source/drain regions are within the semiconductor base. The true digit-lines are coupled with the first source/drain regions. Wordlines are along the opposing sidewalls and include gating regions which gatedly couple the first source/drain regions with the second source/drain regions. Storage-elements are coupled with the second source/drain regions. In some embodiments, memory may utilize a 4F2 layout.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Anton P. Eppich
  • Patent number: 11257755
    Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 22, 2022
    Inventors: Yen-Yu Chen, Chung-Liang Cheng
  • Patent number: 11244712
    Abstract: A semiconductor device includes a substrate including an active region and a dummy active region that are spaced apart by an isolation layer, a buried word line extending from the active region to the dummy active region, and a contact plug coupled to an edge portion of the buried word line, wherein an upper surface of the active region is positioned at a higher level than an upper surface of the buried word line, and an upper surface of the dummy active region is positioned at a lower level than the upper surface of the buried word line.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: February 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Se Han Kwon
  • Patent number: 11245335
    Abstract: A DC/DC converter includes: electronic components group including a first capacitor, a high-voltage-side switching element, a low-voltage-side switching element, an inductor, and a second capacitor and constituting a half-bridge circuit; and a substrate including a high-voltage region, a low-voltage region, a connection region, and a pair of ground regions. The first capacitor is mounted across one of the ground regions and the high-voltage region. The high-voltage-side switching element is mounted across the high-voltage region and the connection region. The low-voltage-side switching element is mounted across the connection region and one of the ground regions. The inductor is mounted across the connection region and the low-voltage region. The second capacitor is mounted across the low-voltage region and one of the ground regions.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: February 8, 2022
    Assignee: Yazaki Corporation
    Inventor: Kazuhisa Wataru
  • Patent number: 11245029
    Abstract: A structure and formation method of a semiconductor device is provided. The method includes forming a semiconductor stack having first sacrificial layers and first semiconductor layers laid out alternately. The method also includes patterning the semiconductor stack to form a first fin structure and a second fin structure. The method further includes replacing the second fin structure with a third fin structure having second sacrificial layers and second semiconductor layers laid out alternately. In addition, the method includes removing the first sacrificial layers in the first fin structure and the second sacrificial layers in the third fin structure. The method includes forming a first metal gate stack and a second metal gate stack to wrap around each of the first semiconductor layers in the first fin structure and each of the second semiconductor layers in the third fin structure, respectively.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wang-Chun Huang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11244948
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 8, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Yi-Ching Chang, Kai-Lou Huang
  • Patent number: 11239252
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
  • Patent number: 11239360
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 1, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • Patent number: 11227867
    Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, an interlayer dielectric layer, multiple trenches in the interlayer dielectric layer including first, second, third trenches for forming respective gate structures of first, second, and third transistors, forming an interface layer on the bottom of the trenches; forming a high-k dielectric layer on the interface layer and sidewalls of the trenches; forming a first PMOS work function adjustment layer on the high-k dielectric layer of the third trench; forming a second PMOS work function adjustment layer in the trenches after forming the first PMOS work function adjustment layer; forming an NMOS work function layer in the trenches after forming the second PMOS work function adjustment layer; and forming a barrier layer in the trenches after forming the NMOS work function layer and a metal gate layer on the barrier layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 18, 2022
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 11217588
    Abstract: Some embodiments include integrated memory having a wordline, a shield plate, and an access device. The access device includes first and second diffusion regions, and a channel region. The channel region is vertically disposed between the first and second diffusion regions. The access device is adjacent to the wordline and to the shield plate. A part of the wordline is proximate a first side surface of the channel region with an intervention of a first insulating region therebetween. A part of the shield plate is proximate a second side surface of the channel region with an intervention of a second insulating region therebetween. The first insulating region includes an insulative material. The second insulating region includes a void. Some embodiments include memory arrays. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mitsunari Sukekawa, Hiroaki Taketani
  • Patent number: 11217518
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a dielectric layer, a first redistribution layer (RDL) and a second RDL. The encapsulant laterally encapsulates the die. The dielectric layer is located on the encapsulant and the die. The first RDL penetrates through the dielectric layer to connect to the die. The second RDL is located on the first RDL and the dielectric layer. The second RDL and the first RDL share a common seed layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho
  • Patent number: 11217587
    Abstract: A semiconductor device and a manufacturing method are provided. The semiconductor device includes an active region, a bit line, a capacitor contact, a conductive ring and a storage capacitor. The active region is formed in a substrate. The bit line and the capacitor contact are disposed over the substrate and electrically connected with the active region. The bit line is laterally separated from the capacitor contact, and a top surface of the bit line is lower than a top surface of the capacitor contact. An upper portion of the capacitor contact is surrounded by the conductive ring. The storage capacitor is disposed over and in electrical contact with the capacitor contact and the conductive ring.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: January 4, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Noriaki Ikeda
  • Patent number: 11211486
    Abstract: A power MOS device with low gate charge and a method for manufacturing the same. The device includes an M-shaped gate structure, which reduces the overlapped area between control gate electrode and split gate electrode. A low-k material is introduced to reduce dielectric constant of the isolation medium material. The combination of the M-shaped gate structure and low-k material can reduce parasitic capacitance Cgs of the device, thereby increasing switching speed and reducing switching losses.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: December 28, 2021
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Ming Qiao, Zhengkang Wang, Shida Dong, Bo Zhang
  • Patent number: 11205478
    Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: December 21, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Juan Boon Tan, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 11195575
    Abstract: A method, memory device and system. The memory device includes an active memory array including memory cells and address lines, the address lines including bitlines (BLs) and wordlines (WLs), each of the memory cells connected between one of the BLs and one of the WLs; a dummy array including dummy address lines, the dummy address lines including dummy BLs and dummy WLs; at least one shorting structure extending across and in electrical contact with at least some of the dummy address lines to electrically short the at least some of the dummy address lines together; and at least one contact structure extending from the dummy array and electrically coupled to the at least some of the dummy address lines to connect the at least some of the dummy address lines to a predetermined voltage.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Jaydip Bharatkumar Patel, Everardo Flores, III, Khaled Hasnat, Max F. Hineman
  • Patent number: 11195848
    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 25, 2019
    Date of Patent: December 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Daniel Billingsley, Indra V. Chary, Rita J. Klein
  • Patent number: 11195567
    Abstract: A circuit and method for establishing a balanced negative voltage to a near-end and far-end of a bitline having a plurality of memory cells connected to the bitline is disclosed. A MOS capacitor and a metal capacitor are connected in parallel. The MOS capacitor is connected to the near-end of the bitline through a first switch transistor. The metal capacitor is connected to the near-end of the bitline through the first switch transistor and the far end of the bitline through a second switch transistor. A falling negative boost voltage is applied to the MOS capacitor and the metal capacitor. When the switch transistors are turned on during a write operation, the MOS capacitor and the metal capacitor are both coupled to the voltage at the near-end and far-end and drive the voltage to approximately equal the boost voltage, thereby providing a balanced voltage to the bitline.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: December 7, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Che Tsai, Chia-En Huang, Chia-Cheng Chen, Yih Wang
  • Patent number: 11189621
    Abstract: A semiconductor layout structure for a dynamic random access memory (DRAM) array comprises a plurality of active areas, an isolation structure and a plurality of word lines in a semiconductor substrate, where the isolation structure is situated among the plurality of active areas. Each of the plurality of active areas comprises a first segment extending in a first direction and a second segment extending in a second direction, one end of the first segment connected to an end of the second segment such that the active area presents a ā€œVā€ shape. Two of the plurality of word lines intersect and traverse the first and second segments in each of the active areas respectively.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: November 30, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih Cheng Liu
  • Patent number: 11189618
    Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namho Jeon, Jin-Seong Lee, Hyun-jung Lee, Dongsoo Woo, Donggyu Heo, Jaeho Hong
  • Patent number: 11183115
    Abstract: A method for forming a pixel circuit includes forming transistors on a substrate; forming a passivation layer over the transistors; forming a contact hole to a source of a transistor; forming a transparent conductor that forms a contact in the contact hole and a resistor to control pixel current; and forming an organic light emitting diode (OLED) with an anode connecting to the resistor.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: November 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
  • Patent number: 11177266
    Abstract: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kirk D. Prall, Mitsunari Sukekawa
  • Patent number: 11177265
    Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Si-Woo Lee, Haitao Liu, Deepak Chandra Pandey
  • Patent number: 11176995
    Abstract: Programmable memory devices having a cross-point array of polymer junctions with individually-programmed conductances are provided. In one aspect, a method of forming a memory device includes: forming first metal lines on an insulating substrate; forming polymeric resistance elements on the first metal lines; and forming second metal lines over the polymeric resistance elements with a single one of the polymeric resistance elements present at each intersection of the first/second metal lines forming a cross-point array. A memory device and a method of operating a memory device are also provided.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, James B. Hannon
  • Patent number: 11177436
    Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Praneet Adusumilli, Jianshi Tang, Reinaldo Vega
  • Patent number: 11177273
    Abstract: A nonvolatile memory device includes a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors. The row line voltage is supplied through a plurality of row lines connecting the pass transistors to the memory cell array. Each of the row lines includes a wiring line parallel with a main surface of the substrate and a contact perpendicular to the main surface of the substrate. The wiring line of at least one row line among the row lines includes a plurality of conductive lines.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: November 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sung-Hoon Kim
  • Patent number: 11171222
    Abstract: A semiconductor device manufacturing method includes forming a first trench insulating film of a first depth in a substrate, forming at least one second trench insulating film that is spaced apart from the first trench insulating film and has a second depth that is greater than the first depth, forming a body region of a first conductivity type and a drift region of a second conductivity type in the substrate, forming a gate electrode overlapping the first trench insulating film, forming a source region in the body region and a drain region in the drift region, forming a silicide film on the drain region, and forming a non-silicide film between the first trench insulating film and the drain region, wherein the first trench insulating film overlaps the drift region and the gate electrode.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 9, 2021
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Guk Hwan Kim, Jin Yeong Son
  • Patent number: 11158718
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, Rita J. Klein, Everett A. McTeer, John Mark Meldrim
  • Patent number: 11158499
    Abstract: A semiconductor component includes a semiconductor substrate, a first oxide layer, an oxide, a first polysilicon layer, a first metal layer, a first mask on the first metal layer, and a bitline. The semiconductor substrate includes an array region, a periphery region and a boundary open region. The boundary open region isolates the array region from the periphery region. The first oxide layer is deposited on the array region. The first polysilicon layer is deposited on the periphery region. The first metal layer is deposited on the first polysilicon layer. A trench is formed on the array region and passes through the first oxide layer. The bitline includes a second polysilicon layer filling in the trench and a second metal layer on the second polysilicon layer. A second mask is formed on the second metal layer. The second polysilicon layer is flush with the first oxide layer.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: October 26, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Deok-Yong Kim, Yongchul Oh
  • Patent number: 11158533
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a first trench, and a second trench. The substrate has a first region and a second region. The first trench is formed in the substrate within the first region. The first trench is surrounded by a first protrusion structure having a top portion and sidewalls. The second trench is formed in the substrate within the second region. The second trench is surrounded by a second protrusion structure having a top portion and sidewalls. The second trench is deeper than the first trench. The connection portion between the top portion and the sidewalls of the second protrusion structure has a greater radius of curvature than the connection portion between the top portion and the sidewalls of the first protrusion structure.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: October 26, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi Hsu, Pi-Kuang Chuang, Po-Sheng Hu
  • Patent number: 11152365
    Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namho Jeon, Jin-Seong Lee, Hyun-jung Lee, Dongsoo Woo, Donggyu Heo, Jaeho Hong
  • Patent number: 11152567
    Abstract: A phase change memory structure (100) can include a memory cell, a dielectric material (130) adjacent to the memory cell, and a bit line. The memory cell can include a phase change material layer (110) and a top electrode layer (120) above the phase change material layer. The dielectric material can have a top surface (135) that is higher than a top surface (125) of the top electrode layer. The bit line (140) can have a non-flat bottom surface that contacts the top surface of the dielectric material and protrudes down from the top surface of the dielectric material to a top surface of the memory cell.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Maneesh Mishra, Mihir H. Bohra
  • Patent number: 11152429
    Abstract: An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: October 19, 2021
    Assignee: Intel Corporation
    Inventors: Abhishek A. Sharma, Brian S. Doyle, Ravi Pillarisetty, Prashant Majhi, Elijah V. Karpov
  • Patent number: 11139368
    Abstract: A semiconductor device includes a substrate having at least one trench with corrugated sidewall surface. At least one trench capacitor is located in the at least one trench. The at least one trench capacitor includes inner and outer electrodes with a node dielectric layer therebetween. At least one transistor is provided on the substrate. The at least one transistor comprises a source region and a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one trench capacitor.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 5, 2021
    Assignee: HeFeChip Corporation Limited
    Inventors: Geeng-Chuan Chern, Liang-Choo Hsia
  • Patent number: 11139302
    Abstract: Some embodiments include an integrated assembly having bitlines spaced from one another by intervening voids. Insulative supports are over the bitlines. A conductive plate is supported by the insulative supports and is proximate the bitlines to drain excess charge from the bitlines. Some embodiments include a method of forming an integrated assembly. A stack is formed to have insulative material over bitline material. The stack is patterned into rails that extend along a first direction. The rails include the patterned bitline material as bitlines, and include the patterned insulative material as insulative supports over the bitlines. The rails are spaced from one another along a second direction, orthogonal to the first direction, by voids. Sacrificial material is formed within the voids. A conductive plate is formed over the insulative supports and the sacrificial material. The sacrificial material is removed from under the conductive plate to re-form the voids.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Mitsunari Sukekawa, Hiroaki Taketani
  • Patent number: 11139309
    Abstract: Integrated circuitry comprises a plurality of features horizontally arrayed in a two-dimensional (2D) lattice. The 2D lattice comprises a parallelogram unit cell having four lattice points and four straight-line sides between pairs of the four lattice points. The parallelogram unit cell has a straight-line diagonal there-across between two diagonally-opposed of the four lattice points. The straight-line diagonal is longer than each of the four straight-line sides. Individual of the features are at one of the four lattice points and occupy a maximum horizontal area that is horizontally elongated along a direction that is horizontally angled relative to each of the four straight-line sides. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal Kumar Muthukrishnan, Alex J. Schrinsky
  • Patent number: 11139397
    Abstract: The present disclosure relates to methods for forming a semiconductor device. The method includes forming a substrate and forming first and second spacers on the substrate. The method includes depositing first and second self-assembly (SAM) layers respectively on sidewalls of the first and second spacers and depositing a layer stack on the substrate and between and in contact with the first and second SAM layers. Depositing the layer stack includes depositing a ferroelectric layer and removing the first and second SAM layers. The method further includes depositing a metal compound layer on the ferroelectric layer. Portions of the metal compound layer are deposited between the ferroelectric layer and the first or second spacers. The method also includes depositing a gate electrode on the metal compound layer and between the first and second spacers.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ming Lin, Sai-Hooi Yeong, Ziwei Fang, Chi On Chui, Huang-Lin Chao