Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) Patents (Class 257/296)
  • Patent number: 10665597
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 26, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Shin-Hung Li
  • Patent number: 10658588
    Abstract: Memory structures with a plurality of memory cells that each include memory devices in combination with switch devices are provided. The memory device and switch device of each cell are connected in series, and include at least first and second electrodes. The first electrode features a relatively high resistance, to provide a reduced snap current during operation of the memory device. The first electrode with a relatively high resistance can contain or be entirely composed of TiAlN.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventors: Shuichiro Yasuda, Tomohito Tsushima
  • Patent number: 10658479
    Abstract: The present disclosure relates to a flash memory cell that includes a substrate and a floating gate structure over the substrate. The floating gate structure includes a first portion having a first top surface and a first thickness. The floating gate structure also includes a second portion having a second top surface and a second thickness that is different from the first thickness. The floating gate structure further includes a sidewall surface connecting the first and second top surfaces, and an angle between the first top surface and the sidewall surface of the floating gate structure is an obtuse angle. The flash memory cell also includes a control gate structure over the first and second portions of the floating gate structure.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsien Chu, Chiang-Ming Chuang, Cheng-Huan Chung
  • Patent number: 10658402
    Abstract: Manufacturing methods for a low temperature poly-silicon array substrate and for a low temperature poly-silicon thin-film transistor are provided.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: May 19, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chen Chen
  • Patent number: 10658520
    Abstract: A semiconductor device including a transistor having low leakage current between the drain and the gate is provided. The semiconductor device includes an insulating film provided so as to cover a corner of the first conductor and a second conductor provided so as to overlap with a corner of the first conductor with the insulating film provided therebetween. Variation in the thickness of the insulating film can be prevented by making the first conductor have a rounded corner. Furthermore, concentration of electric field due to the corner of the first conductor can be relaxed. Thus, the current leakage between the first conductor and the second conductor can be reduced.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshinori Ieda
  • Patent number: 10651177
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate, a semiconductor layer, and a contact. The semiconductor layer is over the semiconductor substrate. The contact has an interface with the semiconductor layer. The contact is substantially tapered toward the semiconductor substrate to the interface.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 12, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chung-Lin Huang
  • Patent number: 10644126
    Abstract: A method to fabricate a non-planar memory device including forming a multi-layer silicon nitride structure substantially perpendicular to a top surface of the substrate. There may be multiple non-stoichiometric silicon nitride layers, each including a different or same silicon richness value from one another.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: May 5, 2020
    Assignee: MONTEREY RESEARCH, LLC
    Inventors: Yi Ma, Shenqing Fang, Robert Ogle
  • Patent number: 10644006
    Abstract: A method of forming a micro-pattern including forming a mold layer and a supporting material layer on a substrate, patterning the mold layer and the supporting material layer to form recess patterns, forming conductor patterns in the recess patterns, removing a portion of an upper portion of the supporting material layer for causing upper portions of the conductor patterns to protrude, forming a block copolymer layer on the supporting material layer, processing the block copolymer layer to phase-separate the block copolymer layer into a plurality of block parts, selectively removing some of the phase-separated plurality of block parts, and removing the supporting material layer to expose the mold layer at a position corresponding to each of the removed block parts may be provided.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: May 5, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soon-mok Ha, Jae-hee Kim, Chan Hwang, Jong-hyuk Kim
  • Patent number: 10636465
    Abstract: Disclosed are a magnetic memory device and a method of fabricating the same. The magnetic memory device comprises a bottom electrode on a substrate, a magnetic tunnel junction pattern including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer that are sequentially stacked on the bottom electrode, and a top electrode on the magnetic tunnel junction pattern. The bottom electrode comprises a first bottom electrode and a second bottom electrode on the first bottom electrode. Each of the first and second bottom electrodes comprises metal nitride. The first bottom electrode has a crystallinity higher than that of the second bottom electrode.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonjong Song, Kilho Lee, Daeeun Jeong
  • Patent number: 10636796
    Abstract: A dynamic random access memory and a method of fabricating the same are provided. The dynamic random access memory includes a substrate, an isolation structure, a buried word line structure, and a plurality of a first fin structures. The isolation structure is disposed in the substrate and defines a plurality of active regions arranged in a column in a first direction. The buried word line structure is located in the substrate and extended along the first direction and across the plurality of active regions and the isolation structure. The plurality of first fin structures is located in an intersecting region of the plurality of active regions and the buried word line structure, arranged in a column along the first direction, and surrounded and covered by the buried word line structure.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: April 28, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Kazuaki Takesako, Kazutaka Manabe
  • Patent number: 10629601
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of transistors on a semiconductor substrate. The formation of the plurality of transistors includes recessing channels of at least two transistors of the plurality of transistors. In the method, a stacked capacitor is formed on the semiconductor substrate, and the stacked capacitor is electrically connected in parallel to the at least two transistors of the plurality of transistors comprising the recessed channels and to an additional one of the plurality of transistors. The stacked capacitor, the at least two transistors and the additional one of the plurality of transistors form a memory cell of a plurality of memory cells of a memory device.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10622459
    Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla
  • Patent number: 10622159
    Abstract: Capacitive energy storage devices (CESDs) are disclosed, along with methods of making and using the CESDs. A CESD includes an array of electrodes with spaces between the electrodes. A dielectric material occupies spaces between the electrodes; regions of the dielectric material located between adjacent electrodes define capacitive elements. The disclosed CESDs are useful as energy storage devices and/or memory storage devices.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: April 14, 2020
    Assignee: Carver Scientific, Inc.
    Inventors: David Reginald Carver, Bradford Wesley Fulfer, Chase Andrepont, Sean Claudius Hall, Sean William Reynolds
  • Patent number: 10622366
    Abstract: A method of forming an array comprising pairs of vertically opposed capacitors comprises forming a conductive lining in individual capacitor openings in support material. An elevational mid-portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed laterally outward of the upper and lower capacitor electrode linings. Conductive material is formed laterally outward of the capacitor insulator to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Other methods and structure independent of method of manufacture are disclosed.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ashonita A. Chavan, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10615182
    Abstract: A thin film transistor device and a method for preparing the same, an array substrate and a display device are disclosed. The thin film transistor device includes a first thin film transistor and a second thin film transistor coupled with each other. A first electrode of the first thin film transistor, a second electrode of the second thin film transistor, and a connecting line therebetween which is configured to couple the first electrode and the second electrode, are formed in a same layer, with each end of the connecting line being connected between respective ends of the first electrode and the second electrode opposite to each other. In the thin film transistor device, the first electrode and the second electrode are spaced apart from each other by a concave portion which is recessed in a region therebetween.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: April 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jideng Zhou, Ran Zhang, Yi Wang, Huanyu Li
  • Patent number: 10615225
    Abstract: A multi-layer cross point memory array includes a plurality of layers, each in turn with a plurality of word lines; a plurality of intersecting lines intersecting the word lines at a plurality of points; and a plurality of memory element-transistor stacks. Each of the latter is formed on the intersecting lines; each stack in turn includes a memory element; and a complementary pair of parallel-connected field effect selection transistors including a p-FET and an n-FET, each of which has a gate, a first drain-source terminal connected to a corresponding one of the intersecting lines, and a second drain-source terminal connected to a corresponding one of the memory elements. The gate of the p-FET and the gate of an n-FET in an adjacent stack are connected to the same word line; and the mirror image is true for the n-FET and a p-FET in the adjacent stack on the opposite side.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 10607986
    Abstract: An IC includes an RC filter, a doped layer under a first dielectric layer, a polysilicon layer on the first dielectric layer providing a polysilicon plate for a capacitor of the filter, and gate(s) for MOSFET(s). A second dielectric layer is on the polysilicon plate. An input contact is on one end of the polysilicon plate and an output contact is on the opposite end. A metal layer includes metal providing contact to at least input contact and metal providing contact to the output contact. Analog circuitry includes the MOSFET having an I/O node coupled to the RC filter.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lin Li, Xiaoming Li, Xianhui Dong, Weibing Jing
  • Patent number: 10607997
    Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ye Ram Kim, Won Chul Lee
  • Patent number: 10600798
    Abstract: A manufacturing method of a non-volatile memory structure including the following steps is provided. Memory cells are formed on a substrate. An isolation layer is formed between the memory cells. A shield electrode is formed on the isolation layer. The shield electrode is electrically connected to a source line.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 24, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10600731
    Abstract: An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Zhang Jin
  • Patent number: 10600568
    Abstract: A capacitor includes a first electrode, a dielectric, and a second electrode. The first electrode is located on a dielectric layer. The dielectric covers the sidewall and the top surface of the first electrode. The second electrode covers the dielectric and the dielectric layer, wherein the orthographic projection area of the second electrode on the dielectric layer is greater than the orthographic projection area of the first electrode on the dielectric layer. The capacitor of the invention has good reliability.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: March 24, 2020
    Assignee: United Microelectronics Corp.
    Inventor: Po-Han Jen
  • Patent number: 10600778
    Abstract: Fabricating a semiconductor device includes receiving a substrate structure including a substrate. The substrate structure further includes a first bottom source/drain and a first fin formed on a vertical transistor portion of the substrate and a second bottom source/drain and a second fin formed on a varactor portion of the substrate. The substrate structure further includes a bottom spacer formed on the first bottom source/drain of the vertical transistor portion and the second bottom source/drain of the varactor portion. A mask is applied to the portion of the bottom spacer formed on the first bottom source/drain. The portion of the bottom spacer formed on the second bottom source/drain of the varactor portion is removed. The mask is removed from the portion of the bottom spacer formed on the first bottom source/drain. A gate oxide is deposited on the vertical transistor portion and the varactor portion.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10593557
    Abstract: A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-In Choi, Sang-Hoon Han, Sun-Jung Kim, Tae-Gon Kim, Hyun-Chul Song
  • Patent number: 10593663
    Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
  • Patent number: 10586806
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Patent number: 10573374
    Abstract: A data reading error is reduced. A memory cell array in a storage device includes a write word line, a read word line, a write bit line, a read bit line, a source line, and a gain cell. For example, a read transistor in the gain cell can include a metal oxide in a channel formation region. A cancel circuit is electrically connected to the read bit line. The cancel circuit has a function of supplying, to the read bit line, current for canceling leakage current supplied to the read bit line from the gain cell in a non-selected state. In read operation, a potential change of the read bit line due to leakage current is compensated for by the current from the cancel circuit, so that a data reading error is reduced.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiko Ishizu, Shuhei Nagatsuka
  • Patent number: 10573643
    Abstract: An integrated circuit having a vertical transistor includes first through fourth gate lines extending in a first direction and sequentially arranged in parallel with each other, a first top active region over the first through third gate lines and insulated from the second gate line, and a second top active region. The first top active region forms first and third transistors with the first and third gate lines respectively. The second top active region is over the second through fourth gate lines and insulated from the third gate line. The second top active region forms second and fourth transistors with the second and fourth gate lines respectively.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-ho Do, Sang-hoon Baek, Tae-joong Song, Jong-hoon Jung, Seung-young Lee
  • Patent number: 10559685
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and at least one semiconductor fin contacting the substrate. A first source/drain layer contacts the substrate. A silicide contacts and wraps around the first source/drain layer. The structure also includes a second source/drain layer above the first source/drain layer. The method comprises forming a structure including at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate. A silicide is formed in contact with and wrapping around the first source/drain layer. A gate structure is formed in contact with at least the at least one semiconductor fin. A second source/drain layer is formed above the first source/drain layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
  • Patent number: 10553692
    Abstract: A semiconductor device includes at least one trench extending into a semiconductor substrate and lined with a gate dielectric layer; a dipole inducing layer covering a lowermost portion of the lined trench; a gate electrode covering the dipole inducing layer and filled in the lined trench; and doping regions, in the semiconductor substrate, separated from each other by the lined trench and separated from the dipole inducing layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: February 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong-Soo Kim, Sung-Won Lim, Eun-Jeong Kim, Hyun-Jin Chang, Keun Heo, Jee-Hyun Kim
  • Patent number: 10553591
    Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: February 4, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ying-Chiao Wang, Li-Wei Feng, Chien-Ting Ho
  • Patent number: 10553703
    Abstract: A method used in forming an array of elevationally-extending transistors comprises forming spaced lower conductive lines over a substrate. A gate insulator is formed in openings that are individually directly above individual of the lower conductive lines. The openings are formed into laterally-spaced lines comprising sacrificial material and are spaced longitudinally there-along. Channel material is formed in the individual openings laterally adjacent the gate insulator and is electrically coupled to the individual lower conductive line there-below. The sacrificial material is replaced with conductive-gate material. Other methods are disclosed including arrays of elevationally-extending transistors independent of method of manufacture.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Patent number: 10535775
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a semiconductor substrate having a first semiconductor material layer separated from a second semiconductor material layer by an insulating layer. A source region and a drain region are disposed in the first semiconductor material layer and spaced apart. A gate electrode is disposed over the first semiconductor material layer between the source region and the drain region. A first doped region having a first doping type is disposed in the second semiconductor material layer, where the gate electrode directly overlies the first doped region. A second doped region having a second doping type different than the first doping type is disposed in the second semiconductor material layer, where the second doped region extends beneath the first doped region and contacts opposing sides of the first doped region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jack Liu, Charles Chew-Yuen Young
  • Patent number: 10529580
    Abstract: A semiconductor device structure and a manufacturing method thereof are provided. The semiconductor device structure includes a semiconductor substrate having an active component region and a non-active component region, a first dielectric layer, a second dielectric layer, high resistivity metal segments, dummy stacked structures and a metal connection structure. The high resistivity metal segments are formed in the second dielectric layer and located in the non-active component region. The dummy stacked structures are located in the non-active component region, and at least one dummy stacked structure penetrates through the first dielectric layer and the second dielectric layer and is located between two adjacent high resistivity metal segments. The metal connection structure is disposed on the second dielectric layer, and the high resistivity metal segments are electrically connected to one another through the metal connection structure.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Patent number: 10510906
    Abstract: A metal-oxide-semiconductor (MOS) capacitor is disclosed. The MOS capacitor includes a front-end-of-the-line (FEOL) field effect transistor (FET), and a plurality of middle-end-of-the-line (MEOL) conductive structures. The FEOL FET includes a source region and a drain region positioned in a semiconductor substrate, and a gate over the semiconductor substrate. The plurality of MEOL conductive structures is disposed on a top surface of the gate. At least one of the MEOL conductive structures is electrically disconnected from a back-end-of-the-line (BEOL) metal layer. A semiconductor fabrication method and a MOS capacitor circuit are also disclosed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Lin Liu, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 10510415
    Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Jun Liu, Zhiliang Xia, Li Hong Xiao
  • Patent number: 10510877
    Abstract: A semiconductor structure includes a substrate, a source/drain region, a composite layer and a plug. The source/drain region and the composite layer are over the substrate. The composite layer includes a first sublayer having a first material, a second sublayer having a second material, and a third sublayer having the first material. A bandgap of the second material is larger than that of the first material. The second sublayer is between the first sublayer and the third sublayer. The plug is through the composite layer, and electrically connected to the source/drain region. The plug includes a first portion laterally adjoining the first sublayer, a second portion laterally adjoining the second sublayer, and a third portion laterally adjoining the third sublayer, and a first width of the first portion and a third width of the third portion is smaller than a second width of the second portion.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ru-Shang Hsiao, Chi-Cherng Jeng, Chih-Mu Huang
  • Patent number: 10504596
    Abstract: Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Roger W. Lindsay
  • Patent number: 10504918
    Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiro Shimojo, Masahisa Sonoda
  • Patent number: 10498326
    Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: December 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Xiaoju Wu, Rajesh Keloth, Sudheer Prasad
  • Patent number: 10497582
    Abstract: A Metal-Insulator-Metal type capacitor structure (1) comprising a substrate (2), a first electrically insulating layer (14) placed on the substrate (2), a lower electrode (6) placed on the first insulating layer (14), a layer of structured metal (12) comprising a plurality of pores disposed on the lower electrode (6), a MIM capacitor (4) comprising a first conductive layer (18) placed on the structured metal layer (12) in contact with the lower electrode (6) and inside the pores, a dielectric layer (20) covering the first conductive layer (18), a second conductive layer (24) covering the dielectric layer (20) in contact with an upper electrode (8) placed on the MIM capacitor (4) and a second electrically insulating layer (16) placed on the upper electrode (8).
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: December 3, 2019
    Assignees: MURATA INTEGRATED PASSIVE SOLUTIONS, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Frédéric Voiron, Guy Parat
  • Patent number: 10490555
    Abstract: A method of forming semiconductor memory device includes the following steps. Firstly, a substrate is provided and the substrate includes a cell region. Then, plural bit lines are disposed within the cell region along a first direction, with each of the bit line includes a tri-layered spacer structure disposed at two sides thereof. Next, plural of first plugs are formed within the cell region, with the first plugs being disposed at two sides of each bit lines. Furthermore, plural conductive patterns are formed in alignment with each first plugs. Following theses, a chemical reaction process is performed to modify the material of a middle layer of the tri-layered spacer structure, and a heat treatment process is performed then to remove the modified middle layer, thereto form an air gap layer within the tri-layered spacer structure.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: November 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Ching Chang, Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10490656
    Abstract: A charge-compensation semiconductor device includes a source metallization spaced apart from a gate metallization, and a semiconductor body including opposing first and second sides, a drift region, a plurality of body regions adjacent the first side and each forming a respective first pn-junction with the drift region, and a plurality of compensation regions arranged between the second side and the body regions. Each compensation region forms a respective further pn-junction with the drift region. A plurality of gate electrodes in Ohmic connection with the gate metallization is arranged adjacent the first side and separated from the body regions and the drift region by a dielectric region. A resistive current path is formed between one of the gate electrodes and a first one of the compensation regions, or between the first one of the compensation regions and a further metallization spaced apart from the source metallization and the gate metallization.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Franz Hirler, Anton Mauder, Frank Dieter Pfirsch, Hans-Joachim Schulze, Uwe Wahl
  • Patent number: 10488392
    Abstract: An electrical stimulation and monitoring device that includes multiple signal paths that are connected in parallel with each other, and each containing a stimulation or sensing electrode, a DC-blocking capacitor and a stimulation or sensing channel. A semiconductor substrate provided for hosting the DC-blocking capacitors is connected electrically to a DC voltage source through a substrate holding capacitor. Such substrate holding capacitor reduces a blanking time between stimulation and sensing periods, and also reduces cross-couplings between different ones of the signal paths while all the DC-blocking capacitors are provided on one and same semiconductor substrate.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 26, 2019
    Assignee: MURATA INTEGRATED PASSIVE SOLUTIONS
    Inventor: Frédéric Voiron
  • Patent number: 10483271
    Abstract: A non-volatile memory structure including memory cells, at least one isolation layer, and at least one shield electrode is provided. The memory cells are disposed on a substrate. The isolation layer is located between the memory cells. The shield electrode is disposed on the isolation layer and electrically connected to a source line.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: November 19, 2019
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10483284
    Abstract: A semiconductor device includes stacked transistors. Each of the transistors includes a semiconductor column including a first conductive region of first conductivity type, a second conductive region of second conductivity type, an intrinsic region disposed between the first conductive region and the second conductive region, and a barrier region of the first conductivity type disposed between the intrinsic region and the second conductive region. A gate electrode is disposed to cover the intrinsic region, and a gate insulating layer is disposed between the gate electrode and the intrinsic region.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 19, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Sangsig Kim, Kyoungah Cho, Minsuk Kim, Yoonjoong Kim, Sola Woo, Doohyeok Lim
  • Patent number: 10483277
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, interconnect portions, a conductive layer, a stacked body, and columnar portions. At least one portion of the interconnect portions is provided inside the substrate, each of the interconnect portions extends in a first direction along a surface of the substrate, and the interconnect portions are arranged along a second direction crossing the first direction. The conductive layer is provided on the interconnect portions. The stacked body is provided on the conductive layer and includes electrode layers stacked to be separated from each other, and each of the electrode layers extends in the second direction. The columnar portions are provided inside the stacked body, each of the columnar portions includes a semiconductor portion extending in a stacking direction of the electrode layers and a charge storage film provided between the semiconductor portion and the stacked body.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Jun Nishimura
  • Patent number: 10475797
    Abstract: One method for manufacturing a semiconductor device includes: forming provisional active regions that are shaped such that active regions that are adjacent in an X direction are connected to each other, forming a sacrificial film, performing etching, including the sacrificial film, so as to form a plurality of first trenches that separate the active regions, embedding element-isolating insulating films in the first trenches and then removing the sacrificial film, forming first side-wall insulating films that cover the exposed side surfaces of the element-isolating insulating films and second side-wall insulating films that cover the side surfaces of the first side-wall insulating films, embedding cap insulating films in second trenches that appear due to the formation of the second side-wall insulating films, and forming a plurality of third trenches at the positions of the second side-wall insulating films and forming word lines thereunder.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: November 12, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Yoshinori Ikebuchi
  • Patent number: 10475921
    Abstract: An LDFET may be formed on the basis of manufacturing platforms designed for forming sophisticated small signal transistor elements. To this end, sidewall areas of trench isolation regions laterally positioned within the drift region may be used as current paths, thereby achieving increased design flexibility, since efficient current paths may still be established, even if the trench isolation regions have to extend into the substrate material due to design criteria determined by the sophisticated small signal transistor elements. In some illustrative embodiments, isolation of P-LDFETs with respect to the P-substrate may be accomplished without requiring a deep well implantation.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Patent number: 10467955
    Abstract: An electroluminescent display panel has pixel circuits for an active matrix driving system. At least one of the pixel circuits has a thin-film transistor in which a portion of a pattern of a metal wiring material above a channel layer of the thin-film transistor is disposed to shield the channel region of the thin-film transistor.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: November 5, 2019
    Assignee: Sony Corporation
    Inventors: Junichi Yamashita, Tetsuro Yamamoto, Katsuhide Uchino
  • Patent number: RE47816
    Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 14, 2020
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie