Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) Patents (Class 257/296)
  • Patent number: 10998321
    Abstract: A semiconductor device includes a buried word line in a substrate and extending along a first direction, a stacked nanowire structure over the buried word line, a first source/drain region and a second source/drain region on opposite sides of the stacked nanowire structure, and a bit line contact and a capacitor contact over the first source/drain region and the second source/drain region, respectively. A method for manufacturing the semiconductor device includes the steps of forming a buried word line extending along a first direction in a substrate, mounting an epitaxy silicon sheet on the substrate and the buried word line, forming a stacked nanowire structure over the buried word line, forming a first source/drain region and a second source/drain region on opposite sides of the stacked nanowire structure, and forming a bit line contact and a capacitor contact over the first source/drain region and the second source/drain region, respectively.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: May 4, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Huan-Yung Yeh
  • Patent number: 10998261
    Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Wen Wei Lum, Mooi Ling Chang, Ping Ping Ooi
  • Patent number: 10998323
    Abstract: A dynamic random access memory (DRAM) including a substrate, transistors, bit line sets, conductive structures, and word line sets is provided. The transistors are arranged on the substrate in an array. Each transistor includes a first conductive layer, a second conductive layer, and a third conductive layer. The bit line sets are disposed in parallel along a Y direction and pass through the transistors. Each bit line set includes a first bit line and a second bit line electrically connected to the first conductive layer of each transistor respectively. The conductive structures are located in the transistors. The conductive structures are electrically connected to the second conductive layer of the transistors and the substrate. The word line sets are disposed in parallel along an X direction. Each word line set includes a first word line and a second word line located on sidewalls of each transistor respectively.
    Type: Grant
    Filed: August 4, 2019
    Date of Patent: May 4, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Kai Jen, Ting-Ting Ke
  • Patent number: 10991703
    Abstract: Provided is a semiconductor device that has a low interface resistance between a contact plug and a bottom electrode of a real ferroelectric capacitor. A real capacitor oxidation suppression structure ST including a dummy ferroelectric capacitor 312 and a second plug 311 is formed. The dummy ferroelectric capacitor 312 includes a second bottom electrode 51, a second ferroelectric film 52, and a second top electrode 53, and is not used as a nonvolatile memory element. The second bottom electrode 51 is formed on an interlayer insulating film 50. The second ferroelectric film 52 is formed on the second bottom electrode 51. The second top electrode 53 is formed on the second ferroelectric film 52. The second plug 311 penetrates the interlayer insulating film 50 and electrically connects the second bottom electrode 51 to a semiconductor substrate 40.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: April 27, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Takanori Ozawa, Hiroaki Ito
  • Patent number: 10992221
    Abstract: A buck-boost charge pump includes a flying capacitor and a switch network. The switch network couples an input terminal to a first terminal of the flying capacitor using a first double switch and the second terminal of the flying capacitor to a power supply voltage terminal using a second switch in a charging phase of a boost mode, the input terminal to the second terminal of the flying capacitor using a third switch and the first terminal of the flying capacitor to an output terminal using the fourth switch in both a discharging phase of the boost mode and a charging phase of a buck mode, and the power supply voltage terminal to the first terminal of the flying capacitor using a first switch and the second terminal of the flying capacitor to the output terminal using a second double switch in a discharging phase of the buck mode.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: April 27, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Miroslav Hukel
  • Patent number: 10991509
    Abstract: A capacitor is provided that includes a base having a first main surface and a second main surface opposing each other with a trench formed on a side of the first main surface (110A. Moreover, a dielectric film is disposed in a region that includes an inside of the trench on the side of the first main surface of the base; a conductor film is provided that includes a first conductor layer disposed on the dielectric film, which is the region including the inside of the trench and a second conductor layer disposed on the first conductor layer; and a stress relieving portion is provided in contact with at least a part of the end of the first conductor layer. Moreover, a thickness of the stress relieving portion is smaller than a thickness of the conductor film, outside the trench portion of the first main surface of the base.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 27, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroshi Nakagawa, Tomoyuki Ashimine, Yasuhiro Murase
  • Patent number: 10985168
    Abstract: A semiconductor memory device includes a substrate, at least one floating gate electrode, an interlayer dielectric layer, an interconnection structure, an etching stop layer, a conductive structure, and an opening. The floating gate electrode is disposed on the substrate. The interlayer dielectric layer is disposed on the floating gate electrode. The interconnection structure is disposed in the interlayer dielectric layer. The etching stop layer is disposed on the interlayer dielectric layer. The conductive structure penetrates the etching stop layer and is electrically connected with the interconnection structure. The opening penetrates the etching stop layer and overlaps at least a part of the floating gate electrode in a thickness direction of the substrate.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 20, 2021
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Jung-Chun Yen, Chien-Chih Wang, Guang Yang, Jiawei Lyu, Linshan Yuan, Wen Yi Tan
  • Patent number: 10985160
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ni-Wan Fan, Jung-Chan Yang, Hsiang-Jen Tseng, Tommy Hu, Chi-Yu Lu, Wei-Ling Chang
  • Patent number: 10985239
    Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew N. Rocklein, An-Jen B. Cheng, Fredrick D. Fishburn, Sevim Korkmaz, Paul A. Paduano
  • Patent number: 10985165
    Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Si-Woo Lee, Kyuseok Lee, Sangmin Hwang
  • Patent number: 10984862
    Abstract: Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including a peripheral circuit, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. The 3D memory device also further includes a second semiconductor structure including an array of 3D NAND memory strings and a second bonding layer including a plurality of second bonding contacts. The 3D memory device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 20, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jun Liu
  • Patent number: 10978553
    Abstract: Methods, apparatuses, and systems related to forming a capacitor using a hard mask material are described. An example method includes patterning a surface to have a first silicate material, a first nitride material on the first silicate material, a second silicate material on the first nitride material, a second nitride material on the second silicate material, and a sacrificial material on the second nitride material. The method further includes forming a hard mask material on the sacrificial material. The method further includes forming a capacitor material in an opening through the first silicate material, the first nitride material, the second silicate material, the second nitride material, the sacrificial material, and the hard mask material. The method further includes removing the sacrificial material and the hard mask material.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Diem Thy N. Tran, Devesh Dadhich Shreeram, Sanjeev Sapra
  • Patent number: 10978456
    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 13, 2021
    Assignee: TC Lab, Inc.
    Inventor: Harry Luan
  • Patent number: 10971578
    Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Patent number: 10971501
    Abstract: A memory structure including a substrate, a memory cell, and a transistor is provided. The substrate includes a memory cell region and a peripheral circuit region. The memory cell is located in the memory cell region. The transistor is located in the peripheral circuit region. The transistor includes a gate, a first doped region, a second doped region, a first nickel silicide layer, and a second nickel silicide layer. The gate is located on the substrate and is insulated from the substrate. The first doped region and the second doped region are located in the substrate on two sides of the gate. The first nickel silicide layer is located on an entire top surface of the first doped region, and the second nickel silicide layer is located on an entire top surface of the second doped region.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ying-Tsung Chu, Ching-Kang Chiu, Ching-Sung Ho
  • Patent number: 10964800
    Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Byron Ho, Michael L. Hattendorf, Jeanne L. Luce, Ebony L. Mays, Erica J. Thompson
  • Patent number: 10964722
    Abstract: A Micro LED display substrate, a method for manufacturing the Micro LED display substrate, and a Micro LED display device are provided. In the method, the Micro LED is transferred onto the organic layer of the array substrate, one etching is performed to form through hole on both the protective layer and the array substrate, and then one metal deposition is performed to simultaneously form an electrode of the Micro LED and a structure electrically connecting the graphene layer with the source or drain electrode of the thin film transistor. Compared with the related art in which the electrode of the Micro LED and the structure electrically connecting the graphene layer with the source or drain electrode of the thin film transistor are formed through two etchings and two metal depositions, the method provided by the present disclosure saves the process steps, simplifies the process and reduces the costs.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 30, 2021
    Assignee: Shanghai Tianma Micro-Electronics Co., Ltd.
    Inventors: Xingda Xia, Jujian Fu, Gang Liu
  • Patent number: 10964690
    Abstract: Techniques are disclosed for forming semiconductor structures including resistors between gates on self-aligned gate edge architecture. A semiconductor structure includes a first semiconductor fin extending in a first direction, and a second semiconductor fin adjacent to the first semiconductor fin, extending in the first direction. A first gate structure is disposed proximal to a first end of the first semiconductor fin and over the first semiconductor fin in a second direction, orthogonal to the first direction, and a second gate structure is disposed proximal to a second end of the first semiconductor fin and over the first semiconductor fin in the second direction. A first structure comprising isolation material is centered between the first and second semiconductor fins. A second structure comprising resistive material is disposed in the first structure, the second structure extending at least between the first gate structure and the second gate structure.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 30, 2021
    Assignee: Intel Corporation
    Inventors: Roman W. Olac-Vaw, Walid M. Hafez, Chia-Hong Jan, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Nidhi Nidhi, Chen-Guan Lee
  • Patent number: 10964688
    Abstract: A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 30, 2021
    Assignee: Rohm Co., Ltd.
    Inventor: Naoki Takahashi
  • Patent number: 10930516
    Abstract: The present invention aims to improve the accuracy and stability when removing an insulating film at a bottom of a TSV to allow a through hole to open toward a connection target electrode. A semiconductor device manufacturing method including: forming a through hole in a semiconductor substrate by using anisotropic etching performed from a first surface side of the semiconductor substrate; forming a thin film being an insulating film on an entire inner surface of the through hole; forming a carbon-containing thin film using plasma deposition on the first surface including an opening edge portion of the through hole; engraving an inner bottom of the through hole by using anisotropic plasma etching with the carbon-containing thin film as a mask; removing the carbon-containing thin film by ashing; and forming a through-substrate electrode in the through hole.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 23, 2021
    Assignee: Sony Corporation
    Inventors: Takushi Shigetoshi, Takanori Tada
  • Patent number: 10923653
    Abstract: A phase change memory cell is provided that includes a phase change material-containing structure sandwiched between first and second electrodes. The phase change material-containing structure has a resistance that changes gradually, and thus may be used in analog or neuromorphic computing. The phase change material-containing structure may contain a plurality of phase change material pillars, wherein each phase change material pillar has a different phase change material composition. Alternatively, the phase change material-containing structure may contain a doped phase change material layer in which a dopant concentration decreases laterally inward from an outermost surface thereof.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kangguo Cheng
  • Patent number: 10923445
    Abstract: An integrated circuit includes pads formed on a back end of the line surface, and decoupling capacitor stacks monolithically formed about the pads. Solder balls are formed on the pads and connect to metal layers within the decoupling capacitor stacks to reduce noise and voltage spikes between the solder balls.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: February 16, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10923593
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. An upper material is directly above a lower material. The upper material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The lower material is in at least one of the top source/drain region, the bottom source/drain region, and the channel region. The upper material comprises 1 atomic percent to 10 atomic percent elemental-form H and 0 total atomic percent to less than 0.1 total atomic percent of one or more noble elements. The lower material comprises 0 atomic percent to less than 1 atomic percent elemental-form H and 0.1 total atomic percent to 10 total atomic percent of one or more noble elements. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov, Darwin Franseda Fan, Ali Moballegh
  • Patent number: 10923472
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a plurality of fins comprising a first fin, a second fin, a third fin, a fourth fin and a fifth fin, each of the plurality of protruding from the substrate in a first direction, and spaced apart from one another in a second direction that intersects the first direction and a plurality of trenches comprising a first trench, a second trench, a third trench and a fourth trench, each of the plurality of trenches being formed between adjacent fins of the plurality of fins, wherein variation of a first width of the first trench and a third width of the third trench is smaller than a first variation, wherein variation of a second width of the second trench and a fourth width of the fourth trench is smaller than a second variation, and wherein the second variation is greater than the first variation.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim, Geum Jong Bae
  • Patent number: 10923481
    Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: February 16, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
  • Patent number: 10923343
    Abstract: The invention discloses a high-k dielectric layer, a fabricating method thereof and a multi-function equipment implementing such fabricating method. The high-k dielectric layer of the invention includes M atomic-layer-deposited films formed in sequence on a material layer of a semiconductor device, where M is an integer larger than 1. The material layer can be a semiconductor layer, a metal layer or another dielectric layer. Each atomic-layer-deposited film is formed of an oxide and formed by an atomic layer deposition (ALD) process. N assigned films among the M atomic-layer-deposited films are bombarded by a non-reactive gas plasma during or after the cycles of the ALD process, where N is a natural number and less than or equal to M.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 16, 2021
    Inventors: Miin-Jang Chen, Chen-Yang Chung
  • Patent number: 10923420
    Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In Wook Oh, Dong Hyun Kim, Doo Hwan Park, Sung Keun Park, Chul Hong Park, Sung Wook Hwang
  • Patent number: 10916623
    Abstract: A semiconductor device including one or more switches on a substrate, a first electrode connected to the one or more switches and having a helical shape defining a spiral groove, a support in contact with the first electrode, the spiral groove extending between the support and a portion of the first electrode, a capacitor dielectric layer in contact with the first electrode, and a second electrode in contact with the capacitor dielectric layer.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok Han Park
  • Patent number: 10910392
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Patent number: 10903208
    Abstract: An electrical device including a plurality of fin structures. The plurality of fin structures including at least one decoupling fin and at least one semiconductor fin. The electrical device includes at least one semiconductor device including a channel region present in the at least one semiconductor fin, a gate structure present on the channel region of the at least one semiconductor fin, and source and drain regions present on source and drain region portion of the at least one semiconductor fin. The electrical device includes at least one decoupling capacitor including the decoupling fin structure as a first electrode of the decoupling capacitor, a node dielectric layer and a second electrode provided by the metal contact to the source and drain regions of the semiconductor fin structures. The decoupling capacitor is present underlying the power line to the semiconductor fin structures.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Darsen D. Lu, Ghavam G. Shahidi
  • Patent number: 10895539
    Abstract: A system includes a camera mounted external to and adjacent to a window of a processing chamber configured to process semiconductor substrates. The window allows the camera to view a component in the processing chamber. The camera is configured to generate a video signal indicative of a status of the component during a process being performed in the processing chamber. The system further includes a controller coupled to the processing chamber. The controller is configured to control the camera, process the video signal from the camera, determine the status of the component based on the processing of the video signal, and determine whether to terminate the process based on the status of the component.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: January 19, 2021
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kapil Sawlani, Gary B. Lind, Michal Danek, Ronald Powell, Michael Rumer, Kaihan Ashtiani
  • Patent number: 10896885
    Abstract: Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: January 19, 2021
    Assignees: Polar Semiconductor, LLC, Sanken Electric Co., Ltd.
    Inventors: Peter West, Dosi Dosev, Don Rankila, Tatsuya Kamimura, Steve Kosier
  • Patent number: 10893225
    Abstract: An electronic device includes a first sensing module and a first threshold voltage generation module. The first sensing module includes a first sensing transistor having a first gate, a second gate and a semiconductor layer. The semiconductor layer of the first sensing transistor is disposed between the first gate and the second gate of the first sensing transistor. The first gate of the first sensing transistor is coupled to a top gate line. The first threshold voltage generation module includes a node coupled to the second gate of the first sensing transistor, and is used to provide a first threshold voltage in a dark state to the node of the first threshold voltage generation module.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 12, 2021
    Assignee: InnoLux Corporation
    Inventor: Junya Shibata
  • Patent number: 10892223
    Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 12, 2021
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Robert L. Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A. Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
  • Patent number: 10892360
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: January 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Patent number: 10886355
    Abstract: A display device includes: a substrate including a display area at which an image is displayed; and on the substrate in the display area thereof: a data line and a gate line on the substrate; a thin film transistor connected to the gate line and the data line; a pixel electrode connected to the thin film transistor; and a storage line which overlaps the pixel electrode. The storage line has a first hole at a position overlapping the data line.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyeoncheol Kang
  • Patent number: 10886275
    Abstract: A memory device is provided that includes a bilayer nanosheet channel layer including a silicon (Si) layer and a silicon germanium (SiGe) layer; and a common gate structure for biasing each of the silicon layer and the silicon germanium layer of the bilayer nanosheet channel layer to provide one of the silicon layer and the silicon germanium layer is biased in accumulation and one of the first layer and the second layer biased in inversion. The memory devices also includes a floating body region on a front face or rear face of the bilayer nanosheet channel layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari, Clint Oteri
  • Patent number: 10886279
    Abstract: A memory device may include an active device region, disposed at least partially in a first level. The memory device may include a storage capacitor, disposed at least partially in a second level, above the first level, wherein the first level and the second level are parallel to a substrate plane. The memory device may also include a contact via, the contact via extending between the storage capacitor and the active device region, and defining a non-zero angle of inclination with respect to a perpendicular to the substrate plane.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 5, 2021
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Sony Varghese, Anthony Renau, Morgan Evans, John Hautala, Joe Olson
  • Patent number: 10886281
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of transistors on a semiconductor substrate. The formation of the plurality of transistors includes recessing channels of at least two transistors of the plurality of transistors. In the method, a stacked capacitor is formed on the semiconductor substrate, and the stacked capacitor is electrically connected in parallel to the at least two transistors of the plurality of transistors comprising the recessed channels and to an additional one of the plurality of transistors. The stacked capacitor, the at least two transistors and the additional one of the plurality of transistors form a memory cell of a plurality of memory cells of a memory device.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10879282
    Abstract: An imaging sensor according to an exemplary embodiment includes a first semiconductor substrate, a second semiconductor substrate, a plurality of pixels, each pixel including a photoelectric conversion unit arranged on the first semiconductor substrate, a plurality of transfer units arranged on the first semiconductor substrate and configured to transfer charges generated in the photoelectric conversion unit or signals based on the charges via a plurality of mutually parallel paths respectively, and a plurality of signal holding units connected to the plurality of transfer units respectively, and a plurality of lines that are arranged between the first semiconductor substrate and the second semiconductor substrate, each of the plurality of lines connecting a corresponding one of the plurality of transfer units to a corresponding one of the plurality of signal holding units in one pixel.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 29, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yasuji Ikeda
  • Patent number: 10878911
    Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: December 29, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Jun Liu, Zhiliang Xia, Li Hong Xiao
  • Patent number: 10879248
    Abstract: A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon-Sang Choi, Hyeok-Jin Jeong, Jung-Kun Lim, Young-Mo Tak, Sung-Kil Han
  • Patent number: 10872858
    Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of word lines, and a plurality of bit lines. The semiconductor substrate includes a plurality of active areas. The word lines are disposed parallel to one another, and each of the word lines is elongated in a first direction. Each of the word lines overlaps at least one of the active areas. The bit lines are disposed parallel to one another, and each of the bit lines is elongated in a second direction. Each of the bit lines overlaps at least one of the active areas. The bit lines cross the word lines. An included angle between the first direction and the second direction is larger than 0 degree and smaller than 90 degrees.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: December 22, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hong-Ru Liu, Kuei-Hsuan Yu
  • Patent number: 10871811
    Abstract: A power chip includes: a first power switch, formed in a wafer region and having a first and a second metal electrodes; a second power switch, formed in the wafer region and having a third and a fourth metal electrodes, wherein the first and second power switches respectively constitute an upper bridge arm and a lower bridge arm of a bridge circuit, and the first and second power switches are alternately arranged along a first direction; and a metal region, at least including a first metal layer, a second metal layer and a third metal layer that are stacked, each metal layer including a first to a third strip electrodes, and strip electrodes with the same voltage potential in two adjacent metal layers are electrically coupled, wherein a routing direction of the strip electrode in the first metal layer is substantially perpendicular to the first direction.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 22, 2020
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Yan Chen, Xiaoni Xin, Le Liang, Shouyu Hong, Jianhong Zeng
  • Patent number: 10867858
    Abstract: Processing methods may be performed to produce three-dimensional interconnects on a substrate. The methods may include forming a first metal interconnect layer over a semiconductor substrate. The methods may include forming a first dielectric layer over the first metal interconnect layer. The methods may include forming a second metal interconnect layer over the first dielectric layer. The methods may include forming a patterning mask overlying the second metal interconnect layer. The methods may also include simultaneously etching each of the first metal interconnect layer, the first dielectric layer, and the second metal interconnect layer to expose the substrate to produce a multilayer interconnect structure in a first lateral direction.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: December 15, 2020
    Assignee: Applied Materials, Inc.
    Inventor: Suketu A. Parikh
  • Patent number: 10867994
    Abstract: A vertical structure may be used as a high density capacitance for an integrated circuit. These thin vertical structures can be configured to operate as an insulator in a metal-insulator-metal (MIM) capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: December 15, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Zhonghai Shi, Marc L. Tarabbia
  • Patent number: 10861698
    Abstract: The present disclosure provides a method for semiconductor manufacturing in accordance with some embodiments. The method includes providing a substrate and a patterning layer over the substrate, wherein the substrate includes a plurality of features to receive a treatment process; forming at least one opening in the patterning layer, wherein the plurality of features is partially exposed in the at least one opening; applying a directional etching to expand the at least one opening in a first direction, thereby forming at least one expanded opening; and performing the treatment process to the plurality of features through the at least one expanded opening.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Ya-Wen Yeh, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Wei-Hao Wu, Li-Te Lin, Ru-Gun Liu, Kuei-Shun Chen
  • Patent number: 10861740
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Patent number: 10854458
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 10854717
    Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: December 1, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears