Abstract: A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a mono-layer gate scheme to simplify the electrode wiring structure and to eliminate a current leakage problem of an insulating film between electrodes. A side and bottom of a semiconductor region, which is disposed directly below a capacity electrode section with a gate insulating film interposed therebetween that compose a control electrode, are isolated from another semiconductor region and semiconductor substrate by insulating films. Thus, a high programming control voltage which is not limited by a junction yield voltage between the semiconductor regions and semiconductor substrate may be applied. Due to that, an area of the capacity electrode section of a floating electrode may be considerably reduced.

Abstract: The outputted voltage of a rectifier 3 is detected by a voltage detector circuit 17. When the detected voltage value is low (received radio wave is weak, distance is long), a controller 20 turns off a switch 16 to connect only a capacitor 14 to the output of the rectifier 3, so that the capacitances of the capacitors are decreased and the build up of a power voltage is accelerated. On the other hand, when the detected voltage value is higher than a prescribed level (received radio wave is powerful, distance is short), the controller 20 turns on the switch 16 to connect capacitors 14, 15 in parallel with the output of the rectifier 3, so that the capacitances of the capacitors are increased and a ripple is fully removed. Thus, communications can be made while preventing a malfunction due to the ripple.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of integrated semiconductor memory or other integrated semiconductor circuit devices which include, as a part of each integrated circuit device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the device to the board. By connecting the on-chip capacitors of the integrated circuit devices in parallel, sufficient capacitance is provided to stabilize current to all of the integrated circuit devices.

Abstract: A memory cell includes a transfer transistor having a gate which is connected to a word line, a first electrode which is connected to a bit line, and a second electrode, and a storage capacitor having a storage electrode which is connected to the second electrode of the transfer transistor, a confronting electrode, and a charge storage layer which is provided between the storage electrode and the confronting electrode. The storage capacitor has a capacitance which changes with a hysteresis curve which is determined by a bias voltage applied across the storage electrode and the confronting electrode, so that the capacitance takes one of two values depending on the bias voltage.

Abstract: A semiconductor memory is provided wherein two bits of binary information are stored simultaneously in a ferroelectric capacitor by utilizing the positive and negative polarization states of the ferroelectric capacitor for storing a first of the two bits of binary information and by utilizing the capacitive characteristic of the ferroelectric capacitor to simultaneously store a second of the two bits of binary information without altering the polarization of the ferroelectric capacitor. When reading information from the ferroelectric capacitor, the second of the two bits of information is read out first and transferred to a buffer cell, then the first of the two bits of binary information is read and re-written, as desired, and the second of the two bits of information is returned from the buffer cell to the ferroelectric capacitor.

Abstract: An electrically controllable variable capacitor includes the interelectrode capacitance of at least one power MOSFET, a capacitance connected in series with the MOSFET and having one terminal connected to the drain or source thereof (the series capacitance), and bias control circuitry for controlling the bias voltage applied to the MOSFET. The voltage rating of the MOSFET, the peak amplitude of the applied ac signal, and the value of the series capacitance determine the range of dc bias voltages over which the MOSFET can be operated, and hence the capacitance range of the variable capacitor. Such a variable capacitance is useful as a tuning capacitor in an electrodeless HID lamp ballast.

Abstract: A multi-bit data storage location 201 is formed at the face of a layer 502 of semiconductor of a first conductivity type. Storage location 201 includes a first transistor 210 having a source/drain region 308 of a second conductivity type formed in layer 502 and a gate 306 disposed insulatively adjacent a first channel area of layer 502 laterally adjacent source/drain region 308. A second transistor 210 is included having a gate 306 disposed insulatively adjacent a second channel area of layer 502. A first capacitor 211 is provided which includes a capacitor conductor 311 disposed insulatively adjacent a first capacitor area 509 of layer 502, first capacitor area 509 being disposed lateral to the first channel area of first transistor 210. A second capacitor 211 is provided which includes a capacitor conductor 211 disposed insulatively adjacent a second capacitor area 509 of layer 502, the second capacitor area 509 disposed lateral to the second channel area of second transistor 210.

Abstract: An LC element with a pn junction layer formed near the surface of a p-Si substrate by forming an n.sup.+ region having a predetermined shape and in a portion thereof additionally forming a p.sup.+ region having the same shape, and with first and second electrodes formed over entire length on the surface of this pn junction layer; wherein the two electrodes respectively function as inductors and by using the pn junction layer with reverse bias, a distributed constant type capacitor is formed between these inductors, thereby providing excellent attenuation characteristics over a wide band, a semiconductor device including the LC element, and a method of manufacturing the LC element.

Abstract: A differential analog memory cell provides output signals governed by precisely adjustable voltage levels having minimal drift. The memory cell comprises a pair of differentially connected floating gate MOSFETs, each MOSFET having its source connected to a common current source and its drain connected to one leg of a current mirror. The floating gate of each MOSFET is connected to one electrode of a tunneling capacitor and one electrode of a coupling capacitor. Voltages applied to the other electrode of the tunneling capacitor inject charges onto the corresponding floating gate, the voltage of which is determined by the size of the coupling capacitor. Output voltages taken from the drains of the floating gate MOSFETs can be precisely adjusted up or down by applying single polarity voltage pulses to one or the other injector nodes.

Abstract: A SIMM (single in-line memory module) board is provided with a plurality of semiconductor memory devices which include, as a part of each memory device, a current spike leveling capacitor. The capacitor is on the die side of circuitry connecting the memory device to the board. By connecting the on-chip capacitors of the memory devices in parallel, sufficient capacitance is provided to stabilize current to all of the memory devices.

Abstract: A method for producing a semiconductor memory device including a volatile memory element, a non-volatile memory element, and a driver in combination on a silicon conductive substrate is provided. The volatile memory element is a DRAM and is disposed in and on a reverse-conductive well. A charge storage electrode layer of the DRAM is partly disposed on a transfer gate electrode layer with an insulating film sandwiched therebetween. The non-volatile memory element is a mask read-only memory and/or a programmable read-only memory.

Abstract: An extensive network of N-channel transistor formed capacitor, with one node tie directly to V.sub.cc power bus and the other node directly V.sub.ss power bus, is implemented throughout all open space available on the whole silicon chip (memory as well as logic chip), particularly those directly underneath the metal power bus to achieve an on-chip power bus decoupling capacitor with capacitance in excess of 0.001 .mu.F.

Abstract: A variable field effect capacitive device suitable for providing different amounts of capacitance in response to control signals of different magnitudes. The device includes a pair of plate electrodes and a pair of control electrodes. A semiconductor region is located between the control electrodes. The plates each make Schottky contact to the semiconductor region to form a depletion region therein which changes shape in response to changes in the magnitude of the control signals.

Abstract: An integrated-distributed-resistive-capacitive network (100) having a high dielectric electronically-tunable semiconductor integrated capacitor. The network (100) also includes a resistive layer (126) formed on the high dielectric semiconductor integrated capacitor, to provide the distributed resistance of the network (100). External contact to the resistive portion of the network (100) is provided via a plurality of contact terminals (122A and 122B) which are coupled to the resistive layer (126).

Abstract: A voltage variable capacitor (10) has as the base substrate a silicon wafer with a layer of high resistivity semiconductor material on top of the substrate. An insulating layer (16) of a metal oxide having a dielectric constant greater than the dielectric constant of the semiconductors (12), such as zirconium titanate, is formed on top of the high resistivity layer, and a metal electrode (18) is formed on the insulating layer (16). When the electrode is energized, a depletion layer (20) is formed in the high resistivity layer. By varying the voltage applied to the electrode, the capacitance of the device is altered.

Abstract: An integrated tunable resonator (100) includes a common semiconductor carrier (110). Formed on the common semiconductor carrier (110) is an integrated voltage variable capacitor (104). A bulk acoustic wave resonator is formed on the common semiconductor carrier (110) and coupled to the voltage variable capacitor (104). In one aspect of the present invention, a thin film resonator (106) is coupled to the voltage variable capacitor (104) both of which are formed on a common semiconductor substrate (110). The combination of these three elements provide for a tunable integrated resonator (100). In another aspect of the present invention, a surface acoustic wave resonator (522), formed on a common semiconductor carrier (514), is coupled to a voltage variable capacitor (520) in order to provide a tunable resonator (500).