Abstract: A semiconductor integrated circuit device includes a p-silicon substrate, an n-buried layer formed in the substrate to divide the substrate into an upper region and a lower region, a trench formed from the surface of the substrate to the lower region of the substrate through the buried layer, and an electrode formed in the trench. The electrode forms an n-inversion layer using the buried layer as a carrier source, in the lower region of the semiconductor substrate by a field effect. The n-inversion layer constitutes a capacitor together with the electrode.

Abstract: On a silicon substrate 1 is provided a silicon oxide film 2, on which a polycrystalline silicon film 3 is formed by a low pressure CVD method at a monosilane partial pressure of no more than 10 Pa and a film formation temperature of no lower than 600.degree. C. The polycrystalline silicon film is doped with an impurity such as phosphorus in a concentration of 1.times.10.sup.20 atoms/cm.sup.3 to 1.times.10.sup.21 atoms/cm.sup.3 to form a phosphosilicate glass film 6, and after removing it, the polycrystalline silicon film is thermally oxidized in an oxidative atmosphere to form a dielectric film 5 on the surface. A polycrystalline silicon film 4 is formed on the dielectric film 5, which is treated as the oriented polycrystalline silicon film 3a to form an oriented polycrystalline silicon film 4a. The oriented polycrystalline silicon film 4a as an upper electrode and the oriented polycrystalline silicon film 3a as a lower electrode are wired to obtain a semiconductor device having a capacitor.

Abstract: An embodiment of the present invention describes a method for forming a dielectric material for a storage capacitor during fabrication of a semiconductor memory device, by: cleaning impurities from the surface of a conductive plate of the storage capacitor; forming a nitride film over the conductive plate's cleaned surface; forming a metal silicide film over the nitride film; and oxidizing the metal silicide film by rapid thermal oxide (RTO) processing. A resulting structure is a capacitor having a dielectric material that is an oxidized metal silicide film.

Abstract: A semiconductor device is provided, which is able to suppress the capacitance lowering of the capacitor due to a voltage applied across the capacitor. The device includes a well formed in a semiconductor substrate of a first conductivity type. The well is of a second conductivity type opposite to the first conductivity type. A surface area of the well is divided into at least first and second parts. The first part is of the first conductivity type and the second part is of the second conductivity type. An insulating layer is formed on the well to be contacted with the first and second parts. An electrode is formed on the insulating layer and is located over the first and second parts. The capacitor formed by the well, the insulating layer, and the electrode is equivalent to a capacitor composed by a first subcapacitor including the first part and a second subcapacitor including the second part.

Abstract: A voltage variable capacitor (10) fabricated on a semiconductor substrate (11) includes a gate structure (62) and a well (22) under the gate structure (62). A heavily doped buried layer (15) and a heavily doped contact region (31) in the semiconductor substrate (11) form a low resistance conduction path from the well (22) to a surface (17) of the semiconductor substrate (11). A multi-finger layout is used to construct the voltage variable capacitor (10). In operation, when a voltage applied across the voltage variable capacitor (10) changes, the width of depletion region in the well (22) changes, and the capacitance of the voltage variable capacitor (10) varies accordingly.

Abstract: A reduced threshold voltage (Vt) magnitude or depletion mode metal-oxide-semiconductor (MOS) capacitor capable of use in a charge pump circuit such as a substrate bias voltage generator in a dynamic random access memory (DRAM) integrated circuit. The Vt magnitude of a p-channel MOS field-effect transistor (FET) used as a capacitor is reduced by using the same ion-implantation step used to increase the Vt magnitude of an n-channel MOS FET. The Vt magnitude of an n-channel MOS FET used as a capacitor is reduced by using the same ion-implantation step used to increase the Vt magnitude of a p-channel MOS FET. By sufficiently reducing Vt magnitude, a depletion mode MOS capacitor is formed. Reduced Vt magnitude and depletion mode MOS capacitors increase the useful voltage range of the capacitor, optimizing operation at low supply voltages.

Abstract: In order to realize a multi-function sensor in which a reduction of a CMOS sensor and an addition of pixel signals are performed in a pixel portion and, further, an addition and a non-addition can be arbitrarily performed, there is provided a solid state image pickup apparatus in which charges generated by a photoelectric converting device are perfectly transferred to a floating diffusion portion through a transfer switch and a change in electric potential of the floating diffusion portion is outputted to the outside by a source-follower amplifier. A few photoelectric converting devices are connected to one floating diffusion portion through the transfer switch. One set of a few source-follower amplifiers are formed for a few pixels. The photoelectric converting device is constructed by an MOS transistor gate and a depletion layer under the gate.

Abstract: A semiconductor memory device comprises a capacitor and a transistor formed on a main surface of a semiconductor substrate and a buried layer of high impurity concentration formed in the substrate, wherein the buried layer has the same conductivity type as that of the substrate and is formed shallow under the capacitor and deep under the transistor.

Abstract: The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a first etching stopper insulating film, a first insulating interlayer, a pair of first contact holes, first buried conductive layers, a first interconnection formed on one of the first buried conductive layers, a second insulating interlayer, a second contact hole, a second buried conductive layer, and a second interconnection. The first contact holes are formed at a predetermined interval in a direction parallel to the surface of the semiconductor substrate so as to reach a semiconductor element formed on the semiconductor substrate through the first insulating interlayer and the etching stopper insulating film. The second contact hole is formed to reach the other first buried conductive layer through the second insulating interlayer corresponding to a portion above the first buried conductive layer.

Abstract: The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.

Abstract: A technique for quantifying the effect of plasma/etching during the formation of MOS transistors avoids the problems of prior techniques. A modified MOS capacitor 40 comprising a dielectric 12 separating a conductive plate 18 having a conductive sidewall 24 from a conductive substrate 10 is formed using the same or similar steps as a MOS transistor. Dielectric layer 12, such as oxide, is formed over a portion of conductive substrate 10. Conductive capacitor plate 18 is formed over a portion of the dielectric layer 12 using a plasma etch to remove unwanted material. After forming capacitor plate 18, the area of capacitor plate 18 is modified to encompass a peripheral oxide region 20. The modification consists of placing a conductive sidewall 24 of the same material as capacitor plate 18 or of other conductive materials around the periphery of capacitor plate 18.

Abstract: In a wiring and contact structure of a semiconductor device, a contact hole is formed to pass trough an interlayer insulating film and a gate oxide film and the contact hole is filled with a conductive material layer which projects from the interlayer insulating film. A first wiring layer is formed on the conductive material layer so as to partially overlap the contact hole, and an first insulating film is formed between the conductive material layer and the first wiring layer. A second insulating film having the same pattern as that of the first wiring layer is formed on the first wiring layer, and a third insulating film is formed as a side wall covering a side surface of the first wiring layer.

Abstract: The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.

Abstract: A semiconductor device according to the present invention includes on the main surface of a p substrate a storing circuit region and peripheral circuit regions. An n well surrounds a p well including the storing circuit region and a p well including the peripheral circuit regions. As a result, a capacitance element is formed in the semiconductor substrate. It is possible to miniaturize the semiconductor device, and to improve reliability of connection between elements.

Abstract: The present invention teaches a new method for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate, the dielectric is formed as an oxide/nitride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.

Abstract: Depletion layer depth and semiconductor real estate occupation area shortcomings of conventional MOS capacitor architectures that are formed on lightly doped semiconductor material are obviated by augmenting the MOS capacitor structure with a pair of opposite conductivity type, high impurity concentration regions, both of which are directly contiguous with the lightly doped lower plate layer that underlies the capacitor's dielectric layer, and connecting both of these auxiliary heavily doped regions to a common capacitor electrode terminal for the lower plate of the capacitor. If a high negative charge is applied to the upper plate overlying the thin dielectric layer, holes are readily supplied by the auxiliary P+ region. Conversely, if a high positive charge be applied to the upper plate, electrons are readily supplied by the auxiliary N+ region. By connecting both the auxiliary N+ and P+ regions together, a deep depletion condition is prevented for either polarity of the applied voltage.

Abstract: A single polysilicon layer electrically programmable and electrically erasable read only memory cell is described. The cell utilizes an n-well inversion capacitor, formed in a semiconductor substrate as the control gate. One plate of the capacitor is formed from the same polysilicon layer as the floating gate of the memory device, thus capacitively coupling the floating gate and the inversion capacitor control gate. Additional erase performance is achieved by addition of a dedicated erase capacitor to the basic cell. Still further improvement in programming performance and protection against over-erase failure in a flash type EEPROM device is achieved by the addition of a select transistor. Prevention of program disturb and DC erase is also described.