With Means To Prevent Sub-surface Currents, Or With Non-uniform Channel Doping Patents (Class 257/345)
  • Patent number: 10950719
    Abstract: A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: March 16, 2021
    Assignee: Cree, Inc.
    Inventors: Vipindas Pala, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour, Edward Robert Van Brunt
  • Patent number: 10943994
    Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: March 9, 2021
    Assignee: Shanhai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Yulong Yang, Zhengrong Chen, Haofeng Shen
  • Patent number: 10944011
    Abstract: A display apparatus includes a base substrate, an active pattern on the base substrate including a source region, a drain region, and a channel region that is doped between the source region and the drain region, the channel region including polycrystalline silicon, and a gate electrode overlapping the channel region of the active pattern. The channel region may include a lower portion, an upper portion, and an intermediate portion between the upper portion and the lower portion, and a dopant density of the lower portion may be 80% or more of a dopant density of the upper portion.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Hoon Yang, Kibum Kim, Jongjun Baek, Byung Soo So, Jong chan Lee, Woong Hee Jeong, Jaewoo Jeong
  • Patent number: 10892349
    Abstract: Electronic apparatus, systems, and methods in a variety of applications can include a fin field effect transistor (FinFET) having a deposited fin body. Such a FinFET can be implemented as an access transistor in a circuit of an integrated circuit. In an embodiment, an array of FinFETs having a deposited fin bodies can be disposed on digitlines. For the array of FinFETs having a deposited fin bodies structured in memory cells of a memory, the digitlines can be coupled to sense amplifiers. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10886396
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: January 5, 2021
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10847645
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SiC) MOSFET device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 24, 2020
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10809806
    Abstract: A touch sensitive device comprising a touch surface, a force exciter coupled to the touch surface to excite vibration in the surface in response to a signal sent to the exciter, with the touch surface and exciter together forming a coupled system and a signal generator to generate the signal, with the signal generator generating a carrier wave signal at frequencies within the frequency bandwidth of the coupled system and modulating the carrier wave signal with a complex modulation where the modulated carrier wave signal has a time response comparable to that of a low frequency signal which produces a desired haptic sensation whereby a user touching the touch surface excited by the exciter in response to the modulated carrier wave signal experiences the desired haptic sensation which is perceived at a frequency below the frequency bandwidth of the coupled system.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: October 20, 2020
    Assignee: Google LLC
    Inventors: Neil John Harris, Martin Colloms
  • Patent number: 10797172
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 6, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang, Michael A. Stuber, Dylan J. Kelly, Clint L. Kemerling, George Imthurn, Mark L. Burgener, Robert B. Welstand
  • Patent number: 10714623
    Abstract: Device architectures for a Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor (SOI-MOSFET) were defined. They incorporated configurations of Body-Tied-Source that drastically increased the conductance that an Impact-Ionizations current sees from the body of an SOI-MOSFET. This consequently permitted the SOI-MOSFET to effectively operate at far higher operating biases.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: July 14, 2020
    Inventor: Ahmad Houssam Tarakji
  • Patent number: 10643903
    Abstract: An optical mode converter and method of fabricating the same from wafer including a double silicon-on-insulator layer structure. The method comprising: providing a first mask over a portion of a device layer of the DSOI layer structure; etching an unmasked portion of the device layer down to at least an upper buried oxide layer, to provide a cavity; etching a first isolation trench and a second isolation trench into a mode converter layer, the mode converter layer being: on an opposite side of the upper buried oxide layer to the device layer and between the upper buried oxide layer and a lower buried oxide layer, the lower buried oxide layer being above a substrate; wherein the first isolation trench and the second isolation trench define a tapered waveguide; filling the first isolation trench and the second isolation trench with an insulating material, so as to optically isolate the tapered waveguide from the remaining mode converter layer; and regrowing the etched region of the device layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 5, 2020
    Assignee: Rockley Photonics Limited
    Inventors: John Drake, Damiana Lerose, Henri Nykänen
  • Patent number: 10629733
    Abstract: A method and apparatus for use in improving linearity sensitivity of MOSFET devices having an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to address degradation in second- and third-order intermodulation harmonic distortion at a desired range of operating voltage in devices employing an accumulated charge sink.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 21, 2020
    Assignee: pSemi Corporation
    Inventors: Christopher N. Brindle, Jie Deng, Alper Genc, Chieh-Kai Yang
  • Patent number: 10600918
    Abstract: Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2? of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: March 24, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Toshihiko Takeuchi, Yasumasa Yamane
  • Patent number: 10586863
    Abstract: Provided are a low-cost semiconductor device manufacturing method and a semiconductor device made using the method. The method includes forming multiple body regions in a semiconductor substrate, forming multiple gate insulating layers and multiple gate electrodes in the body region; implementing a blanket ion implantation in an entire surface of the substrate to form a low concentration doping region (LDD region) in the body region without a mask, forming a spacer at a side wall of the gate electrode, and implementing a high concentration ion implantation to form a high concentration source region and a high concentration drain region around the LDD region. According to the examples, devices have favorable electrical characteristics and at the same time, manufacturing costs are reduced. Since, when forming high concentration source region and drain regions, tilt and rotation co-implants are applied, an LDD masking step is potentially omitted.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: March 10, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Francois Hebert, Yon Sup Pang, Yu Shin Ryu, Seong Min Cho, Ju Ho Kim
  • Patent number: 10361283
    Abstract: MOS transistors and fabrication methods are provided. An exemplary MOS transistor includes a gate structure formed on a semiconductor substrate. A lightly doped region is formed by a light ion implantation in the semiconductor substrate on both sides of the gate structure. A first halo region is formed by a first halo implantation to substantially cover the lightly doped region in the semiconductor substrate. A groove is formed in the semiconductor substrate on the both sides of the gate structure. Prior to forming a source and a drain in the groove, a second halo region is formed in the semiconductor substrate by a second halo implantation performed into a groove sidewall that is adjacent to the gate structure. The second halo region substantially covers the lightly doped region in the semiconductor substrate and substantially covers the groove sidewall that is adjacent to the gate structure.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: July 23, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 10312240
    Abstract: A microelectronic component is capable of being used as a memory cell. The component includes a semiconductor layer resting on an insulating layer and including a doped source region of a first conductivity type, a doped drain region of a second conductivity type, and an intermediate region, non-doped or more lightly doped, with the second conductivity type, than the drain region, the intermediate region including first and second portions respectively extending from the drain region and from the source region. An insulated front gate electrode rests on the first portion. A first back gate electrode and a second back gate electrode are arranged under the insulating layer, respectively opposite the first portion and the second portion.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: June 4, 2019
    Assignee: STMICROELECTRONICS SA
    Inventors: Hassan El Dirani, Yohann Solaro, Pascal Fonteneau
  • Patent number: 10230001
    Abstract: Disclosed are a field effect transistor and method for manufacturing the same, and a display device. The field effect transistor includes: a source and a drain which are spaced apart from each other; a semi-conductor layer arranged between the source and the drain; a first gate layer located on a side of the semi-conductor layer; and a second gate layer located on the other side of the semi-conductor layer. The field effect transistor provided by the present disclosure is less energy-consuming; a method for manufacturing the same is low costing; and a display device using the same is also less energy-consuming.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: March 12, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Hongyuan Xu, Hsiang Chih Hsiao, Chang I Su
  • Patent number: 10153343
    Abstract: A method for producing a tunnel field-effect transistor (TFET) having a source region, a channel region, and a drain region includes arranging an epitaxial layer on a silicon substrate; applying a gate arrangement having a gate electrode to the epitaxial layer, a gate dielectric being arranged between the gate electrode and the silicon substrate; forming a doped pocket region below the gate dielectric adjacent to the source region; forming a selectively silicidated region in the source region, the selectively silicidated region extending as far as to below a gate; and forming a counter-doped region doped in an opposite way to the pocket region adjacent to the pocket region in the source region by diffusion of dopants out of the silicidated region, as a result of which a tunnel junction parallel to the electric field lines of the gate electrode is achieved.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: December 11, 2018
    Assignee: FORSCHUNGSZENTRUM JUELICH GMBH
    Inventors: Qing-Tai Zhao, Siegfried Mantl, Sebastian Blaeser
  • Patent number: 10115815
    Abstract: A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: October 30, 2018
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Brett Hull
  • Patent number: 10014294
    Abstract: Provided is a constant voltage circuit having a stable output voltage. In a constant voltage circuit formed by connecting an enhancement type NMOS and a depression type NMOS in series, in order to enhance the back bias effect of the depression type NMOS, the impurity concentration is set to be high only in a P-type well region on which the depression type NMOS is arranged.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: July 3, 2018
    Assignee: ABLIC Inc.
    Inventors: Hirofumi Harada, Masayuki Hashitani
  • Patent number: 10008532
    Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate and extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and two end cap hardmasks are between the gate dielectric and the gate electrode over the implant isolation region. The two end cap hardmasks include same dopants as those implanted into the active region.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: June 26, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Wen-De Wang, Wen-I Hsu
  • Patent number: 9905426
    Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung
  • Patent number: 9881841
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: January 30, 2018
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Alban Zaka, Ran Yan, El Mehdi Bazizi, Jan Hoentschel
  • Patent number: 9853186
    Abstract: The invention relates to a light-emitting semiconductor component, comprising—a first semiconductor body (1), which comprises an active zone (11) in which during the operation of the light-emitting semiconductor component electromagnetic radiation is generated, at least some of which leaves the first semiconductor body (1) through a radiation exit surface (1a), and—a second semiconductor body (2), which is suitable for converting the electromagnetic radiation into converted electromagnetic radiation having a longer wavelength, wherein—the first semiconductor body (1) and the second semiconductor body (2) are produced separately from each other,—the second semiconductor body (2) is electrically inactive, and—the second semiconductor body (2) is in direct contact with the radiation exit surface (1a) and is attached there to the first semiconductor body (1) without connecting means.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: December 26, 2017
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Matthias Sabathil, Andreas Plöβl, Hans-Jürgen Lugauer, Alexander Linkov, Patrick Rode
  • Patent number: 9806154
    Abstract: Present disclosure provides a FinFET structure, including a fin and a gate surrounding a first portion of the fin. A dopant concentration in the first portion of the fin is lower than about 1E17/cm3. The FinFET structure further includes an insulating layer surrounding a second portion of the fin. The dopant concentration of the second portion of the fin is greater than about 8E15/cm3. The insulating layer includes a lower layer and an upper layer, and the lower layer is disposed over a substrate connecting to the fin and has a dopant concentration greater than about 1E19/cm3.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Lai-Wan Chong, Chien-Wei Lee, Kei-Wei Chen
  • Patent number: 9590207
    Abstract: A deposition apparatus is configured to form a deposition layer on a substrate. The deposition apparatus includes a deposition source configured to face a first side of the substrate and to spray one or more depositing materials toward the substrate, a cooling stage configured to support a second side of the substrate that is opposite from the first side of the substrate, and a hardening unit configured to harden the one or more depositing materials sprayed from the deposition source and that have reached the substrate. A method of forming a thin film deposition layer on a substrate by using a deposition apparatus is also provided. The method includes spraying one or more depositing materials toward the substrate by using a deposition source of the deposition apparatus while the substrate is on a cooling stage of the deposition apparatus.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: March 7, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myung-Soo Huh, Sun-Ho Kim, Hyun-Woo Joo, Jae-Hyun Kim
  • Patent number: 9590106
    Abstract: A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jie Deng, Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9564504
    Abstract: A manufacturing method according to an embodiment of this invention is a method of manufacturing a semiconductor device, which has: a first step of forming a first electrode 22 containing Ti or Ta on a top face of a nitride semiconductor layer 18; a second step of forming a second electrode 24 containing Al on a top face of the first electrode 22; a third step of forming a coating metal layer 26 covering at least one of an edge of a top face of the second electrode 24 and a side face of the second electrode 24, having a window 26a exposing the top face of the second electrode 24 in a region separated from the foregoing edge, and containing at least one of Ta, Mo, Pd, Ni, and Ti; and a step of performing a thermal treatment, after the third step.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: February 7, 2017
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Masahiro Nishi
  • Patent number: 9553202
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: January 24, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Patent number: 9484417
    Abstract: Methods of forming doped transition regions of transistor structures are provided herein. The methods include, for instance: providing a first semiconductor material including a dopant over a source/drain region of the transistor structure; providing a second semiconductor material including the dopant over the first semiconductor material, where the second semiconductor material is different from the first semiconductor material; and, where providing the second semiconductor material is performed at a temperature sufficient to diffuse the dopant from the first semiconductor material through the source/drain region into a portion of a channel region of the transistor structure. The portion of the channel region into which the dopant from the first semiconductor material diffuses forms the doped transition region.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xusheng Wu, Manfred Eller
  • Patent number: 9478551
    Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 25, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hun Kim, Ju-Youn Kim, Koung-Min Ryu, Jong-Mil Youn, Jong-Ho Lee
  • Patent number: 9437500
    Abstract: A semiconductor device and a method for making the semiconductor device are provided. The semiconductor device includes a non-volatile memory cell having a gate dielectric and formed in a non-volatile memory well region; a first transistor type formed using a first gate oxide and formed in a first transistor well region; a second transistor type formed using a second gate oxide and formed in a second transistor well region; and a third transistor type formed using a third gate oxide and formed in a third transistor well region. The gate dielectric and the first and second gate oxides are formed from the same oxide stack. The first, second, and third transistor types include extension implants formed using a first implant dopant, and the non-volatile memory cell includes extension implants formed using a second implant dopant, where the first and second implant dopants are different.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Cheong Min Hong
  • Patent number: 9397184
    Abstract: A semiconductor device having metal gate includes a substrate, a metal gate positioned on the substrate, a high-k gate dielectric layer, and an epitaxial channel layer positioned in between the high-k gate dielectric layer and the substrate. A length of the epitaxial channel layer is larger than a length of the metal gate, and a bottom of the epitaxial channel layer and the substrate are coplanar.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: July 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yong Tian Hou
  • Patent number: 9269714
    Abstract: A device includes a substrate, a P-channel transistor and an N-channel transistor. The substrate includes a first layer of a first semiconductor material and a second layer of a second semiconductor material. The first and second semiconductor materials have different crystal lattice constants. The P-channel transistor includes a channel region having a compressive stress in a first portion of the substrate. The channel region of the P-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. The N-channel transistor includes a channel region having a tensile stress formed in a second portion of the substrate. The channel region of the N-channel transistor includes a portion of the first layer of the first semiconductor material and a portion of the second layer of the second semiconductor material. Methods of forming the device are also disclosed.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: February 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Gerd Zschaezsch
  • Patent number: 9263272
    Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Feng-Chi Hung
  • Patent number: 9263588
    Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 16, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Hun-Hyeoung Leam, Tae-Hyun Kim, Seok-Woo Nam, Hyun Namkoong, Yong-Seok Kim, Tea-Kwang Yu
  • Patent number: 9219177
    Abstract: The photo detector (100, 300, 500, 600, 700, 900) comprises a photo transistor (102, 902). The photo transistor has a light sensitive region (112, 910) for controlling the transistor action of the photo transistor. The photo detector further comprises a dielectric layer (118). The dielectric layer is in contact with the photo transistor. The photo detector further comprises a grating pattern (114, 604, 914, 1010) in contact with the dielectric layer. The grating layer and the dielectric layer are adapted for focusing electromagnetic radiation in the light sensitive region.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: December 22, 2015
    Assignee: International Business Machines Corporation
    Inventors: Matthias Fertig, Nikolaj Moll, Thomas Morf, Thomas Pflueger
  • Patent number: 9209212
    Abstract: Provided is an image sensor including a source follower transistor. The source follower transistor may include a channel structure that is provided between a source and a drain, and includes a first semiconductor layer, a second semiconductor layer, and a blocking structure. The first semiconductor layer may be spaced apart from a gate insulating layer of the source follower transistor by a first depth or more. Carriers may move from the source of the source follower transistor to the drain thereof through the first semiconductor layer.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hirosige Goto
  • Patent number: 9105493
    Abstract: A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region further includes a plurality of third doped regions, a plurality of gaps, and a plurality of fourth doped regions. The gaps and the third doped regions s are alternately arranged, and the fourth doped regions are formed in the gaps. The third doped regions include a second conductivity type complementary to the first conductivity type, and the fourth doped regions include the first conductivity type.
    Type: Grant
    Filed: May 21, 2012
    Date of Patent: August 11, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Tsung Lee, Cheng-Hua Yang, Wen-Fang Lee, Chih-Chung Wang, Te-Yuan Wu
  • Patent number: 9041104
    Abstract: A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: May 26, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Emiko Sugizaki, Shigeru Kawanaka, Kanna Adachi
  • Patent number: 9029946
    Abstract: A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region overlying a first major surface, a control electrode coupled to a control electrode interconnection region overlying the first major surface, and a second electrode coupled to a second electrode interconnection region overlying a second major surface. Each transistor cell has an approximately constant doping concentration in the channel region. A dielectric platform is used as an edge termination of an epitaxial layer to maintain substantially planar equipotential lines therein. The power transistor finds particular utility in radio frequency applications operating at a frequency greater than 500 megahertz and dissipating more than 5 watts of power. The semiconductor die and package are designed so that the power transistor can efficiently operate under such severe conditions.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Estivation Properties LLC
    Inventor: Robert Bruce Davies
  • Patent number: 8994107
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: El Mehdi Bazizi, Francis Benistant
  • Publication number: 20150084127
    Abstract: High integrity, lower power consuming semiconductor devices and methods for manufacturing the same. The semiconductor device includes: semiconductor substrate; a well region in the semiconductor substrate; an interlayer structure over the well region, the interlayer structure including a back gate conductor, semiconductor fins at both sides of the back gate conductor and respective back gate dielectric isolating the back gate conductor from the semiconductor fins, respectively, wherein the well region functions as one portion of a conductive path of the back gate conductor; a punch-through stop layer at a lower portion of the semiconductor fin; a front gate stack intersecting the semiconductor fin, the front gate stack including a front gate dielectric and a front gate conductor and the front gate dielectric isolating the front gate conductor from the semiconductor fin; and a source region and a drain region connected to a channel region provided by the semiconductor fin.
    Type: Application
    Filed: March 19, 2013
    Publication date: March 26, 2015
    Inventor: Huilong Zhu
  • Patent number: 8928093
    Abstract: A semiconductor device may include body contacts on a finFET device for ESD protection. The semiconductor device comprises a semiconductor fin, a source/drain region and a body contact. The source/drain region and the body contact are in the semiconductor fin. A portion of the fin is laterally between the source/drain region and the body contact. The semiconductor fin is on a substrate.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Hsiung Lo, Jam-Wem Lee, Wun-Jie Lin, Jen-Chou Tseng
  • Patent number: 8921937
    Abstract: The present invention provides a high voltage metal-oxide-semiconductor transistor device including a substrate, a deep well, and a doped region. The substrate and the doped region have a first conductive type, and the substrate has at least one electric field concentration region. The deep well has a second conductive type different from the first conductive type. The deep well is disposed in the substrate, and the doped region is disposed in the deep well. The doping concentrations of the doped region and the deep well in the electric field have a first ratio, and the doping concentrations of the doped region and the deep well outside the electric field have a second ratio. The first ratio is greater than the second ratio.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chung Wang, Wei-Lun Hsu, Shan-Shi Huang, Ke-Feng Lin, Te-Yuan Wu
  • Publication number: 20140361367
    Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Hua-Chou TSENG, Chien-Chih HO
  • Patent number: 8906753
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: December 9, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Publication number: 20140346598
    Abstract: In one embodiment, method of making a high voltage PMOS (HVPMOS) transistor, can include: (i) providing a P-type substrate; (ii) implanting N-type dopants in the P-type substrate; (iii) dispersing the implanted N-type dopants in the P-type substrate to form a deep N-type well; (iv) implanting P-type dopants of different doping concentrations in the deep N-type well along a horizontal direction of the deep N-type well; and (v) dispersing the implanted P-type dopants to form a composite drift region having an increasing doping concentration and an increasing junction depth along the horizontal direction of the deep N-type well.
    Type: Application
    Filed: May 14, 2014
    Publication date: November 27, 2014
    Applicant: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Chenggong Han
  • Patent number: 8884368
    Abstract: Some embodiments include transistors having a channel region under a gate, having a source/drain region laterally spaced from the channel region by an active region, and having one or more dielectric features extending through the active region in a configuration which precludes any straight-line lateral conductive path from the channel region to the source/drain region. The dielectric features may be spaced-apart islands in some configurations. The dielectric features may be multi-branched interlocking structures in some configurations.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Michael A. Smith
  • Patent number: 8860136
    Abstract: A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Till Schloesser
  • Patent number: 8809940
    Abstract: A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Shin-Yeh Huang, Shu-Tine Yang, Hung-Ming Chen