Short Channel Insulated Gate Field Effect Transistor Patents (Class 257/327)
  • Patent number: 11107884
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: August 31, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Siva P. Adusumilli, Anthony K. Stamper, Laura J. Silverstein, Cameron E. Luce
  • Patent number: 11088275
    Abstract: A method for operating a superjunction transistor device and a transistor arrangement are disclosed. The method includes operating the superjunction transistor device in a diode state. Operating the superjunction transistor device in the diode state includes applying a bias voltage different from zero between a drift region of at least one transistor cell of the superjunction transistor device and a compensation region of a doping type complementary to a doping type of the drift region. The compensation region adjoins the drift region, and a polarity of the bias voltage is such that a pn-junction between the drift region and the compensation region is reverse biased.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: August 10, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Matteo-Alessandro Kutschak, Andreas Riegler
  • Patent number: 11075284
    Abstract: A semiconductor structure and a forming method thereof are provided. One form of the forming method includes: providing a base, where a well region and a drift region adjacent to the well region are formed in the base; forming a trench in the drift region; forming a diffusion barrier layer in the trench; after the diffusion barrier layer is formed, forming a gate structure on the base at a junction between the well region and the drift region, where the gate structure is located on a side of the diffusion barrier layer near the well region; and forming a source region in the well region on one side of the gate structure, and forming a drain region in the drift region on the other side of the gate structure, where the drain region is located on a side of the diffusion barrier layer in the drift region away from the well region.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Zhaomeng
  • Patent number: 11075295
    Abstract: A metal-oxide-semiconductor field-effect transistor includes a wide bandgap substrate, a wide bandgap drift layer over the substrate, a number of junction implants in the drift layer, and a JFET region between the junction implants. The JFET region is defined by a JFET gap, which is the distance between adjacent ones of the junction implants. The JFET gap is not uniform throughout the MOSFET device. The JFET region is separated into a first JFET sub-region and a second JFET sub-region, such that a doping concentration in the first JFET sub-region is different from a doping concentration in the second JFET sub-region.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: July 27, 2021
    Assignee: Cree, Inc.
    Inventor: Sei-Hyung Ryu
  • Patent number: 11075108
    Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
  • Patent number: 11049938
    Abstract: A PLDMOS transistor includes a substrate, a P-type drift region disposed on an upper surface of the substrate, a first body region of N-type conductivity, the first body region being disposed on one side of the drift region and having a channel region formed thereon, a drain extension region of P-type conductivity, the drain extension region being disposed on another side of the drift region and being spaced apart from the first body region, a P-type drain region disposed on the drain extension region, a gate structure disposed on the channel region, an N-type buried layer disposed under the drift region and first and second breakdown voltage increasing layers being configured to increase the breakdown voltage by providing reduced surface fields.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 29, 2021
    Assignee: DB HITEK CO., LTD.
    Inventor: Chang Eun Lee
  • Patent number: 11031395
    Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tetsu Ohtou, Ching-Wei Tsai, Jiun-Jia Huang, Kuan-Lun Cheng, Chi-Hsing Hsu
  • Patent number: 11018002
    Abstract: A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 25, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 11018131
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Patent number: 11011556
    Abstract: A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Victor Chiang Liang, Fu-Huan Tsai, Fang-Ting Kuo, Meng-Chang Ho, Yu-Lin Wei, Chi-Feng Huang
  • Patent number: 10971216
    Abstract: A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 6, 2021
    Assignee: Microsemi SoC Corp.
    Inventors: Jonathan W. Greene, John McCollum
  • Patent number: 10937910
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure and a gate spacer formed on a sidewall surface of the gate structure. The semiconductor structure also includes a first source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate spacer, and a second S/D epitaxial layer formed over the first S/D epitaxial layer. A top surface of the second S/D layer is higher than a top surface of the first S/D epitaxial layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 10886386
    Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: January 5, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventor: Qing Liu
  • Patent number: 10854747
    Abstract: Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Chris M. Carlson, Hung-Wei Liu, Jie Li, Dimitrios Pavlopoulos
  • Patent number: 10818750
    Abstract: A semiconductor device includes a semiconductor part including first to fifth layers; an electrode on a front surface of the semiconductor part; first and second control electrodes between the semiconductor part and the electrode. The first layer includes first and second portions alternately arranged along the front surface of the semiconductor part. The second layer is positioned between the first and second portions of the first layer. The first and second control electrodes are placed at boundaries of the first and second portions and the second layer, respectively. The third layer is provided between the second electrode and the first and second portions of the first layer. The fourth and fifth layers are selectively provided between the third layer and the second electrode. The first control electrode is opposed to the first, third and fourth layers. The second control electrode is opposed to the first, third and fifth layers.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: October 27, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Yamashita, Syotaro Ono, Hisao Ichijo, Takafumi Koumoto
  • Patent number: 10804403
    Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daewon Ha, Seungseok Ha, Byoung Hak Hong
  • Patent number: 10790370
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a first semiconductor fin that extends from a substrate. The first semiconductor fin has source and drain regions, which are separated from one another by a channel region in the first semiconductor fin. A gate overlies an upper surface and sidewalls of the channel region. A contact is coupled to the source or drain region of the first semiconductor fin, where the source or drain region includes a layer of epitaxial material with a substantially diamond-shaped cross-section. The contact surrounds the source or drain region on top and bottom surfaces of the substantially diamond-shaped cross-section. A first capping material is arranged along outer sidewalls of the first semiconductor fin under the contact. The first capping material has an uppermost surface that is spaced below a lowermost surface of the contact by a non-zero distance.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chan Syun David Yang
  • Patent number: 10770296
    Abstract: Exposure of a gate conductive film covered by an interlayer insulation film in a unit cell portion is reduced when a gate contact region is formed. A method of manufacturing a semiconductor device includes forming a gate conductive film to come in contact with a gate oxide film in a unit cell portion, forming a gate wire to come in contact with the gate oxide film in a termination region, forming a first insulation film on an upper surface of the gate wire in the termination region, subjecting an upper surface of the gate conductive film in the unit cell portion to thermal oxidation with use of the first insulation film as a mask to form a thermal oxide film on the upper surface of the gate conductive film, and forming a second insulation film covering the first insulation film and the thermal oxide film.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeshi Murakami
  • Patent number: 10749038
    Abstract: In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Ruilong Xie, Tenko Yamashita
  • Patent number: 10741646
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 10727340
    Abstract: A p-type field effect transistor includes a pair of spacers over a substrate top surface. The p-type field effect transistor includes a channel recess cavity in the substrate top surface between the pair of spacers. The p-type field effect transistor includes a gate stack with a bottom portion in the channel recess cavity. The p-type field effect transistor includes a source/drain (S/D) recess cavity including a bottom surface and sidewalls below the substrate top surface, wherein the S/D recess cavity includes a portion extending below the gate stack. The p-type field effect transistor includes a strained material filling the S/D recess cavity. The p-type field effect transistor further includes a source/drain (S/D) extension substantially conformably surrounding the bottom surface and sidewalls of the S/D recess cavity. The S/D extension includes a portion between the gate stack and the S/D recess cavity.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Fai Cheng, Ka-Hing Fung, Li-Ping Huang, Wei-Yuan Lu
  • Patent number: 10727647
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Acorn Semi, LLC
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 10727307
    Abstract: A display substrate and a fabrication method thereof, and a display device are disclosed. The fabrication method of a display substrate, includes forming a first gate electrode on a transparent base substrate; forming a transparent gate insulating layer on the first gate electrode; forming a transparent active layer on the transparent gate insulating layer; forming a transparent source electrode and a transparent drain electrode on the transparent active layer, wherein, the transparent source electrode and the transparent drain electrode do not overlap with the first gate electrode in a thickness direction of the transparent base substrate.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: July 28, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiaming Zhu
  • Patent number: 10714472
    Abstract: Semiconductor devices may include a substrate, gate electrodes on the substrate, and source/drain regions at both sides of each of the gate electrodes. Each of the gate electrodes may include a gate insulating pattern on the substrate, a lower work-function electrode pattern that is on the gate insulating pattern and has a recessed upper surface, and an upper work-function electrode pattern that conformally extends on the recessed upper surface of the lower work function electrode pattern. Topmost surfaces of the lower work-function electrode patterns may be disposed at an equal level, and the upper work-function electrode patterns may have different thicknesses from each other.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kee Sang Kwon, Boun Yoon, Sangjine Park, Myunggeun Song, Ki-Hyung Ko, Jiwon Yun
  • Patent number: 10693009
    Abstract: A semiconductor device includes a fin feature in a substrate, a stack of semiconductor layers over the fin feature. Each of the semiconductor layers does not contact each other. The device also includes a semiconductor oxide layer interposed between the fin feature and the stack of the semiconductor layers. A surface of the semiconductor oxide layer contacts the fin feature and an opposite surface of the semiconductor oxide layer contacts a bottom layer of the stack of semiconductor layers. The device also includes a conductive material layer encircling each of the semiconductor layers and filling in spaces between each of two semiconductor layers.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chun-Hsiang Fan
  • Patent number: 10685889
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate including a core region and a peripheral region, forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10680109
    Abstract: A device includes a semiconductor substrate, a first fin arranged over the semiconductor substrate, and an isolation structure. The first fin includes an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion. A top surface of the insulator layer is wider than a bottom surface of the upper portion of the first fin. The isolation structure surrounds the bottom portion of the first fin.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Hao Kuo, Jung-Hao Chang, Chao-Hsien Huang, Li-Te Lin, Kuo-Cheng Ching
  • Patent number: 10658484
    Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10658483
    Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10644101
    Abstract: A level shifter is provided. The level shifter is located between a high-side circuit area and a low-side circuit area and includes a substrate, a buried island, and an isolation structure. The buried island has a first conductivity type and is located in the substrate. The isolation structure has a second conductivity type, is located in the substrate and surrounds the buried island. In addition, a dimension of the isolation structure near the high-side circuit area is different from a dimension of the isolation structure near the low-side circuit area. A semiconductor device including the level shifter is also provided.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 5, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Md Imran Siddiqui, Po-An Chen
  • Patent number: 10629726
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Patent number: 10586858
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a strained channel, including forming one or more vertical fins on a substrate, forming a sacrificial stressor layer adjacent to the one or more vertical fins, wherein the sacrificial stressor layer imparts a strain in the adjacent vertical fins, forming a fin trench through one or more vertical fins and the sacrificial stressor layer to form a plurality of fin segments and a plurality of sacrificial stressor layer blocks, forming an anchor wall adjacent to and in contact with one or more fin segment endwalls, and removing at least one of the plurality of the sacrificial stressor layer blocks, wherein the anchor wall maintains the strain of the adjacent fin segments after removal of the sacrificial stressor layer blocks adjacent to the fin segment with the adjacent anchor wall.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10586853
    Abstract: Non-planar field effect transistor (FET) devices having wrap-around source/drain contacts are provided, as well as methods for fabricating non-planar FET devices with wrap-around source/drain contacts. A method includes forming a non-planar FET device on a substrate, which includes a semiconductor channel layer, and a gate structure in contact with upper and sidewall surfaces of the semiconductor channel layer. First and second source/drain regions are formed on opposite sides of the gate structure in contact with the semiconductor channel layer. First and second recesses are formed in an isolation layer below bottom surfaces of the first and second source/drain regions, respectively. A layer of metallic material is deposited to fill the first and second recesses in the isolation layer with metallic material and form first and second source/drain contacts which surround the first and second source/drain regions.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10573751
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 10546865
    Abstract: The reliability of a semiconductor device is improved. A control gate electrode and a memory gate electrode for memory cell of a nonvolatile memory, a first gate electrode and a dummy gate electrode for peripheral circuit are formed. Then, a first insulation film is formed so as to cover them. The gate length of the first gate electrode is larger than the gate length of the control gate electrode. Then, an opening is formed in the first insulation film, to etch and reduce the height of the first gate electrode exposed from the opening. Thereafter, over the first insulation film, an insulation film is formed. Then, the insulation film is polished, to expose the control gate electrode, the memory gate electrode, the first gate electrode, and the dummy gate electrode. Then, the dummy gate electrode is removed. A gate electrode is formed in the removal region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shigeki Katou
  • Patent number: 10535733
    Abstract: A sacrificial gate stack for forming a nanosheet transistor includes a substrate. first, second and third silicon channel nanosheets formed over the substrate, and a first sandwich of germanium (Ge) containing layers disposed between the substrate and first silicon channel nanosheet. The stack also includes a second sandwich of Ge containing layers disposed between the first silicon channel nanosheet and the second silicon channel nanosheet; and a third sandwich of Ge containing layers disposed between the second silicon channel nanosheet and the third silicon channel nanosheet. Each sandwich includes first and second low Ge containing layers surrounding a silicon germanium (SiGe) sacrificial nanosheet that has a higher Ge concentration than the first and second low Ge containing layers.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Peng Xu
  • Patent number: 10514357
    Abstract: A chemical sensor is described having a substrate comprising a plurality of nanoribbons of an active layered nanomaterial, and a substance detection component for measuring a change in electrical or physical properties of at least a portion of the plurality of nanoribbons when in contact with a substance.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 24, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Avetik Harutyunyan, Gugang Chen
  • Patent number: 10516047
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure also includes a gate stack structure in the dielectric layer. The semiconductor device structure further includes a semiconductor wire partially surrounded by the gate stack structure. In addition, the semiconductor device structure includes a contact electrode in the dielectric layer and electrically connected to the semiconductor wire. The contact electrode and the gate stack structure extend from the semiconductor wire in opposite directions.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kam-Tou Sio, Jiann-Tyng Tzeng, Charles Chew-Yuen Young, Yi-Ming Sheu, Chun-Fu Cheng, Yi-Han Wang
  • Patent number: 10468329
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: November 5, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10468530
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer and a source/drain structure. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The source/drain structure includes a first source/drain epitaxial layer and a second source/drain epitaxial layer. The first source/drain epitaxial layer is in contact with the fin structure. The first source/drain epitaxial layer is connected to a portion of the second source/drain epitaxial layer below a top surface of the fin structure. The lattice constant of the first source/drain epitaxial layer is different from the lattice constant of the second source/drain epitaxial layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Wang, Yu-Ting Lin, Yueh-Ching Pai, Shih-Chieh Chang, Huai-Tei Yang
  • Patent number: 10453933
    Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
  • Patent number: 10453754
    Abstract: The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 22, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jianwei Peng, Haigou Huang, Qun Gao, Xin Wang
  • Patent number: 10446650
    Abstract: A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: October 15, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Ali Khakifirooz
  • Patent number: 10446655
    Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
  • Patent number: 10431523
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 1, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10431696
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate including a first fin portion and a first nanowire over the first fin portion. The first nanowire has a polygonal cross-section. The semiconductor device structure also includes a first gate structure surrounding the first nanowire, and two first source/drain portions adjacent to the first nanowire.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wilman Tsai, Cheng-Hsien Wu, I-Sheng Chen, Stefan Rusu
  • Patent number: 10424611
    Abstract: An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: September 24, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hisanori Ihara
  • Patent number: 10403738
    Abstract: Methods for forming three-dimensional transistor devices. In one embodiment a method of forming a three-dimensional transistor device may include providing a substrate comprising a semiconductor device structure, the semiconductor device structure comprising a nanowire stack, a gate stack disposed above the nanowire stack, and an inner spacer layer, disposed over the gate stack and the nanowire stack. The method may further include directing ions at the semiconductor device structure, wherein an altered layer is formed in a first part of the inner spacer layer, and an unaltered portion of the inner spacer layer remains, subjacent to the altered layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 3, 2019
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Min Gyu Sung, Rajesh Prasad, John Hautala, Sony Varghese
  • Patent number: 10381289
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10373956
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins