Short Channel Insulated Gate Field Effect Transistor Patents (Class 257/327)
  • Patent number: 10381289
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 13, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10373956
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 10361310
    Abstract: A method of fabricating a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, removing the sacrificial gate pattern to form a gap region exposing the active fin, and forming a separation region in the active fin exposed by the gap region. Forming the separation region includes forming an oxide layer in the exposed active fin and forming an impurity regions with impurities implanted into the exposed active fin.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Daewon Ha, Seungseok Ha, Byoung Hak Hong
  • Patent number: 10361297
    Abstract: A semiconductor epitaxial wafer includes a semiconductor wafer, and a semiconductor layer of a first conductivity type disposed on a main surface of the semiconductor wafer. The semiconductor epitaxial wafer includes a plurality of device regions. The plurality of device regions each include a body region of a second conductivity type in contact with the semiconductor layer, a source region of the first conductivity type in contact with the body region, and a channel layer that is constituted by a semiconductor, and that is disposed on the semiconductor layer so as to be in contact with at least a part of the body region. In a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the first conductivity type impurity in the channel layer are negatively correlated to each other.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: July 23, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Tsutomu Kiyosawa
  • Patent number: 10361268
    Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 23, 2019
    Assignee: IMEC VZW
    Inventors: Kurt Wostyn, Hans Mertens, Liesbeth Witters, Andriy Hikavyy, Naoto Horiguchi
  • Patent number: 10355133
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a stacked wire structure over a substrate and forming a gate structure across middle portions of the stacked wire structure. A trench can be formed by removing the gate structure, in which a middle portion of the stacked wire structure is exposed. The method further includes removing a portion of the stacked wire structure to form a recess and forming a source/drain (S/D) structure at two opposite sides of the stacked wire structure, where the S/D structure is formed by an epitaxial process and includes a top surface, a sidewall surface, and a rounded corner between the top surface and the sidewall surface.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Wu, Chih-Chieh Yeh, Yee-Chia Yeo
  • Patent number: 10355082
    Abstract: A third dummy trench (11) is orthogonal to the first and second dummy trenches (9,10) in the dummy cell region of a substrate end portion. An interlayer insulating film (13) insulates the p-type diffusion layer (3,4) in the dummy cell region of a substrate center portion situated between the first and second dummy trenches (9,10) from the emitter electrode (14). The third dummy trench (11) separates the p-type diffusion layer (3,4) in the dummy cell region of the substrate center portion from the p-type diffusion layer (3,4,15) in the dummy cell region of the substrate end portion connected to the emitter electrode (14). A p-type well layer (15) is provided deeper than the third dummy trench (11) in the substrate end portion. The third dummy trench (11) is provided closer to a center of the n-type substrate than the p-type well layer (15).
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: July 16, 2019
    Assignee: Mitsubishi Electronic Corporation
    Inventors: Tomohito Kudo, Yoshihumi Tomomatsu, Hideki Haruguchi, Yasuo Ata
  • Patent number: 10347742
    Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 9, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton Villiers
  • Patent number: 10340369
    Abstract: A tunneling field effect transistor device disclosed herein includes a substrate, a body comprised of a first semiconductor material being doped with a first type of dopant material positioned above the substrate, and a second semiconductor material positioned above at least a portion of the gate region and above the source region. The first semiconductor material is part of the drain region, and the second semiconductor material defines the channel region. The device also includes a third semiconductor material positioned above the second semiconductor material and above at least a portion of the gate region and above the source region. The third semiconductor material is part of the source region, and is doped with a second type of dopant material that is opposite to the first type of dopant material. A gate structure is positioned above the first, second and third semiconductor materials in the gate region.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Bartlomiej Jan Pawlak
  • Patent number: 10340202
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 2, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10332833
    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 25, 2019
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Zhuowen Sun
  • Patent number: 10315416
    Abstract: An ink-jet head driving circuit includes: PMOS transistors each of which has an Nwell area, a drain terminal and a source terminal, the PMOS transistors connected to a piezoelectric element for jetting ink from a nozzle; and an NMOS transistor connected to the drain terminals of the PMOS transistors. The source terminals and Nwell areas of the PMOS transistors are connected respectively to power sources, and voltage of one of the power sources connected to the Nwell area of each of the PMOS transistors is equal to or higher than the highest voltage of the power sources connected to the source terminals of the PMOS transistors.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: June 11, 2019
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Toru Yamashita
  • Patent number: 10312333
    Abstract: Fin-type semiconductor device is provided. The semiconductor device includes: a semiconductor substrate and an insulating layer on sidewalls of the plurality of fins. A plurality of fins is projected on a surface of the semiconductor substrate. The insulating layer is located on the surface of the semiconductor substrate. A surface of the insulating layer is lower than top surfaces of the plurality of fins. A thermal conductivity of the insulating layer is larger than a thermal conductivity of silicon oxide.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 4, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xinyun Xie, Ming Zhou
  • Patent number: 10304753
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 28, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10290546
    Abstract: A semiconductor structure includes a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers. The first and second semiconductor layers have different material compositions. A dummy gate stack is formed over an uppermost first semiconductor layer. A first etching process is performed to remove portions of the second semiconductor layer that are not disposed below the dummy gate stack, thereby forming a plurality of voids. The first etching process has an etching selectivity between the first semiconductor layer and the second semiconductor layer. Thereafter, a second etching process is performed to enlarge the voids.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Li Chiang, Szu-Wei Huang, Huan-Sheng Wei, Jon-Hsu Ho, Chih Chieh Yeh, Wen-Hsing Hsieh, Chung-Cheng Wu, Yee-Chia Yeo
  • Patent number: 10276661
    Abstract: A semiconductor device includes: a channel-forming region of a first conductivity type; a first main electrode region of a second conductivity type disposed in a portion of an upper part of the channel-forming region; a drift region of the second conductivity type that is disposed in an upper part of the channel-forming region apart from the first main electrode region; a second main electrode region of the second conductivity type that is disposed in a part of an upper part of the drift region; and a stopper region of the second conductivity type that is disposed at an end region of the drift region apart from the first main electrode region and has a higher concentration than the drift region. The stopper region restricts extension of a depletion layer developing at the boundary of the pn junction between the channel-forming region and the drift region.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: April 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideaki Katakura
  • Patent number: 10276660
    Abstract: A device includes a substrate, a buffer layer, a nanowire, a gate structure, and a remnant of a sacrificial layer. The buffer layer is above the substrate. The nanowire is above the buffer layer and includes a pair of source/drain regions and a channel region between the source/drain regions. The gate structure surrounds the channel region. The remnant of the sacrificial layer is between the buffer layer and the nanowire and includes a group III-V semiconductor material.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Richard Kenneth Oxland
  • Patent number: 10269680
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10269799
    Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Yan-Ming Tsai, Chung-Ting Wei, Ziwei Fang, Chih-Wei Chang, Chien-Hao Chen, Huicheng Chang
  • Patent number: 10249707
    Abstract: A laterally diffused metal oxide semiconductor field-effect transistor, comprising a substrate (110), a source electrode (150), a drain electrode (140), a body region (160), and a well region on the substrate, the well region comprising: an insertion-type well (122) having P-type doping, being arranged below the drain electrode and being connected to the drain electrode; N wells (124), arranged on two sides of the insertion-type well; and P wells (126), arranged next to the N wells and being connected to the N wells; the source electrode and the body region are arranged in the P well.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 2, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Shukun Qi
  • Patent number: 10243074
    Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: March 26, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC., STMICROELECTRONICS, INC.
    Inventors: Qing Liu, Ruilong Xie, Chun-chen Yeh
  • Patent number: 10243046
    Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn P. Fetterolf, Ahmet S. Ozcan
  • Patent number: 10236235
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 19, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10229983
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of dummy gate patterns spaced apart from each other on a substrate, growing a plurality of source/drain regions adjacent the plurality of dummy gate patterns, forming a dielectric layer on each of the plurality of source/drain regions adjacent the plurality of dummy gate patterns, removing the plurality of dummy gate patterns to create a plurality of trenches, forming a plurality of spacers on sidewalls of each of the plurality of trenches, wherein the plurality of spacers comprise at least one of a low-k material and an airgap, and forming a gate structure in each of the plurality of trenches between the plurality of spacers.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Kangguo Cheng, Peng Xu
  • Patent number: 10211208
    Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Anand S. Murthy, Tahir Ghani, Willy Rachmady, Chandra S. Mohapatra, Jack T. Kavalieros, Glenn A. Glass
  • Patent number: 10204904
    Abstract: A method, apparatus and system are disclosed herein for a finFET device having an air gap spacer and/or a tapered bottom dielectric spacer for reducing parasitic capacitance. A first source/drain (S/D) region is formed on a substrate. A set of fin structures are formed above the first S/D region. A gate region is formed above the first S/D region and adjacent at least a portion of the fin structures. A space for an air gap is formed above the gate region. A top epitaxial (EPI) feature is formed extending over the space for the air gap, thereby forming an air gap spacer between the top epitaxial feature and the gate region.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Rinus Tek Po Lee
  • Patent number: 10204857
    Abstract: A method is disclosed that includes disposing a first conductive metal segment; disposing a second conductive metal segment over an active area; disposing a local conductive segment to couple the first conductive metal segment and the second conductive metal segment; disposing a first conductive via on the first conductive metal segment; and disposing a first conductive line coupled to the first conductive metal segment through the first conductive via.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
  • Patent number: 10199304
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 5, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Patent number: 10193307
    Abstract: Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: January 29, 2019
    Assignee: Acorn Technologies, Inc.
    Inventors: Paul A. Clifton, Andreas Goebel, R. Stockton Gaines
  • Patent number: 10192983
    Abstract: An LDFET is disclosed. A source region is electrically coupled to a source contact. A lightly doped drain (LDD) region has a lower dopant concentration than the source region, and is separated from the source region by a channel. A highly doped drain region forms an electrically conductive path between a drain contact and the LDD region. A gate electrode is located above the channel and separated from the channel by a gate dielectric. A shield plate is located above the gate electrode and the LDD region, and is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. A control circuit applies a variable voltage to the shield plate that: (1) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: January 29, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: George Imthurn, James Douglas Ballard, Yashodhan Vijay Moghe
  • Patent number: 10192888
    Abstract: FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance. Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Pranita Kerber, Alexander Reznicek, Joshua M. Rubin
  • Patent number: 10181511
    Abstract: A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Georg Ehrentraut, Franz Hirler, Maximilian Roesch
  • Patent number: 10170587
    Abstract: A semiconductor structure includes a source drain region of a first material and an extension region of a second material. A semiconductor device fabrication process includes forming a sacrificial dielectric portion upon a semiconductor substrate, forming a sacrificial gate stack upon the sacrificial dielectric portion, forming a gate spacer upon the sacrificial dielectric portion against the sacrificial gate, forming a source drain region of a first doped material upon the semiconductor substrate against the gate spacer, forming a replacement gate trench by removing the sacrificial gate stack, forming an extension trench by removing the sacrificial dielectric portion, and forming an extension region of a second doped material within the extension trench.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10170558
    Abstract: A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10157999
    Abstract: A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung, Carlos H Diaz
  • Patent number: 10157981
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a first conductive type well region in the substrate, and a second conductive type well region in the substrate. The first conductive type is different from the second conductive type. The first conductive type well region partially overlaps the second conductive type well region in an overlapping region. The semiconductor device structure also includes a source portion in the first conductive type well region and a drain portion in the second conductive type well region. The semiconductor device structure further includes a gate structure over the substrate and the overlapping region, and between the source portion and the drain portion. The semiconductor device structure further includes a first conductive type doping region in the first conductive type well region and the overlapping region.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Tseng, Chia-Pin Hung, Ming-Hsien Chen
  • Patent number: 10153365
    Abstract: A semiconductor device and a method of making a semiconductor device. The device includes a semiconductor substrate having a first conductivity type, a layer of doped silicon located on the substrate, a trench extending into the layer of silicon, and a gate electrode and gate dielectric located in the trench. The device also includes a drain region, a body region having a second conductivity type located adjacent the trench and above the drain region, and a source region having the first conductivity type located adjacent the trench and above the body region. The layer of doped silicon in a region located beneath the body region includes donor ions and acceptor ions forming a net doping concentration within said region by compensation. The net doping concentration of the layer of doped silicon as a function of depth has a minimum in a region located immediately beneath the body region.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: December 11, 2018
    Assignee: Nexperia B.V.
    Inventors: Steven Thomas Peake, Philip Rutter, Chris Rogers
  • Patent number: 10121786
    Abstract: In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Robert H. Dennard, Isaac Lauer, Ramachandran Muralidhar, Ghavam G. Shahidi
  • Patent number: 10090404
    Abstract: A semiconductor device according to the present invention includes a first conductive-type semiconductor layer, a second conductive-type base region that is arranged in the front surface portion of the semiconductor layer, a plurality of trenches that extend from a front surface of the semiconductor layer beyond a bottom portion of the base region with an active region being defined therebetween, a plurality of first conductive-type emitter regions that are arranged in the active region, each connecting the trenches adjacent to each other, a gate electrode that is embedded in the trench, an embedding insulating film that is embedded in the trench on the gate electrode and that has an upper surface in the same height position as the front surface of the semiconductor layer or in a height position lower than the front surface and an emitter electrode that covers the active region and the embedding insulating film and that is electrically connected to the base region and the emitter region.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 2, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Akihiro Hikasa
  • Patent number: 10074735
    Abstract: A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 11, 2018
    Assignee: D3 Semiconductor LLC
    Inventors: Thomas E. Harrington, III, Zhijun Qu
  • Patent number: 10056486
    Abstract: Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a channel region over the Si fin including a dummy gate with a spacer on each side; forming S/D regions at opposite ends of the Si fin; removing the dummy gate, forming a cavity; thinning sidewalls of the Si fin; and forming a high-k/metal gate in the cavity.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shesh Mani Pandey, Pei Zhao, Zhenyu Hu
  • Patent number: 10050107
    Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10026657
    Abstract: A method is provided for producing at least one first transistor and at least one second transistor on the same substrate, including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing at least one first protective layer on the first and the second gate patterns; depositing, on the first and the second gate patterns, at least a first protective layer and a second protective layer overlying the first protective layer, the second protective layer being made from a different material than that of the first protective layer; masking the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 17, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Laurent Grenouillet
  • Patent number: 10008267
    Abstract: The present disclosure relates to semiconductor devices and discloses a method for operating a flash memory. When a read operation is performed on a flash memory unit, a potential of a first control line connected to gates of select gate PMOS transistors located in a same row is switched from a positive supply voltage to 0V. Since it is not required to switch the potential from a positive voltage to a negative voltage, the power consumption of the pump circuit is significantly reduced. In addition, a read current of the flash memory unit selected for reading can accurately represent the status of the unit being read thanks to the appropriate settings of the gate oxide layer thickness and the threshold voltage of the select gate PMOS transistor. Furthermore, high-voltage devices are removed from the read path and only low-voltage devices are used, so that the reading speed can be significantly improved during the read operation.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 26, 2018
    Assignee: Integrated Silicon Solution (Shanghai), Inc.
    Inventors: Anxing Shen, Jianhui Xie, Chih-Kuang Lin
  • Patent number: 9997640
    Abstract: Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 12, 2018
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Zhijiong Luo
  • Patent number: 9991359
    Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: June 5, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Alexander Reznicek
  • Patent number: 9984936
    Abstract: A method includes forming a sacrificial gate and a stack of materials above a semiconductor substrate, forming a trench in each of the source/drain areas of the device, wherein each trench extends into the semiconductor substrate, forming an empty space under the sacrificial gate structure, the empty space being vertically positioned between the stack of materials and the semiconductor substrate, wherein the empty space is in communication with the trenches, performing a conformal deposition process so as to deposit a conformal layer of a device isolation material adjacent at least the sacrificial gate while at least partially filling the empty space and substantially filling the trenches, and performing a recess etching process to remove at least portions of the conformal layer positioned adjacent the sacrificial gate, thereby defining a recessed upper surface of the device isolation material.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 29, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Siva P. Adusumilli, Kangguo Cheng, Pietro Montanini, Robinhsinku Chao
  • Patent number: 9984930
    Abstract: A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 29, 2018
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Stefan Tegen, Marko Lemke
  • Patent number: 9972676
    Abstract: A silicon carbide semiconductor device includes: a drift layer of a first conductivity type made of silicon carbide; a well region of a second conductivity type formed on the drift layer; a source region of a first conductivity type formed on the well region; a gate insulating film formed on an inner wall of a trench extending from a front surface of the source region through the well region, at least a part of a side surface of the gate insulating film being in contact with the drift layer; a gate electrode formed in the trench with the gate insulating film therebetween; a protective layer of the second conductivity type formed in the drift layer; and a depletion suppressing layer of the first conductivity type formed in the drift layer so as to be in contact with a side surface of the protective layer.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: May 15, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Rina Tanaka, Yasuhiro Kagawa, Naruhisa Miura, Yuji Ebiike
  • Patent number: 9972772
    Abstract: The present disclosure relates to a memory cell structure, a method of manufacturing a memory, and a memory apparatus that are capable of providing a memory cell structure of an MRAM, which reduces resistance of drawn wiring to be connected to an MTJ, reduces an area of a memory cell, and avoids performance degradation of the MTJ due to heat. A memory cell includes: a transistor that uses a first diffusion layer formed in a bottom portion of a concave portion formed by processing a silicon substrate into a groove shape, and a second diffusion layer formed in upper end portions of two opposing sidewall portions of the concave portion, to form channels at portions between the first diffusion layer and the second diffusion layer in the two sidewall portions; and a memory element that is disposed below the first diffusion layer. The first diffusion layer is electrically connected to the memory element via a contact formed after the silicon substrate is thinned.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: May 15, 2018
    Assignee: Sony Corporation
    Inventors: Taku Umebayashi, Shunichi Sukegawa, Takashi Yokoyama, Masanori Hosomi, Yutaka Higo